Lines Matching refs:con
154 u32 con, sel, rate; in rk3588_center_get_clk() local
158 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
159 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
171 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
172 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
184 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
185 sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
197 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
198 sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
286 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
290 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
291 div = (con & ACLK_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
293 sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >> in rk3588_top_get_clk()
301 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
302 div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
304 sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >> in rk3588_top_get_clk()
312 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
313 sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT; in rk3588_top_get_clk()
383 u32 sel, con; in rk3588_i2c_get_clk() local
388 con = readl(&cru->pmuclksel_con[3]); in rk3588_i2c_get_clk()
389 sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT; in rk3588_i2c_get_clk()
392 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
393 sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; in rk3588_i2c_get_clk()
396 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
397 sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; in rk3588_i2c_get_clk()
400 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
401 sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT; in rk3588_i2c_get_clk()
404 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
405 sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT; in rk3588_i2c_get_clk()
408 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
409 sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT; in rk3588_i2c_get_clk()
412 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
413 sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT; in rk3588_i2c_get_clk()
416 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
417 sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT; in rk3588_i2c_get_clk()
420 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
421 sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT; in rk3588_i2c_get_clk()
492 u32 sel, con; in rk3588_spi_get_clk() local
494 con = readl(&cru->clksel_con[59]); in rk3588_spi_get_clk()
498 sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; in rk3588_spi_get_clk()
501 sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; in rk3588_spi_get_clk()
504 sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; in rk3588_spi_get_clk()
507 sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; in rk3588_spi_get_clk()
510 sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT; in rk3588_spi_get_clk()
577 u32 sel, con; in rk3588_pwm_get_clk() local
581 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
582 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3588_pwm_get_clk()
585 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
586 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; in rk3588_pwm_get_clk()
589 con = readl(&cru->clksel_con[60]); in rk3588_pwm_get_clk()
590 sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; in rk3588_pwm_get_clk()
593 con = readl(&cru->pmuclksel_con[2]); in rk3588_pwm_get_clk()
594 sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT; in rk3588_pwm_get_clk()
656 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
660 con = readl(&cru->clksel_con[40]); in rk3588_adc_get_clk()
661 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3588_adc_get_clk()
662 sel = (con & CLK_SARADC_SEL_MASK) >> in rk3588_adc_get_clk()
670 con = readl(&cru->clksel_con[41]); in rk3588_adc_get_clk()
671 div = (con & CLK_TSADC_DIV_MASK) >> in rk3588_adc_get_clk()
673 sel = (con & CLK_TSADC_SEL_MASK) >> in rk3588_adc_get_clk()
747 u32 sel, con, div, prate; in rk3588_mmc_get_clk() local
751 con = readl(&cru->clksel_con[172]); in rk3588_mmc_get_clk()
752 div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT; in rk3588_mmc_get_clk()
753 sel = (con & CCLK_SDIO_SRC_SEL_MASK) >> in rk3588_mmc_get_clk()
763 con = readl(&cru->clksel_con[77]); in rk3588_mmc_get_clk()
764 div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
765 sel = (con & CCLK_EMMC_SEL_MASK) >> in rk3588_mmc_get_clk()
775 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
776 div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
777 sel = (con & BCLK_EMMC_SEL_MASK) >> in rk3588_mmc_get_clk()
785 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
786 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rk3588_mmc_get_clk()
787 sel = (con & SCLK_SFC_SEL_MASK) >> in rk3588_mmc_get_clk()
797 con = readl(&cru->clksel_con[62]); in rk3588_mmc_get_clk()
798 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; in rk3588_mmc_get_clk()
799 sel = (con & DCLK_DECOM_SEL_MASK) >> in rk3588_mmc_get_clk()
901 u32 div, con, parent; in rk3588_aux16m_get_clk() local
904 con = readl(&cru->clksel_con[117]); in rk3588_aux16m_get_clk()
908 div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT; in rk3588_aux16m_get_clk()
911 div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT; in rk3588_aux16m_get_clk()
950 u32 div, sel, con, parent; in rk3588_aclk_vop_get_clk() local
955 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
956 div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT; in rk3588_aclk_vop_get_clk()
957 sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT; in rk3588_aclk_vop_get_clk()
970 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
971 sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >> in rk3588_aclk_vop_get_clk()
982 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
983 sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT; in rk3588_aclk_vop_get_clk()
1064 u32 div, sel, con, parent; in rk3588_dclk_vop_get_clk() local
1069 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1070 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1071 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1075 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1076 div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1077 sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1081 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_get_clk()
1082 div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1083 sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1086 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_get_clk()
1087 div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1088 sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1114 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3588_dclk_vop_set_clk() local
1121 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1122 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1130 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1131 sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1139 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_set_clk()
1140 sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1147 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_set_clk()
1148 sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1226 u32 div, sel, con, parent; in rk3588_clk_csihost_get_clk() local
1230 con = readl(&cru->clksel_con[114]); in rk3588_clk_csihost_get_clk()
1233 con = readl(&cru->clksel_con[115]); in rk3588_clk_csihost_get_clk()
1239 div = (con & CLK_DSIHOST_DIV_MASK) >> CLK_DSIHOST_DIV_SHIFT; in rk3588_clk_csihost_get_clk()
1240 sel = (con & CLK_DSIHOST_SEL_MASK) >> CLK_DSIHOST_SEL_SHIFT; in rk3588_clk_csihost_get_clk()
1257 u32 con, div; in rk3588_gmac_get_clk() local
1261 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1262 div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1265 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1266 div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1269 con = readl(&cru->clksel_con[83]); in rk3588_gmac_get_clk()
1270 div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT; in rk3588_gmac_get_clk()
1273 con = readl(&cru->clksel_con[84]); in rk3588_gmac_get_clk()
1274 div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT; in rk3588_gmac_get_clk()
1325 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3588_uart_get_rate() local
1359 con = readl(&cru->clksel_con[reg + 2]); in rk3588_uart_get_rate()
1360 src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT; in rk3588_uart_get_rate()
1361 con = readl(&cru->clksel_con[reg]); in rk3588_uart_get_rate()
1362 div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT; in rk3588_uart_get_rate()
1363 p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT; in rk3588_uart_get_rate()
1462 u32 con, div, src; in rk3588_pciephy_get_rate() local
1466 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1467 src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1468 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1469 div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1472 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1473 src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1474 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1475 div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1478 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1479 src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1480 div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()