| #
41bb8b73 |
| 07-Apr-2020 |
Joseph Chen <chenjh@rock-chips.com> |
Merge branch 'next-dev' into thunder-boot
Conflicts:
common/spl/spl_rkfw.c
drivers/pinctrl/pinctrl-rockchip.c
make.sh
Change-Id: I93f4dbe1e067c3b938bf64c4964bd5e7023b1daf
Signed-off-by: Joseph C
Merge branch 'next-dev' into thunder-boot
Conflicts:
common/spl/spl_rkfw.c
drivers/pinctrl/pinctrl-rockchip.c
make.sh
Change-Id: I93f4dbe1e067c3b938bf64c4964bd5e7023b1daf
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
show more ...
|
| #
3732e2b8 |
| 17-Mar-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk1808: enable saradc in spl
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iaf91ec37624b3cd2dd7328ae8eb082236a40f83e
|
| #
1a4f6af8 |
| 02-Mar-2020 |
Joseph Chen <chenjh@rock-chips.com> |
Merge branch 'next-dev' into thunder-boot
|
| #
c2fb06de |
| 21-Feb-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: Restore mmc/sfc frequency after PLL frequency setting
Change-Id: I14d0f9c41c45253de3a71b7c3d3fdae89ddf9952
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
28e9e98a |
| 17-Feb-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: Id356c87b1db158a0638e4560e886
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: Id356c87b1db158a0638e4560e886868f133dfaf9
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
show more ...
|
| #
20769c64 |
| 06-Dec-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: Restore crypto frequency after PLL frequency setting
Change-Id: I4821309bfe1a2333469eae1d92f1d7716ea6635e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
a9f7ad7f |
| 25-Sep-2019 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: I28f56f161eb40cf640f7d979f53f
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: I28f56f161eb40cf640f7d979f53f8e6fdaff957c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
show more ...
|
| #
32f0452d |
| 01-Jul-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: support crypto clk get/set rate
Change-Id: Id09bd7e6a303bc3e72421aeef277a16805e95761
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
6b5ade5a |
| 10-Apr-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: fix up the clk_set_default failed
Change-Id: If49d6def0e16b93238311885217f30a4b7a2e7c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
b9f59722 |
| 14-Mar-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: add mac clk interface
support mac clk set rate and set parent.
Change-Id: I3b4626fd3fcc5ffdf3c58add9c1bc002bb56429a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
68d8964c |
| 09-Apr-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: support pclk_wdt get rate
Change-Id: Ib204b4c014c3b4cbd35d1f335378b0b399689303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
ed6f5d94 |
| 22-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: print arm enter and init rate
Change-Id: I14f0b0c95b1367266fe9c64050a602ad58208d53
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
6259b22e |
| 25-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: add pll 100M config parameters
PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6,
postdiv2=6, vco= 3.6G, is best for pcie.
Change-Id: Ie9fddbb32baa0d4b8883b399b0e903b83afc820f
clk: rockchip: rk1808: add pll 100M config parameters
PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6,
postdiv2=6, vco= 3.6G, is best for pcie.
Change-Id: Ie9fddbb32baa0d4b8883b399b0e903b83afc820f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
fab09610 |
| 11-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: Support dclk_voplite to set any of the frequencies
Change-Id: I7ac53f75244388e7fb448a721e55b6b1e789d4d7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
1ae6d6e5 |
| 10-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: fix up the dclk_raw/lite set rate error
Change-Id: I0b8c7d0e15501c7ecc3c5acb0e0844e722ad18ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
dad14895 |
| 06-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: support pclk_pmu freq setting
set pclk_pmu freq before ppll freq setting.
Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chi
clk: rockchip: rk1808: support pclk_pmu freq setting
set pclk_pmu freq before ppll freq setting.
Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
cb3c37fc |
| 19-Sep-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: support clk_tsadc setting freq
Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
45a3782a |
| 06-Aug-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|