273 	u32 con;  in rkclk_pll_get_rate()  local
282 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
284 	switch ((con >> shift) & CRU_MODE_MASK) {  in rkclk_pll_get_rate()
289 		con = readl(&pll->con0);  in rkclk_pll_get_rate()
290 		no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;  in rkclk_pll_get_rate()
291 		nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;  in rkclk_pll_get_rate()
292 		con = readl(&pll->con1);  in rkclk_pll_get_rate()
293 		nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;  in rkclk_pll_get_rate()
448 		u32 con = readl(&cru->cru_clksel_con[21]);  in rockchip_mac_set_clk()  local
452 		if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==  in rockchip_mac_set_clk()
455 		else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==  in rockchip_mac_set_clk()
719 	u32 con;  in rockchip_mmc_get_clk()  local
725 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
726 		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;  in rockchip_mmc_get_clk()
727 		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;  in rockchip_mmc_get_clk()
731 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
732 		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;  in rockchip_mmc_get_clk()
733 		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;  in rockchip_mmc_get_clk()
737 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
738 		mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;  in rockchip_mmc_get_clk()
739 		div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;  in rockchip_mmc_get_clk()
803 	u32 con;  in rockchip_spi_get_clk()  local
807 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
808 		mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;  in rockchip_spi_get_clk()
809 		div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;  in rockchip_spi_get_clk()
812 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
813 		mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;  in rockchip_spi_get_clk()
814 		div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;  in rockchip_spi_get_clk()
817 		con = readl(&cru->cru_clksel_con[39]);  in rockchip_spi_get_clk()
818 		mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;  in rockchip_spi_get_clk()
819 		div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;  in rockchip_spi_get_clk()
866 	u32 con;  in rockchip_aclk_peri_get_clk()  local
869 	con = readl(&cru->cru_clksel_con[10]);  in rockchip_aclk_peri_get_clk()
870 	mux = (con & PERI_SEL_PLL_MASK) >> PERI_SEL_PLL_SHIFT;  in rockchip_aclk_peri_get_clk()
871 	div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;  in rockchip_aclk_peri_get_clk()
884 	u32 con;  in rockchip_aclk_cpu_get_clk()  local
887 	con = readl(&cru->cru_clksel_con[1]);  in rockchip_aclk_cpu_get_clk()
888 	mux = (con & PD_BUS_SEL_PLL_MASK) >> PD_BUS_SEL_PLL_SHIFT;  in rockchip_aclk_cpu_get_clk()
889 	div = (con & PD_BUS_ACLK_DIV0_MASK) >> PD_BUS_ACLK_DIV0_SHIFT;  in rockchip_aclk_cpu_get_clk()
896 	div = (con & PD_BUS_ACLK_DIV1_MASK) >> PD_BUS_ACLK_DIV1_SHIFT;  in rockchip_aclk_cpu_get_clk()
905 	u32 con;  in rockchip_pclk_peri_get_clk()  local
909 	con = readl(&cru->cru_clksel_con[10]);  in rockchip_pclk_peri_get_clk()
910 	div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;  in rockchip_pclk_peri_get_clk()
919 	u32 con;  in rockchip_pclk_cpu_get_clk()  local
923 	con = readl(&cru->cru_clksel_con[1]);  in rockchip_pclk_cpu_get_clk()
924 	div = (con & PD_BUS_PCLK_DIV_MASK) >> PD_BUS_PCLK_DIV_SHIFT;  in rockchip_pclk_cpu_get_clk()
1026 	u32 div, con, parent;  in rk3288_alive_get_clk()  local
1028 	con = readl(&cru->cru_clksel_con[33]);  in rk3288_alive_get_clk()
1029 	div = (con & PCLK_ALIVE_DIV_CON_MASK) >>  in rk3288_alive_get_clk()