Lines Matching refs:con
172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
176 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
177 sel = (con & ACLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
179 div = (con & ACLK_BUS_ROOT_DIV_MASK) >> in rk3576_bus_get_clk()
187 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
188 sel = (con & HCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
200 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
201 sel = (con & PCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
278 u32 con, sel, div, rate, prate; in rk3576_top_get_clk() local
282 con = readl(&cru->clksel_con[9]); in rk3576_top_get_clk()
283 div = (con & ACLK_TOP_DIV_MASK) >> in rk3576_top_get_clk()
285 sel = (con & ACLK_TOP_SEL_MASK) >> in rk3576_top_get_clk()
295 con = readl(&cru->clksel_con[10]); in rk3576_top_get_clk()
296 div = (con & ACLK_TOP_MID_DIV_MASK) >> in rk3576_top_get_clk()
298 sel = (con & ACLK_TOP_MID_SEL_MASK) >> in rk3576_top_get_clk()
306 con = readl(&cru->clksel_con[8]); in rk3576_top_get_clk()
307 sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT; in rk3576_top_get_clk()
316 con = readl(&cru->clksel_con[19]); in rk3576_top_get_clk()
317 sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT; in rk3576_top_get_clk()
407 u32 sel, con; in rk3576_i2c_get_clk() local
412 con = readl(&cru->pmuclksel_con[6]); in rk3576_i2c_get_clk()
413 sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT; in rk3576_i2c_get_clk()
416 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
417 sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; in rk3576_i2c_get_clk()
420 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
421 sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; in rk3576_i2c_get_clk()
424 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
425 sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT; in rk3576_i2c_get_clk()
428 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
429 sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT; in rk3576_i2c_get_clk()
432 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
433 sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT; in rk3576_i2c_get_clk()
436 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
437 sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT; in rk3576_i2c_get_clk()
440 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
441 sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT; in rk3576_i2c_get_clk()
444 con = readl(&cru->clksel_con[57]); in rk3576_i2c_get_clk()
445 sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT; in rk3576_i2c_get_clk()
448 con = readl(&cru->clksel_con[58]); in rk3576_i2c_get_clk()
449 sel = (con & CLK_I2C9_SEL_MASK) >> CLK_I2C9_SEL_SHIFT; in rk3576_i2c_get_clk()
532 u32 sel, con; in rk3576_spi_get_clk() local
536 con = readl(&cru->clksel_con[70]); in rk3576_spi_get_clk()
537 sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; in rk3576_spi_get_clk()
540 con = readl(&cru->clksel_con[71]); in rk3576_spi_get_clk()
541 sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; in rk3576_spi_get_clk()
544 con = readl(&cru->clksel_con[71]); in rk3576_spi_get_clk()
545 sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; in rk3576_spi_get_clk()
548 con = readl(&cru->clksel_con[71]); in rk3576_spi_get_clk()
549 sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; in rk3576_spi_get_clk()
552 con = readl(&cru->clksel_con[71]); in rk3576_spi_get_clk()
553 sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT; in rk3576_spi_get_clk()
624 u32 sel, con; in rk3576_pwm_get_clk() local
628 con = readl(&cru->clksel_con[71]); in rk3576_pwm_get_clk()
629 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3576_pwm_get_clk()
632 con = readl(&cru->clksel_con[74]); in rk3576_pwm_get_clk()
633 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; in rk3576_pwm_get_clk()
636 con = readl(&cru->pmuclksel_con[5]); in rk3576_pwm_get_clk()
637 sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT; in rk3576_pwm_get_clk()
694 u32 div, sel, con, prate; in rk3576_adc_get_clk() local
698 con = readl(&cru->clksel_con[58]); in rk3576_adc_get_clk()
699 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3576_adc_get_clk()
700 sel = (con & CLK_SARADC_SEL_MASK) >> in rk3576_adc_get_clk()
708 con = readl(&cru->clksel_con[59]); in rk3576_adc_get_clk()
709 div = (con & CLK_TSADC_DIV_MASK) >> in rk3576_adc_get_clk()
765 u32 sel, con, prate, div = 0; in rk3576_mmc_get_clk() local
770 con = readl(&cru->clksel_con[104]); in rk3576_mmc_get_clk()
771 div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT; in rk3576_mmc_get_clk()
772 sel = (con & CCLK_SDIO_SRC_SEL_MASK) >> in rk3576_mmc_get_clk()
783 con = readl(&cru->clksel_con[105]); in rk3576_mmc_get_clk()
784 div = (con & CCLK_SDMMC0_SRC_DIV_MASK) >> CCLK_SDMMC0_SRC_DIV_SHIFT; in rk3576_mmc_get_clk()
785 sel = (con & CCLK_SDMMC0_SRC_SEL_MASK) >> in rk3576_mmc_get_clk()
796 con = readl(&cru->clksel_con[89]); in rk3576_mmc_get_clk()
797 div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; in rk3576_mmc_get_clk()
798 sel = (con & CCLK_EMMC_SEL_MASK) >> in rk3576_mmc_get_clk()
808 con = readl(&cru->clksel_con[90]); in rk3576_mmc_get_clk()
809 sel = (con & BCLK_EMMC_SEL_MASK) >> in rk3576_mmc_get_clk()
821 con = readl(&cru->clksel_con[89]); in rk3576_mmc_get_clk()
822 div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT; in rk3576_mmc_get_clk()
823 sel = (con & SCLK_FSPI_SEL_MASK) >> in rk3576_mmc_get_clk()
833 con = readl(&cru->clksel_con[106]); in rk3576_mmc_get_clk()
834 div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT; in rk3576_mmc_get_clk()
835 sel = (con & SCLK_FSPI_SEL_MASK) >> in rk3576_mmc_get_clk()
845 con = readl(&cru->clksel_con[72]); in rk3576_mmc_get_clk()
846 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; in rk3576_mmc_get_clk()
847 sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; in rk3576_mmc_get_clk()
972 u32 div, sel, con, parent = 0; in rk3576_aclk_vop_get_clk() local
977 con = readl(&cru->clksel_con[144]); in rk3576_aclk_vop_get_clk()
978 div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT; in rk3576_aclk_vop_get_clk()
979 sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
992 con = readl(&cru->clksel_con[149]); in rk3576_aclk_vop_get_clk()
993 div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT; in rk3576_aclk_vop_get_clk()
994 sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1005 con = readl(&cru->clksel_con[158]); in rk3576_aclk_vop_get_clk()
1006 div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT; in rk3576_aclk_vop_get_clk()
1007 sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1018 con = readl(&cru->clksel_con[144]); in rk3576_aclk_vop_get_clk()
1019 sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1029 con = readl(&cru->clksel_con[144]); in rk3576_aclk_vop_get_clk()
1030 sel = (con & PCLK_VOP_ROOT_SEL_MASK) >> PCLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1131 u32 div, sel, con, parent; in rk3576_dclk_vop_get_clk() local
1136 con = readl(&cru->clksel_con[145]); in rk3576_dclk_vop_get_clk()
1137 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_get_clk()
1138 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1142 con = readl(&cru->clksel_con[146]); in rk3576_dclk_vop_get_clk()
1143 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_get_clk()
1144 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1148 con = readl(&cru->clksel_con[147]); in rk3576_dclk_vop_get_clk()
1149 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_get_clk()
1150 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1177 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_vop_set_clk() local
1184 con = readl(&cru->clksel_con[conid]); in rk3576_dclk_vop_set_clk()
1185 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1193 con = readl(&cru->clksel_con[conid]); in rk3576_dclk_vop_set_clk()
1194 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1202 con = readl(&cru->clksel_con[conid]); in rk3576_dclk_vop_set_clk()
1203 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1286 u32 div, sel, con, parent; in rk3576_clk_csihost_get_clk() local
1290 con = readl(&cru->clksel_con[151]); in rk3576_clk_csihost_get_clk()
1291 div = (con & CLK_DSIHOST0_DIV_MASK) >> CLK_DSIHOST0_DIV_SHIFT; in rk3576_clk_csihost_get_clk()
1292 sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT; in rk3576_clk_csihost_get_clk()
1319 u32 i, con, div, best_div = 0, best_sel = 0; in rk3576_clk_csihost_set_clk() local
1324 con = 151; in rk3576_clk_csihost_set_clk()
1370 rk_clrsetreg(&cru->clksel_con[con], in rk3576_clk_csihost_set_clk()
1384 u32 div, sel, con, parent; in rk3576_dclk_ebc_get_clk() local
1389 con = readl(&cru->clksel_con[123]); in rk3576_dclk_ebc_get_clk()
1390 div = (con & DCLK_EBC_DIV_MASK) >> DCLK_EBC_DIV_SHIFT; in rk3576_dclk_ebc_get_clk()
1391 sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; in rk3576_dclk_ebc_get_clk()
1408 con = readl(&cru->clksel_con[123]); in rk3576_dclk_ebc_get_clk()
1410 sel = (con & DCLK_EBC_FRAC_SRC_SEL_MASK) >> DCLK_EBC_FRAC_SRC_SEL_SHIFT; in rk3576_dclk_ebc_get_clk()
1437 u32 i, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_ebc_set_clk() local
1442 con = readl(&cru->clksel_con[123]); in rk3576_dclk_ebc_set_clk()
1443 sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; in rk3576_dclk_ebc_set_clk()
1561 u32 con, div, src, p_rate; in rk3576_gmac_get_clk() local
1566 con = readl(&cru->clksel_con[105]); in rk3576_gmac_get_clk()
1567 div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; in rk3576_gmac_get_clk()
1568 src = (con & CLK_GMAC0_PTP_SEL_MASK) >> CLK_GMAC0_PTP_SEL_SHIFT; in rk3576_gmac_get_clk()
1578 con = readl(&cru->clksel_con[104]); in rk3576_gmac_get_clk()
1579 div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; in rk3576_gmac_get_clk()
1580 src = (con & CLK_GMAC1_PTP_SEL_MASK) >> CLK_GMAC1_PTP_SEL_SHIFT; in rk3576_gmac_get_clk()
1589 con = readl(&cru->clksel_con[30]); in rk3576_gmac_get_clk()
1590 div = (con & CLK_GMAC0_125M_DIV_MASK) >> CLK_GMAC0_125M_DIV_SHIFT; in rk3576_gmac_get_clk()
1593 con = readl(&cru->clksel_con[31]); in rk3576_gmac_get_clk()
1594 div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT; in rk3576_gmac_get_clk()
1665 u32 reg, con, fracdiv, p_src, p_rate; in rk3576_uart_frac_get_rate() local
1681 con = readl(&cru->clksel_con[reg + 1]); in rk3576_uart_frac_get_rate()
1682 p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT; in rk3576_uart_frac_get_rate()
1764 u32 con, div, src, p_rate; in rk3576_uart_get_rate() local
1768 con = readl(&cru->clksel_con[60]); in rk3576_uart_get_rate()
1771 con = readl(&cru->pmuclksel_con[8]); in rk3576_uart_get_rate()
1772 src = (con & CLK_UART1_SEL_MASK) >> CLK_UART1_SEL_SHIFT; in rk3576_uart_get_rate()
1775 con = readl(&cru->clksel_con[27]); in rk3576_uart_get_rate()
1778 con = readl(&cru->clksel_con[61]); in rk3576_uart_get_rate()
1781 con = readl(&cru->clksel_con[62]); in rk3576_uart_get_rate()
1784 con = readl(&cru->clksel_con[63]); in rk3576_uart_get_rate()
1787 con = readl(&cru->clksel_con[64]); in rk3576_uart_get_rate()
1790 con = readl(&cru->clksel_con[65]); in rk3576_uart_get_rate()
1793 con = readl(&cru->clksel_con[66]); in rk3576_uart_get_rate()
1796 con = readl(&cru->clksel_con[67]); in rk3576_uart_get_rate()
1799 con = readl(&cru->clksel_con[68]); in rk3576_uart_get_rate()
1802 con = readl(&cru->clksel_con[69]); in rk3576_uart_get_rate()
1805 con = readl(&cru->clksel_con[70]); in rk3576_uart_get_rate()
1811 src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT; in rk3576_uart_get_rate()
1812 div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT; in rk3576_uart_get_rate()
1814 src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT; in rk3576_uart_get_rate()
1815 div = (con & CLK_UART_DIV_MASK) >> CLK_UART_DIV_SHIFT; in rk3576_uart_get_rate()
1929 u32 reg, con, div, src, p_rate; in rk3576_ref_clkout_get_clk() local
1944 con = readl(&cru->clksel_con[reg]); in rk3576_ref_clkout_get_clk()
1945 div = (con & REF_CLK0_OUT_PLL_DIV_MASK) >> REF_CLK0_OUT_PLL_DIV_SHIFT; in rk3576_ref_clkout_get_clk()
1946 src = (con & REF_CLK0_OUT_PLL_SEL_MASK) >> REF_CLK0_OUT_PLL_SEL_SHIFT; in rk3576_ref_clkout_get_clk()
1967 u32 i, con, div, best_div = 0, best_sel = 0; in rk3576_ref_clkout_set_clk() local
1971 con = 33; in rk3576_ref_clkout_set_clk()
1974 con = 34; in rk3576_ref_clkout_set_clk()
1977 con = 35; in rk3576_ref_clkout_set_clk()
2021 rk_clrsetreg(&cru->clksel_con[con], in rk3576_ref_clkout_set_clk()