Lines Matching refs:con
251 uint32_t con; in rkclk_pll_get_rate() local
260 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
262 switch ((con >> shift) & APLL_MODE_MASK >> APLL_MODE_SHIFT) { in rkclk_pll_get_rate()
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
268 no = ((con >> CLKOD_SHIFT) & (CLKOD_MASK >> CLKOD_SHIFT)) + 1; in rkclk_pll_get_rate()
269 nr = ((con >> CLKR_SHIFT) & (CLKR_MASK >> CLKR_SHIFT)) + 1; in rkclk_pll_get_rate()
270 con = readl(&pll->con1); in rkclk_pll_get_rate()
271 nf = ((con >> CLKF_SHIFT) & (CLKF_MASK >> CLKF_SHIFT)) + 1; in rkclk_pll_get_rate()
284 u32 con; in rockchip_mmc_get_clk() local
288 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
289 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
292 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
293 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK >> MMC0_DIV_SHIFT; in rockchip_mmc_get_clk()
296 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
297 div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK >> SDIO_DIV_SHIFT; in rockchip_mmc_get_clk()
343 u32 con; in rockchip_spi_get_clk() local
347 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
348 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK >> SPI0_DIV_SHIFT; in rockchip_spi_get_clk()
351 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
352 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK >> SPI1_DIV_SHIFT; in rockchip_spi_get_clk()