clk: rockchip: rk3036: support sdio and sdmmc clk setting

Change-Id: I0b27f0a32ab5afce352ad3289738880c883da55a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3036: add support to set and get pwm clock

Change-Id: I896c97bac5fa1e5aa36545fe5dd1a2c73e623baa
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>

clk: rockchip: rk3036: add support to set and get spi clock

Change-Id: I24db5f250fa89845b62005950d520600434adb99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3036: Add support for vop

Change-Id: I0f057350a6ad07f61aaf42c84e50c452ee662f46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Merge branch 'next-dev' into thunder-boot

Change-Id: I35db1f0aa79575e972942b5c366f380fc8106343

clk: rockchip: rk3036: add nandc clk init

Change-Id: I8aefe310a366e346310135f684f3b5db43b0b734
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

clk: rockchip: rk3036: fix up the assert error

Change-Id: Id987e8847dbe97e5502259a9432dac85782769f3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3036: print arm enter and init rate

Change-Id: Ic9212c8a0f1d50006f7121957b8bd5f34d2622d9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3036: Add power down and power up for pll set

If power down and power up were not done, there was an error during
pll setting again.

Change-Id: Iaa5ef558c2bff270614f08d96a70e5c847c

rockchip: clk: rk3036: Add power down and power up for pll set

If power down and power up were not done, there was an error during
pll setting again.

Change-Id: Iaa5ef558c2bff270614f08d96a70e5c847ce927c
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: Get cru's reg address before probe for rk3036

The assigned clock-rate and clock-parent is done before probe,
so it is better to get cru's reg address at ofdata_to_platdata
before prob

clk: rockchip: Get cru's reg address before probe for rk3036

The assigned clock-rate and clock-parent is done before probe,
so it is better to get cru's reg address at ofdata_to_platdata
before probe, otherwise there is a error to use cru's red address.

Change-Id: I7af5faa931352a4ee4a495efa9b80c95066eb5c5
Signed-off-by: David Wu <david.wu@rock-chips.com>

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rockchip: rk3036: clk: update periph hclk/pclk

periph hclk/pclk parent is aclk, not gpll.

Change-Id: Ic59abb7964f5efd627f9b76c13643e2b83af6e96
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co

rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC w

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: rk3036: correct setting for pll integer mode

According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Ke

rockchip: clk: rk3036: correct setting for pll integer mode

According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixe

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

show more ...

rockchip: clock: rk3036: some fix according TRM

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Sig

rockchip: clock: rk3036: some fix according TRM

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: rk3036: clean mask definition for cru reg

Embeded the shift in mask MACRO definition in cru header file
and clock driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by

rockchip: rk3036: clean mask definition for cru reg

Embeded the shift in mask MACRO definition in cru header file
and clock driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing function

dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg

rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip