clk: rockchip: rk3188: fix up the assert error

Change-Id: I690798cd9a17e266c32d702f5b2c8bfdc413d970
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3188: print arm enter and init rate

Change-Id: I604c18050e8ccbbc9aa25ecd8f4379a877239d49
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3188: convert to live dt

Use dev_read_addr_ptr to get cru base

Change-Id: Ib0903a0ec7b0602fb2f78bab65c44db071f13bd0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co

rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: Add rk3188 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I186

clk: rockchip: Add rk3188 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I1869cd06615e037548e77eae65df4acdf666a058
Signed-off-by: David Wu <david.wu@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC w

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing function

dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simo

rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3188: Allow configuration of the armclk

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to

rockchip: clk: rk3188: Allow configuration of the armclk

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it bo

Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).

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rockchip: rk3188: Add clock driver

Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon

rockchip: rk3188: Add clock driver

Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>

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