| #
56e11a8c |
| 17-Mar-2021 |
David Wu <david.wu@rock-chips.com> |
clk: rockchip: Add SCLK_MAC_SRC clock rate setup
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested
by the integrated phy usuage.
Change-Id: Ifc63fa7ff9e9734cd5d59fab38f4cde13afa4183
Sig
clk: rockchip: Add SCLK_MAC_SRC clock rate setup
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested
by the integrated phy usuage.
Change-Id: Ifc63fa7ff9e9734cd5d59fab38f4cde13afa4183
Signed-off-by: David Wu <david.wu@rock-chips.com>
show more ...
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| #
4b495484 |
| 17-Mar-2021 |
David Wu <david.wu@rock-chips.com> |
clk: rockchip: fix the gmac selection of pll source for rk322x
There is a wrong selection for gmac pll source, fix it.
Change-Id: I385a6f1f1dc0b9465ddacf1468c2e62d55f2c649
Signed-off-by: David Wu <
clk: rockchip: fix the gmac selection of pll source for rk322x
There is a wrong selection for gmac pll source, fix it.
Change-Id: I385a6f1f1dc0b9465ddacf1468c2e62d55f2c649
Signed-off-by: David Wu <david.wu@rock-chips.com>
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| #
403d8d4c |
| 09-Jun-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk322x: add support to set and get spi clock
Change-Id: I361aa06aa795d2c041d2bdad9ee5ff6982d554fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
2401c256 |
| 22-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk322x: print arm enter and init rate
Change-Id: Iab7034c8cef09908a99b5a1e396f6e015da350fb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
e9dcade2 |
| 14-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk322x: add clk_set_defaults for clk init
Change-Id: Ie2bcdf77bb7cdeb9c27b482ce70e4af35fbdc8c6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
a7c5f873 |
| 11-Dec-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk322x: support crypto clk setting
Change-Id: Id92acae9424fd0b200f9b4f33982f753f6123207
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
dcb78704 |
| 15-Nov-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk322x: fix up the vop clk setting assert error
Change-Id: Ied72bcb5e92e300eeccd7bfd32285d2eeb4d4860
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
0598134a |
| 02-Nov-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk322x: fix clock assert value
The value after '<' should be max value instead of 'max-1'
Change-Id: I7a1deaa75b8a931631a54e8dfd154c266251c7fc
Signed-off-by: Kever Yang <kever.yang@rock-c
rockchip: rk322x: fix clock assert value
The value after '<' should be max value instead of 'max-1'
Change-Id: I7a1deaa75b8a931631a54e8dfd154c266251c7fc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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|
| #
c93db2f3 |
| 22-Aug-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3229: tpl skip rkclk_init
The new rkclk_init is too complecate and not able to run in TPL,
skip it in TPL.
Change-Id: I46f30613050a86ee74060e713283bcb7980c3348
Signed-off-by: Kever Yang
rockchip: rk3229: tpl skip rkclk_init
The new rkclk_init is too complecate and not able to run in TPL,
skip it in TPL.
Change-Id: I46f30613050a86ee74060e713283bcb7980c3348
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
809e91fd |
| 25-Jul-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk322x: support more clks to set and get rate
Change-Id: Ibed40f1826469263a8015d8af2dea4d3567a08e6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
58996dfc |
| 13-Jan-2018 |
David Wu <david.wu@rock-chips.com> |
clk: rockchip: Add rk322x gamc clock support
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Change-Id: I6405c3b2ead4290841
clk: rockchip: Add rk322x gamc clock support
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Change-Id: I6405c3b2ead429084118c544bcc461e0b301d77a
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| #
cd47f9d7 |
| 24-Jan-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: rk322x: convert to live dt
Change-Id: Ib0943d8f66d24ef36fd0020e468befce42ed5836
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
| #
6442f219 |
| 08-Dec-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: rk322x: update assert for periph hclk/pclk
This is a fix to:
f04b6e2 rockchip: rk322x: fix pd_bus hclk/pclk
Change-Id: Ia57554a8f09e44b576c59c60273247dd7fcef10d
Signed-off-by: Kever
rockchip: clk: rk322x: update assert for periph hclk/pclk
This is a fix to:
f04b6e2 rockchip: rk322x: fix pd_bus hclk/pclk
Change-Id: Ia57554a8f09e44b576c59c60273247dd7fcef10d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
3d555d75 |
| 10-Oct-2017 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: add device_bind_driver_to_node for reset driver
all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.
Change-Id: I03c2a798d211fb4181d5
rockchip: clk: add device_bind_driver_to_node for reset driver
all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.
Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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|
| #
fbdd1558 |
| 25-Oct-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clock: update sysreset driver bingding
Using priv for new sysreset driver binding.
Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co
rockchip: clock: update sysreset driver bingding
Using priv for new sysreset driver binding.
Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
show more ...
|
| #
eecd6f34 |
| 13-Oct-2017 |
Zhangbin Tong <zebulun.tong@rock-chips.com> |
rockchip: clk: Add rk322x bus pclk clock support
Change-Id: I63fcd3527ac2d4447b0f49f4665ca99caa90d6e5
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
|
| #
f04b6e29 |
| 28-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.
Change-Id: I3e83f05f6b5423decb264f917adc91c6b40a6e46
Signed-off-by: Kever Yang <kever.yang@rock-chips
rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.
Change-Id: I3e83f05f6b5423decb264f917adc91c6b40a6e46
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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|
| #
6c9bca3c |
| 27-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: fix typo in rk322x clock driver
Fix typo RK322X/RK3036 in rk322x clock driver.
Change-Id: If06fc94761519c215c6a3ddc3de5f54c8b949c8f
Signed-off-by: Kever Yang <kever.yang@rock-chips.c
rockchip: clk: fix typo in rk322x clock driver
Fix typo RK322X/RK3036 in rk322x clock driver.
Change-Id: If06fc94761519c215c6a3ddc3de5f54c8b949c8f
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
show more ...
|
| #
6c639845 |
| 06-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
Change-Id: I332e9ad79f8f9ce51108d3e914f8e439a5ff8b74
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
| #
c1b62ba9 |
| 14-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
|
| #
217273cd |
| 27-Jul-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| #
3a94d75d |
| 27-Jul-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: update dwmmc clock div
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC w
rockchip: clk: update dwmmc clock div
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| #
d43ef73b |
| 11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
|
| #
045029cb |
| 23-Jun-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Phi
rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|