clk: rockchip: rk3399: set aclk_vio by vop

Change-Id: I7971ae19764f82cbce051111502f8384a1bda1d7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: support crypto clk set/get in SPL

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I159d062320ca523e8dc4f0dcce94a619692481f3

Merge branch 'next-dev' into thunder-boot

Change-Id: I22ac688008080eac49169d752a94b66668f890fc

Conflicts:
drivers/phy/Kconfig
drivers/phy/Makefile

clk: rockchip: rk3399: add usb3.0 host clocks mandatory

This adds clocks mandatory for the DWC3 controllers of RK3399,
as these are enabled by default we just simply return success.

Change-Id: I810

clk: rockchip: rk3399: add usb3.0 host clocks mandatory

This adds clocks mandatory for the DWC3 controllers of RK3399,
as these are enabled by default we just simply return success.

Change-Id: I81006d710cb6b4608c8dfa61a4eef661415bad29
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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Merge branch 'next-dev' into thunder-boot

clk: rockchip: rk3399: init 816 MHz for ARM big core

We don't use clk_set_defaults() to initial it, because
there are too many clocks to be set in "assigned-clock-rates"
which wastes time.

Signed-o

clk: rockchip: rk3399: init 816 MHz for ARM big core

We don't use clk_set_defaults() to initial it, because
there are too many clocks to be set in "assigned-clock-rates"
which wastes time.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6de5e2174945fdbce06e044c390ae2860970b0c4

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Merge branch 'next-dev' into thunder-boot

clk: rk3399: fix up the i2c clk error

I2c MUx is in cpll by default, but cpll is for dclk_vop exclusive.
If dclk_vop set rate after i2c init, the CPLL changed,
but the i2c not perception, it will re

clk: rk3399: fix up the i2c clk error

I2c MUx is in cpll by default, but cpll is for dclk_vop exclusive.
If dclk_vop set rate after i2c init, the CPLL changed,
but the i2c not perception, it will resulting the wrong frequency
of the i2c.
So set the i2c frequency according to the kernel configuration.
and Hang I2C on the GPLL.

Change-Id: I91f891e9033e9d4648027ea253998a54011f4863
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3399: fix up the assert error

Change-Id: I8cc4f6b775243fef1f5c8e2c711eb1b16eac79a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: support pclk_wdt get rate

Change-Id: I8634beb815d5129534c36861c2f02e62669889e9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: print arm enter and init rate

Change-Id: Ib5e3e0f9a3e1a5b535ec852e7c58966dc0db77cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3399: support 50MHz and 400MHz for ddr clock

Change-Id: I9d3a64ce38986f2c48e1f2614bcc274340674aa7
Signed-off-by: YouMin Chen <cym@rock-chips.com>

clk: rockchip: rk3399: support clk dump

add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zh

clk: rockchip: rk3399: support clk dump

add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3399: support crypto clk setting

Change-Id: I12cbaeac250f21d4cb05d8ef3ef0e9238cb3f911
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: support clk_tsadc setting freq

Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-

clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3399: fix assert error

We can not meet the assert condition after we update the code,
fix it so that we can enable the DEBUG option.

Change-Id: I4b3e6b30aae4480ed208f30610493a7d297

rockchip: clk: rk3399: fix assert error

We can not meet the assert condition after we update the code,
fix it so that we can enable the DEBUG option.

Change-Id: I4b3e6b30aae4480ed208f30610493a7d297e90ee
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: rk3399: fix up the pll setting

If the gpll and npll freq is no change,don't set pll once again.

Change-Id: Ib16a0a1ff56560997b6ed4b487fc2d56928c14ec
Signed-off-by: Elaine Zhang <zhan

clk: rockchip: rk3399: fix up the pll setting

If the gpll and npll freq is no change,don't set pll once again.

Change-Id: Ib16a0a1ff56560997b6ed4b487fc2d56928c14ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clock: rk3399: support 400KHZ output for emmc initialization.

support 400KHz output for emmc initialization

Change-Id: I4f2182981f587688c777f64c30d0eeb59f69b0ea
Signed-off-by: chenfen <ch

rockchip: clock: rk3399: support 400KHZ output for emmc initialization.

support 400KHz output for emmc initialization

Change-Id: I4f2182981f587688c777f64c30d0eeb59f69b0ea
Signed-off-by: chenfen <chenfen@rock-chips.com>

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clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@ro

clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3399: fix up the hdmi clk error

make the dclk_vop div=1.

Change-Id: I0faedbd557cddd55f93529d66f2f7815ce4c5f9e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: remove pll init

use the dts node to set rate by:
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <800000000>;

Change-Id: I2a674213509308fcd5ad27239bdf261c428d8027
S

clk: rockchip: rk3399: remove pll init

use the dts node to set rate by:
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <800000000>;

Change-Id: I2a674213509308fcd5ad27239bdf261c428d8027
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3399: add phy 480MHz clks for usb Host0/1

In kernel dtb, the rk3399 usb Host0/1 use SCLK_USBPHY0/1_480M_SRC
in addition to HCLK_HOST0/1 and HCLK_HOST0/1_ARB. This patch adds
the phy

rockchip: clk: rk3399: add phy 480MHz clks for usb Host0/1

In kernel dtb, the rk3399 usb Host0/1 use SCLK_USBPHY0/1_480M_SRC
in addition to HCLK_HOST0/1 and HCLK_HOST0/1_ARB. This patch adds
the phy 480MHz clks for usb Host0/1 to ensure the generic ehci-driver
(ehci-generic.c) to enable the clocks successfully.

Change-Id: I0790e949bca0d7bdc4179f3232b29aa58436593f
Signed-off-by: William Wu <william.wu@rock-chips.com>

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clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cr

clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0_DIV>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&vopl {
status = "okay";
assigned-clocks = <&cru DCLK_VOP1_DIV>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

Change-Id: I07ab4e2837cf7fc0860e8b4d14adb8936f5cb27a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip/rk3399: fixes the correct clock init

We will use the rkclk_init() for rk3399 without SPL/TPL way.

Change-Id: I73a4d694ff2cb0e18f390c293971985f41d2b03d
Signed-off-by: Caesar Wang <wxt@

clk: rockchip/rk3399: fixes the correct clock init

We will use the rkclk_init() for rk3399 without SPL/TPL way.

Change-Id: I73a4d694ff2cb0e18f390c293971985f41d2b03d
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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