248 	u32 div, con;  in rk3568_i2c_get_pmuclk()  local
252 		con = readl(&pmucru->pmu_clksel_con[3]);  in rk3568_i2c_get_pmuclk()
253 		div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;  in rk3568_i2c_get_pmuclk()
287 	u32 div, sel, con, parent;  in rk3568_pwm_get_pmuclk()  local
291 		con = readl(&pmucru->pmu_clksel_con[6]);  in rk3568_pwm_get_pmuclk()
292 		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;  in rk3568_pwm_get_pmuclk()
293 		div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT;  in rk3568_pwm_get_pmuclk()
339 	u32 div, con, sel, parent;  in rk3568_pmu_get_pmuclk()  local
341 	con = readl(&pmucru->pmu_clksel_con[2]);  in rk3568_pmu_get_pmuclk()
342 	sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;  in rk3568_pmu_get_pmuclk()
343 	div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT;  in rk3568_pmu_get_pmuclk()
624 	int div, mask, shift, con;  in rk3568_cpll_div_get_rate()  local
628 		con = 78;  in rk3568_cpll_div_get_rate()
633 		con = 79;  in rk3568_cpll_div_get_rate()
638 		con = 79;  in rk3568_cpll_div_get_rate()
643 		con = 80;  in rk3568_cpll_div_get_rate()
648 		con = 82;  in rk3568_cpll_div_get_rate()
653 		con = 80;  in rk3568_cpll_div_get_rate()
658 		con = 81;  in rk3568_cpll_div_get_rate()
663 		con = 81;  in rk3568_cpll_div_get_rate()
671 	div = (readl(&cru->clksel_con[con]) & mask) >> shift;  in rk3568_cpll_div_get_rate()
679 	int div, mask, shift, con;  in rk3568_cpll_div_set_rate()  local
683 		con = 78;  in rk3568_cpll_div_set_rate()
688 		con = 79;  in rk3568_cpll_div_set_rate()
693 		con = 79;  in rk3568_cpll_div_set_rate()
698 		con = 80;  in rk3568_cpll_div_set_rate()
703 		con = 82;  in rk3568_cpll_div_set_rate()
708 		con = 80;  in rk3568_cpll_div_set_rate()
713 		con = 81;  in rk3568_cpll_div_set_rate()
718 		con = 81;  in rk3568_cpll_div_set_rate()
731 	rk_clrsetreg(&cru->clksel_con[con],  in rk3568_cpll_div_set_rate()
739 	u32 con, sel, rate;  in rk3568_bus_get_clk()  local
743 		con = readl(&cru->clksel_con[50]);  in rk3568_bus_get_clk()
744 		sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
756 		con = readl(&cru->clksel_con[50]);  in rk3568_bus_get_clk()
757 		sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
820 	u32 con, sel, rate;  in rk3568_perimid_get_clk()  local
824 		con = readl(&cru->clksel_con[10]);  in rk3568_perimid_get_clk()
825 		sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
836 		con = readl(&cru->clksel_con[10]);  in rk3568_perimid_get_clk()
837 		sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
899 	u32 con, sel, rate;  in rk3568_top_get_clk()  local
903 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
904 		sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT;  in rk3568_top_get_clk()
915 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
916 		sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT;  in rk3568_top_get_clk()
927 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
928 		sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
939 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
940 		sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
1028 	u32 sel, con;  in rk3568_i2c_get_clk()  local
1037 		con = readl(&cru->clksel_con[71]);  in rk3568_i2c_get_clk()
1038 		sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;  in rk3568_i2c_get_clk()
1087 	u32 sel, con;  in rk3568_spi_get_clk()  local
1089 	con = readl(&cru->clksel_con[72]);  in rk3568_spi_get_clk()
1093 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rk3568_spi_get_clk()
1096 		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;  in rk3568_spi_get_clk()
1099 		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;  in rk3568_spi_get_clk()
1102 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;  in rk3568_spi_get_clk()
1164 	u32 sel, con;  in rk3568_pwm_get_clk()  local
1166 	con = readl(&cru->clksel_con[72]);  in rk3568_pwm_get_clk()
1170 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rk3568_pwm_get_clk()
1173 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rk3568_pwm_get_clk()
1176 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;  in rk3568_pwm_get_clk()
1231 	u32 div, sel, con, prate;  in rk3568_adc_get_clk()  local
1237 		con = readl(&cru->clksel_con[51]);  in rk3568_adc_get_clk()
1238 		div = (con & CLK_TSADC_TSEN_DIV_MASK) >>  in rk3568_adc_get_clk()
1240 		sel = (con & CLK_TSADC_TSEN_SEL_MASK) >>  in rk3568_adc_get_clk()
1248 		con = readl(&cru->clksel_con[51]);  in rk3568_adc_get_clk()
1249 		div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;  in rk3568_adc_get_clk()
1307 	u32 sel, con;  in rk3568_crypto_get_rate()  local
1312 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1313 		sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1326 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1327 		sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1338 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1339 		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >>  in rk3568_crypto_get_rate()
1348 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1349 		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >>  in rk3568_crypto_get_rate()
1428 	u32 sel, con;  in rk3568_sdmmc_get_clk()  local
1433 		con = readl(&cru->clksel_con[30]);  in rk3568_sdmmc_get_clk()
1434 		sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1437 		con = readl(&cru->clksel_con[30]);  in rk3568_sdmmc_get_clk()
1438 		sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1441 		con = readl(&cru->clksel_con[32]);  in rk3568_sdmmc_get_clk()
1442 		sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1525 	u32 sel, con;  in rk3568_sfc_get_clk()  local
1527 	con = readl(&cru->clksel_con[28]);  in rk3568_sfc_get_clk()
1528 	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;  in rk3568_sfc_get_clk()
1585 	u32 sel, con;  in rk3568_nand_get_clk()  local
1587 	con = readl(&cru->clksel_con[28]);  in rk3568_nand_get_clk()
1588 	sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT;  in rk3568_nand_get_clk()
1635 	u32 sel, con;  in rk3568_emmc_get_clk()  local
1637 	con = readl(&cru->clksel_con[28]);  in rk3568_emmc_get_clk()
1638 	sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_clk()
1697 	u32 sel, con;  in rk3568_emmc_get_bclk()  local
1699 	con = readl(&cru->clksel_con[28]);  in rk3568_emmc_get_bclk()
1700 	sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_bclk()
1743 	u32 div, sel, con, parent;  in rk3568_aclk_vop_get_clk()  local
1745 	con = readl(&cru->clksel_con[38]);  in rk3568_aclk_vop_get_clk()
1746 	div = (con & ACLK_VOP_PRE_DIV_MASK) >> ACLK_VOP_PRE_DIV_SHIFT;  in rk3568_aclk_vop_get_clk()
1747 	sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT;  in rk3568_aclk_vop_get_clk()
1784 	u32 conid, div, sel, con, parent;  in rk3568_dclk_vop_get_clk()  local
1800 	con = readl(&cru->clksel_con[conid]);  in rk3568_dclk_vop_get_clk()
1801 	div = (con & DCLK0_VOP_DIV_MASK) >> DCLK0_VOP_DIV_SHIFT;  in rk3568_dclk_vop_get_clk()
1802 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_get_clk()
1825 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3568_dclk_vop_set_clk()  local
1841 	con = readl(&cru->clksel_con[conid]);  in rk3568_dclk_vop_set_clk()
1842 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_set_clk()
1908 	u32 sel, con;  in rk3568_gmac_src_get_clk()  local
1910 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_src_get_clk()
1911 	sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT;  in rk3568_gmac_src_get_clk()
1958 	u32 sel, con;  in rk3568_gmac_out_get_clk()  local
1960 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_out_get_clk()
1961 	sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT;  in rk3568_gmac_out_get_clk()
2011 	u32 sel, con;  in rk3568_gmac_ptp_ref_get_clk()  local
2013 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_ptp_ref_get_clk()
2014 	sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT;  in rk3568_gmac_ptp_ref_get_clk()
2064 	u32 con, sel, div_sel;  in rk3568_gmac_tx_rx_set_clk()  local
2066 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_tx_rx_set_clk()
2067 	sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT;  in rk3568_gmac_tx_rx_set_clk()
2095 	u32 con, div, p_rate;  in rk3568_ebc_get_clk()  local
2097 	con = readl(&cru->clksel_con[79]);  in rk3568_ebc_get_clk()
2098 	div = (con & CPLL_333M_DIV_MASK) >> CPLL_333M_DIV_SHIFT;  in rk3568_ebc_get_clk()
2101 	con = readl(&cru->clksel_con[43]);  in rk3568_ebc_get_clk()
2102 	div = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;  in rk3568_ebc_get_clk()
2135 	u32 con, div, src, p_rate;  in rk3568_rkvdec_get_clk()  local
2140 		con = readl(&cru->clksel_con[47]);  in rk3568_rkvdec_get_clk()
2141 		src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT;  in rk3568_rkvdec_get_clk()
2142 		div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT;  in rk3568_rkvdec_get_clk()
2149 		con = readl(&cru->clksel_con[49]);  in rk3568_rkvdec_get_clk()
2150 		src = (con & CLK_RKVDEC_CORE_SEL_MASK)  in rk3568_rkvdec_get_clk()
2152 		div = (con & CLK_RKVDEC_CORE_DIV_MASK)  in rk3568_rkvdec_get_clk()
2221 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3568_uart_get_rate()  local
2255 	con = readl(&cru->clksel_con[reg]);  in rk3568_uart_get_rate()
2256 	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;  in rk3568_uart_get_rate()
2257 	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;  in rk3568_uart_get_rate()
2258 	p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;  in rk3568_uart_get_rate()
2358 	u32 con, div, src, p_rate;  in rk3568_i2s3_get_rate()  local
2364 		con = readl(&cru->clksel_con[21]);  in rk3568_i2s3_get_rate()
2365 		src = (con & I2S3_MCLKOUT_TX_SEL_MASK) >>  in rk3568_i2s3_get_rate()
2373 		con = readl(&cru->clksel_con[83]);  in rk3568_i2s3_get_rate()
2374 		src = (con & I2S3_MCLKOUT_TX_SEL_MASK) >>  in rk3568_i2s3_get_rate()
2382 		con = readl(&grf->soc_con2);  in rk3568_i2s3_get_rate()
2383 		src = (con & I2S3_MCLKOUT_SEL_MASK)  in rk3568_i2s3_get_rate()
2400 	con = readl(&cru->clksel_con[reg]);  in rk3568_i2s3_get_rate()
2401 	src = (con & CLK_I2S3_SEL_MASK) >> CLK_I2S3_SEL_SHIFT;  in rk3568_i2s3_get_rate()
2402 	div = (con & CLK_I2S3_SRC_DIV_MASK) >> CLK_I2S3_SRC_DIV_SHIFT;  in rk3568_i2s3_get_rate()
2403 	p_src = (con & CLK_I2S3_SRC_SEL_MASK) >> CLK_I2S3_SRC_SEL_SHIFT;  in rk3568_i2s3_get_rate()
2429 	u32 reg, con, clk_src, i2s_src, div;  in rk3568_i2s3_set_rate()  local
2484 		con = readl(&grf->soc_con2);  in rk3568_i2s3_set_rate()
2485 		clk_src = (con & I2S3_MCLKOUT_SEL_MASK)  in rk3568_i2s3_set_rate()