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Searched refs:CLK_DIVIDER_HIWORD_MASK (Results 1 – 25 of 27) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi3660.c336 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
338 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
340 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
342 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
344 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
346 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
348 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
350 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
352 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
354 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
H A Dclk-hi3670.c488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
H A Dclk-hi3620.c124 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
125 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
126 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
127 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
128 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
129 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
130 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap.h151 .div_flags = CLK_DIVIDER_HIWORD_MASK, \
168 .div_flags = CLK_DIVIDER_HIWORD_MASK, \
H A Dclk-regmap-composite.c256 if (div_flags & CLK_DIVIDER_HIWORD_MASK) { in devm_clk_regmap_register_composite()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c57 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_dclk_set_rate()
H A Dclk-half-divider.c117 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_half_divider_set_rate()
H A Dclk-rk3036.c152 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3128.c172 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3228.c181 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rv1108.c164 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3188.c239 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3328.c235 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3368.c171 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3288.c256 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3308.c199 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-px30.c210 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3528.c197 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3562.c145 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk1808.c206 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rv1106.c268 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rv1126.c256 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
H A Dclk-rk3399.c321 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-divider.c436 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_divider_set_rate()
478 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { in __clk_hw_register_divider()
/OK3568_Linux_fs/kernel/include/linux/
H A Dclk-provider.h626 #define CLK_DIVIDER_HIWORD_MASK BIT(3) macro

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