arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1

arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.

- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b

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rockchip: Add arch timer 1Ghz support

Change-Id: I8e58b15be1823e732852a2aa76cc98813e6b4fe9
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

cpu: armv7: Add udelay support for 32-bits platforms in board_init_f()

Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: I949e738d230dfc5f84421422f7d0201b66ff31f8

cpu: armv7: Disable align access in cpu_init_cp15()

There is unalign access when decompress firmware.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I780e4a0c3bd0a5285f5624e79bdc7184

cpu: armv7: Disable align access in cpu_init_cp15()

There is unalign access when decompress firmware.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I780e4a0c3bd0a5285f5624e79bdc7184c8bbe40f

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arm: v7: Add zero CNTVOFF support

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I844ea7592e1448d7e5408b6ec1b26ed80af53358

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene ===
When access a illegal address, It results in:
- read: Synchronous data-abort
- write: SError(64-bit)/Asynchronous external abort(32-bit)

=== 64-bit ===
EL3 SError ASynchronous exception in TPL/SPL was already
enabled in start.S and crt0_64.S which sets SCR_EL3.EA=1
and DAIF.A=0. We can test result of TPL/SPL by access address
0xfe108000 in rk3568.
Let's enable SError in U-Boot proper.

=== 32-bit ===
Let's set CPSR.A=0 to enable Asynchronous external abort, we can
test result by access address 0xfe808000 in rv1126.
Note: TPL/SPL vectors only provides "b ." for all exception entry.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id9f660a9275f69fdc8443ad239aabf79682d95d0

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arm: cache_v7: optimise dcache inval for unaligned range

- inval: flush first and last cacheline
- disable range alignment check(noisy vebose)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Cha

arm: cache_v7: optimise dcache inval for unaligned range

- inval: flush first and last cacheline
- disable range alignment check(noisy vebose)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie448c1c97a7ef15e3a10d3c984d5f36350df4eea

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UPSTREAM: arm: armv7: solve issue for timer_rate_hz in arch timer

The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeou

UPSTREAM: arm: armv7: solve issue for timer_rate_hz in arch timer

The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.

With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
(cherry picked from commit 77aace579a9a84c74e99d2e86ecc08b1d9ca402b)
Change-Id: Id289de433e49d396a95e3a72acf210be3a2d910b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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