xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/spl.c (revision 11f9ae3a9f57d1ecc3b8cc16cfbf5e4e599e5330) 
1 /*
2  * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <boot_rkimg.h>
9 #include <debug_uart.h>
10 #include <dm.h>
11 #include <key.h>
12 #include <led.h>
13 #include <misc.h>
14 #include <ram.h>
15 #include <spl.h>
16 #include <optee_include/OpteeClientInterface.h>
17 #include <power/fuel_gauge.h>
18 #include <asm/arch/bootrom.h>
19 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
20 #include <asm/arch/rk_atags.h>
21 #endif
22 #include <asm/arch/sdram.h>
23 #include <asm/arch/boot_mode.h>
24 #include <asm/arch-rockchip/sys_proto.h>
25 #include <asm/io.h>
26 #include <asm/arch/param.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 void board_return_to_bootrom(void)
31 {
32 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
33 }
34 
35 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
36 };
37 
38 const char *board_spl_was_booted_from(void)
39 {
40 	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
41 	const char *bootdevice_ofpath = NULL;
42 
43 	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
44 		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
45 
46 	if (bootdevice_ofpath)
47 		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
48 		      __func__, bootdevice_brom_id, bootdevice_ofpath);
49 	else
50 		debug("%s: failed to resolve brom_bootdevice_id %x\n",
51 		      __func__, bootdevice_brom_id);
52 
53 	return bootdevice_ofpath;
54 }
55 
56 u32 spl_boot_device(void)
57 {
58 	u32 boot_device = BOOT_DEVICE_MMC1;
59 
60 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
61 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
62 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
63 	return BOOT_DEVICE_SPI;
64 #endif
65 	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
66 		return BOOT_DEVICE_BOOTROM;
67 
68 	return boot_device;
69 }
70 
71 u32 spl_boot_mode(const u32 boot_device)
72 {
73 	return MMCSD_MODE_RAW;
74 }
75 
76 __weak void rockchip_stimer_init(void)
77 {
78 	/* If Timer already enabled, don't re-init it */
79 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
80 	if ( reg & 0x1 )
81 		return;
82 #ifndef CONFIG_ARM64
83 	asm volatile("mcr p15, 0, %0, c14, c0, 0"
84 		     : : "r"(COUNTER_FREQUENCY));
85 #endif
86 	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
87 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
88 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
89 	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
90 }
91 
92 __weak int arch_cpu_init(void)
93 {
94 	return 0;
95 }
96 
97 __weak int rk_board_init_f(void)
98 {
99 	return 0;
100 }
101 
102 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
103 void udelay(unsigned long usec)
104 {
105 	__udelay(usec);
106 }
107 
108 void hang(void)
109 {
110 	bootstage_error(BOOTSTAGE_ID_NEED_RESET);
111 	for (;;)
112 		;
113 }
114 
115 /**
116  * memset - Fill a region of memory with the given value
117  * @s: Pointer to the start of the area.
118  * @c: The byte to fill the area with
119  * @count: The size of the area.
120  *
121  * Do not use memset() to access IO space, use memset_io() instead.
122  */
123 void *memset(void *s, int c, size_t count)
124 {
125 	unsigned long *sl = (unsigned long *)s;
126 	char *s8;
127 
128 #if !CONFIG_IS_ENABLED(TINY_MEMSET)
129 	unsigned long cl = 0;
130 	int i;
131 
132 	/* do it one word at a time (32 bits or 64 bits) while possible */
133 	if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
134 		for (i = 0; i < sizeof(*sl); i++) {
135 			cl <<= 8;
136 			cl |= c & 0xff;
137 		}
138 		while (count >= sizeof(*sl)) {
139 			*sl++ = cl;
140 			count -= sizeof(*sl);
141 		}
142 	}
143 #endif /* fill 8 bits at a time */
144 	s8 = (char *)sl;
145 	while (count--)
146 		*s8++ = c;
147 
148 	return s;
149 }
150 #endif
151 
152 void board_init_f(ulong dummy)
153 {
154 #ifdef CONFIG_SPL_FRAMEWORK
155 	int ret;
156 #if !defined(CONFIG_SUPPORT_TPL)
157 	struct udevice *dev;
158 #endif
159 #endif
160 	gd->flags = dummy;
161 	rockchip_stimer_init();
162 #define EARLY_UART
163 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
164 	/*
165 	 * Debug UART can be used from here if required:
166 	 *
167 	 * debug_uart_init();
168 	 * printch('a');
169 	 * printhex8(0x1234);
170 	 * printascii("string");
171 	 */
172 	if (!gd->serial.using_pre_serial &&
173 	    !(gd->flags & GD_FLG_DISABLE_CONSOLE))
174 		debug_uart_init();
175 	printascii("U-Boot SPL board init");
176 #endif
177 	gd->sys_start_tick = get_ticks();
178 #ifdef CONFIG_SPL_FRAMEWORK
179 	ret = spl_early_init();
180 	if (ret) {
181 		printf("spl_early_init() failed: %d\n", ret);
182 		hang();
183 	}
184 #if !defined(CONFIG_SUPPORT_TPL)
185 	debug("\nspl:init dram\n");
186 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
187 	if (ret) {
188 		printf("DRAM init failed: %d\n", ret);
189 		return;
190 	}
191 #endif
192 	preloader_console_init();
193 #else
194 	/* Some SoCs like rk3036 does not use any frame work */
195 	sdram_init();
196 #endif
197 
198 	arch_cpu_init();
199 	rk_board_init_f();
200 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
201 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
202 #endif
203 
204 }
205 
206 #ifdef CONFIG_SPL_LOAD_FIT
207 int board_fit_config_name_match(const char *name)
208 {
209 	/* Just empty function now - can't decide what to choose */
210 	debug("%s: %s\n", __func__, name);
211 
212 	return 0;
213 }
214 #endif
215 
216 int board_init_f_boot_flags(void)
217 {
218 	int boot_flags = 0;
219 
220 #ifdef CONFIG_FPGA_ROCKCHIP
221 	arch_fpga_init();
222 #endif
223 #ifdef CONFIG_PSTORE
224 	param_parse_pstore();
225 #endif
226 	/* pre-loader serial */
227 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
228     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
229 	struct tag *t;
230 
231 	t = atags_get_tag(ATAG_SERIAL);
232 	if (t) {
233 		gd->serial.using_pre_serial = 1;
234 		gd->serial.enable = t->u.serial.enable;
235 		gd->serial.baudrate = t->u.serial.baudrate;
236 		gd->serial.addr = t->u.serial.addr;
237 		gd->serial.id = t->u.serial.id;
238 		gd->baudrate = t->u.serial.baudrate;
239 		if (!t->u.serial.enable)
240 			boot_flags |= GD_FLG_DISABLE_CONSOLE;
241 		debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
242 		      t->u.serial.enable, (u32)t->u.serial.addr,
243 		      t->u.serial.baudrate, t->u.serial.id);
244 	} else
245 #endif
246 	{
247 		gd->baudrate = CONFIG_BAUDRATE;
248 		gd->serial.baudrate = CONFIG_BAUDRATE;
249 		gd->serial.addr = CONFIG_DEBUG_UART_BASE;
250 	}
251 
252 	/* The highest priority to turn off (override) console */
253 #if defined(CONFIG_DISABLE_CONSOLE)
254 	boot_flags |= GD_FLG_DISABLE_CONSOLE;
255 #endif
256 
257 	return boot_flags;
258 }
259 
260 #ifdef CONFIG_SPL_BOARD_INIT
261 __weak int rk_spl_board_init(void)
262 {
263 	return 0;
264 }
265 
266 static int setup_led(void)
267 {
268 #ifdef CONFIG_SPL_LED
269 	struct udevice *dev;
270 	char *led_name;
271 	int ret;
272 
273 	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
274 	if (!led_name)
275 		return 0;
276 	ret = led_get_by_label(led_name, &dev);
277 	if (ret) {
278 		debug("%s: get=%d\n", __func__, ret);
279 		return ret;
280 	}
281 	ret = led_set_state(dev, LEDST_ON);
282 	if (ret)
283 		return ret;
284 #endif
285 
286 	return 0;
287 }
288 
289 void spl_board_init(void)
290 {
291 	int ret;
292 
293 	ret = setup_led();
294 
295 	if (ret) {
296 		debug("LED ret=%d\n", ret);
297 		hang();
298 	}
299 
300 	rk_spl_board_init();
301 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
302 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
303 #endif
304 	return;
305 }
306 #endif
307 
308 void spl_perform_fixups(struct spl_image_info *spl_image)
309 {
310 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
311 	atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
312 #endif
313 	return;
314 }
315 
316 #ifdef CONFIG_SPL_KERNEL_BOOT
317 static int spl_rockchip_dnl_key_pressed(void)
318 {
319 #if defined(CONFIG_SPL_INPUT)
320 	return key_read(KEY_VOLUMEUP);
321 #else
322 	return 0;
323 #endif
324 }
325 
326 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
327 bool spl_is_low_power(void)
328 {
329 	struct udevice *dev;
330 	int ret, voltage;
331 
332 	ret = uclass_get_device(UCLASS_FG, 0, &dev);
333 	if (ret) {
334 		debug("Get charge display failed, ret=%d\n", ret);
335 		return false;
336 	}
337 
338 	voltage = fuel_gauge_get_voltage(dev);
339 	if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD)
340 		return false;
341 
342 	return true;
343 }
344 #endif
345 
346 void spl_next_stage(struct spl_image_info *spl)
347 {
348 	uint32_t reg_boot_mode;
349 
350 	if (spl_rockchip_dnl_key_pressed()) {
351 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
352 		return;
353 	}
354 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
355 	if (spl_is_low_power()) {
356 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
357 		return;
358 	}
359 #endif
360 
361 	reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
362 	switch (reg_boot_mode) {
363 	case BOOT_COLD:
364 	case BOOT_PANIC:
365 	case BOOT_WATCHDOG:
366 	case BOOT_NORMAL:
367 	case BOOT_RECOVERY:
368 		spl->next_stage = SPL_NEXT_STAGE_KERNEL;
369 		break;
370 	default:
371 		if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG)
372 			spl->next_stage = SPL_NEXT_STAGE_KERNEL;
373 		else
374 			spl->next_stage = SPL_NEXT_STAGE_UBOOT;
375 	}
376 }
377 #endif
378 
379 #ifdef CONFIG_SPL_KERNEL_BOOT
380 const char *spl_kernel_partition(struct spl_image_info *spl,
381 				 struct spl_load_info *info)
382 {
383 	struct bootloader_message *bmsg = NULL;
384 	u32 boot_mode;
385 	int ret, cnt;
386 	u32 sector = 0;
387 
388 #ifdef CONFIG_SPL_LIBDISK_SUPPORT
389 	disk_partition_t part_info;
390 
391 	ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
392 	if (ret >= 0)
393 		sector = part_info.start;
394 #else
395 	sector = CONFIG_SPL_MISC_SECTOR;
396 #endif
397 	if (sector) {
398 		cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
399 		bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
400 		ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
401 				 cnt, bmsg);
402 		if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
403 			free(bmsg);
404 			return PART_RECOVERY;
405 		} else {
406 			free(bmsg);
407 		}
408 	}
409 
410 	boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
411 
412 	return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
413 }
414 #endif
415 
416 void spl_hang_reset(void)
417 {
418 	printf("# Reset the board to bootrom #\n");
419 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
420 	/* reset is available after dm setup */
421 	if (gd->flags & GD_FLG_SPL_EARLY_INIT) {
422 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
423 		do_reset(NULL, 0, 0, NULL);
424 	}
425 #endif
426 }
427 
428 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
429 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
430 {
431 	int ret = 0;
432 
433 	*otp_index = 0;
434 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
435 	struct udevice *dev;
436 	u32 index, i, otp_version;
437 	u32 bit_count;
438 
439 	dev = misc_otp_get_device(OTP_S);
440 	if (!dev)
441 		return -ENODEV;
442 
443 	otp_version = 0;
444 	for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
445 		if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
446 		    &index,
447 		    4)) {
448 			printf("Can't read rollback index\n");
449 			return -EIO;
450 		}
451 
452 		bit_count = fls(index);
453 		otp_version += bit_count;
454 	}
455 	*otp_index = otp_version;
456 #endif
457 
458 	return ret;
459 }
460 
461 static int fit_write_otp_rollback_index(u32 fit_index)
462 {
463 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
464 	struct udevice *dev;
465 	u32 index, i, otp_index;
466 
467 	if (!fit_index)
468 		return 0;
469 
470 	if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
471 		return -EINVAL;
472 
473 	dev = misc_otp_get_device(OTP_S);
474 	if (!dev)
475 		return -ENODEV;
476 
477 	if (fit_read_otp_rollback_index(fit_index, &otp_index))
478 		return -EIO;
479 
480 	if (otp_index < fit_index) {
481 		/* Write new SW version to otp */
482 		for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
483 			/*
484 			 * If fit_index is equal to 0, then execute 0xffffffff >> 32.
485 			 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is
486 			 * actually be "0xffffffff >> 0".
487 			 */
488 			if (!fit_index)
489 				break;
490 			/* convert to base-1 representation */
491 			index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
492 				min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
493 			fit_index -= min(fit_index,
494 					  (u32)OTP_ALL_ONES_NUM_BITS);
495 			if (index) {
496 				if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
497 				    &index,
498 				    4)) {
499 					printf("Can't write rollback index\n");
500 					return -EIO;
501 				}
502 			}
503 		}
504 	}
505 #endif
506 
507 	return 0;
508 }
509 #endif
510 
511 int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
512 {
513 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
514 	int ret;
515 
516 	ret = fit_write_otp_rollback_index(gd->rollback_index);
517 	if (ret) {
518 		panic("Failed to write fit rollback index %d, ret=%d",
519 		      gd->rollback_index, ret);
520 	}
521 #endif
522 
523 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
524 	misc_decompress_cleanup();
525 #endif
526 	return 0;
527 }
528