1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/arch/cpu.h> 14 15 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 16 #define RK_FUNC_GPIO 0 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 19 enum rockchip_pinctrl_type { 20 PX30, 21 RV1108, 22 RK1808, 23 RK2928, 24 RK3066B, 25 RK3128, 26 RK3188, 27 RK3288, 28 RK3308, 29 RK3368, 30 RK3399, 31 }; 32 33 /** 34 * Encode variants of iomux registers into a type variable 35 */ 36 #define IOMUX_GPIO_ONLY BIT(0) 37 #define IOMUX_WIDTH_4BIT BIT(1) 38 #define IOMUX_SOURCE_PMU BIT(2) 39 #define IOMUX_UNROUTED BIT(3) 40 #define IOMUX_WIDTH_3BIT BIT(4) 41 #define IOMUX_8WIDTH_2BIT BIT(5) 42 #define IOMUX_WRITABLE_32BIT BIT(6) 43 44 /** 45 * @type: iomux variant using IOMUX_* constants 46 * @offset: if initialized to -1 it will be autocalculated, by specifying 47 * an initial offset value the relevant source offset can be reset 48 * to a new value for autocalculating the following iomux registers. 49 */ 50 struct rockchip_iomux { 51 int type; 52 int offset; 53 }; 54 55 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 56 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 57 58 /** 59 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 60 */ 61 enum rockchip_pin_drv_type { 62 DRV_TYPE_IO_DEFAULT = 0, 63 DRV_TYPE_IO_1V8_OR_3V0, 64 DRV_TYPE_IO_1V8_ONLY, 65 DRV_TYPE_IO_1V8_3V0_AUTO, 66 DRV_TYPE_IO_3V3_ONLY, 67 DRV_TYPE_MAX 68 }; 69 70 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 71 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 72 73 /** 74 * enum type index corresponding to rockchip_pull_list arrays index. 75 */ 76 enum rockchip_pin_pull_type { 77 PULL_TYPE_IO_DEFAULT = 0, 78 PULL_TYPE_IO_1V8_ONLY, 79 PULL_TYPE_MAX 80 }; 81 82 /** 83 * @drv_type: drive strength variant using rockchip_perpin_drv_type 84 * @offset: if initialized to -1 it will be autocalculated, by specifying 85 * an initial offset value the relevant source offset can be reset 86 * to a new value for autocalculating the following drive strength 87 * registers. if used chips own cal_drv func instead to calculate 88 * registers offset, the variant could be ignored. 89 */ 90 struct rockchip_drv { 91 enum rockchip_pin_drv_type drv_type; 92 int offset; 93 }; 94 95 /** 96 * @priv: common pinctrl private basedata 97 * @pin_base: first pin number 98 * @nr_pins: number of pins in this bank 99 * @name: name of the bank 100 * @bank_num: number of the bank, to account for holes 101 * @iomux: array describing the 4 iomux sources of the bank 102 * @drv: array describing the 4 drive strength sources of the bank 103 * @pull_type: array describing the 4 pull type sources of the bank 104 * @recalced_mask: bits describing the mux recalced pins of per bank 105 * @route_mask: bits describing the routing pins of per bank 106 */ 107 struct rockchip_pin_bank { 108 struct rockchip_pinctrl_priv *priv; 109 u32 pin_base; 110 u8 nr_pins; 111 char *name; 112 u8 bank_num; 113 struct rockchip_iomux iomux[4]; 114 struct rockchip_drv drv[4]; 115 enum rockchip_pin_pull_type pull_type[4]; 116 u32 recalced_mask; 117 u32 route_mask; 118 }; 119 120 #define PIN_BANK(id, pins, label) \ 121 { \ 122 .bank_num = id, \ 123 .nr_pins = pins, \ 124 .name = label, \ 125 .iomux = { \ 126 { .offset = -1 }, \ 127 { .offset = -1 }, \ 128 { .offset = -1 }, \ 129 { .offset = -1 }, \ 130 }, \ 131 } 132 133 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 134 { \ 135 .bank_num = id, \ 136 .nr_pins = pins, \ 137 .name = label, \ 138 .iomux = { \ 139 { .type = iom0, .offset = -1 }, \ 140 { .type = iom1, .offset = -1 }, \ 141 { .type = iom2, .offset = -1 }, \ 142 { .type = iom3, .offset = -1 }, \ 143 }, \ 144 } 145 146 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 147 { \ 148 .bank_num = id, \ 149 .nr_pins = pins, \ 150 .name = label, \ 151 .iomux = { \ 152 { .offset = -1 }, \ 153 { .offset = -1 }, \ 154 { .offset = -1 }, \ 155 { .offset = -1 }, \ 156 }, \ 157 .drv = { \ 158 { .drv_type = type0, .offset = -1 }, \ 159 { .drv_type = type1, .offset = -1 }, \ 160 { .drv_type = type2, .offset = -1 }, \ 161 { .drv_type = type3, .offset = -1 }, \ 162 }, \ 163 } 164 165 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 166 drv2, drv3, pull0, pull1, \ 167 pull2, pull3) \ 168 { \ 169 .bank_num = id, \ 170 .nr_pins = pins, \ 171 .name = label, \ 172 .iomux = { \ 173 { .offset = -1 }, \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 }, \ 178 .drv = { \ 179 { .drv_type = drv0, .offset = -1 }, \ 180 { .drv_type = drv1, .offset = -1 }, \ 181 { .drv_type = drv2, .offset = -1 }, \ 182 { .drv_type = drv3, .offset = -1 }, \ 183 }, \ 184 .pull_type[0] = pull0, \ 185 .pull_type[1] = pull1, \ 186 .pull_type[2] = pull2, \ 187 .pull_type[3] = pull3, \ 188 } 189 190 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 191 iom2, iom3, drv0, drv1, drv2, \ 192 drv3, offset0, offset1, \ 193 offset2, offset3) \ 194 { \ 195 .bank_num = id, \ 196 .nr_pins = pins, \ 197 .name = label, \ 198 .iomux = { \ 199 { .type = iom0, .offset = -1 }, \ 200 { .type = iom1, .offset = -1 }, \ 201 { .type = iom2, .offset = -1 }, \ 202 { .type = iom3, .offset = -1 }, \ 203 }, \ 204 .drv = { \ 205 { .drv_type = drv0, .offset = offset0 }, \ 206 { .drv_type = drv1, .offset = offset1 }, \ 207 { .drv_type = drv2, .offset = offset2 }, \ 208 { .drv_type = drv3, .offset = offset3 }, \ 209 }, \ 210 } 211 212 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 213 iom2, iom3, drv0, drv1, drv2, \ 214 drv3, pull0, pull1, pull2, \ 215 pull3) \ 216 { \ 217 .bank_num = id, \ 218 .nr_pins = pins, \ 219 .name = label, \ 220 .iomux = { \ 221 { .type = iom0, .offset = -1 }, \ 222 { .type = iom1, .offset = -1 }, \ 223 { .type = iom2, .offset = -1 }, \ 224 { .type = iom3, .offset = -1 }, \ 225 }, \ 226 .drv = { \ 227 { .drv_type = drv0, .offset = -1 }, \ 228 { .drv_type = drv1, .offset = -1 }, \ 229 { .drv_type = drv2, .offset = -1 }, \ 230 { .drv_type = drv3, .offset = -1 }, \ 231 }, \ 232 .pull_type[0] = pull0, \ 233 .pull_type[1] = pull1, \ 234 .pull_type[2] = pull2, \ 235 .pull_type[3] = pull3, \ 236 } 237 238 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 239 label, iom0, iom1, iom2, \ 240 iom3, drv0, drv1, drv2, \ 241 drv3, offset0, offset1, \ 242 offset2, offset3, pull0, \ 243 pull1, pull2, pull3) \ 244 { \ 245 .bank_num = id, \ 246 .nr_pins = pins, \ 247 .name = label, \ 248 .iomux = { \ 249 { .type = iom0, .offset = -1 }, \ 250 { .type = iom1, .offset = -1 }, \ 251 { .type = iom2, .offset = -1 }, \ 252 { .type = iom3, .offset = -1 }, \ 253 }, \ 254 .drv = { \ 255 { .drv_type = drv0, .offset = offset0 }, \ 256 { .drv_type = drv1, .offset = offset1 }, \ 257 { .drv_type = drv2, .offset = offset2 }, \ 258 { .drv_type = drv3, .offset = offset3 }, \ 259 }, \ 260 .pull_type[0] = pull0, \ 261 .pull_type[1] = pull1, \ 262 .pull_type[2] = pull2, \ 263 .pull_type[3] = pull3, \ 264 } 265 266 /** 267 * struct rockchip_mux_recalced_data: represent a pin iomux data. 268 * @num: bank number. 269 * @pin: pin number. 270 * @bit: index at register. 271 * @reg: register offset. 272 * @mask: mask bit 273 */ 274 struct rockchip_mux_recalced_data { 275 u8 num; 276 u8 pin; 277 u32 reg; 278 u8 bit; 279 u8 mask; 280 }; 281 282 /** 283 * struct rockchip_mux_recalced_data: represent a pin iomux data. 284 * @bank_num: bank number. 285 * @pin: index at register or used to calc index. 286 * @func: the min pin. 287 * @route_offset: the max pin. 288 * @route_val: the register offset. 289 */ 290 struct rockchip_mux_route_data { 291 u8 bank_num; 292 u8 pin; 293 u8 func; 294 u32 route_offset; 295 u32 route_val; 296 }; 297 298 /** 299 */ 300 struct rockchip_pin_ctrl { 301 struct rockchip_pin_bank *pin_banks; 302 u32 nr_banks; 303 u32 nr_pins; 304 char *label; 305 enum rockchip_pinctrl_type type; 306 int grf_mux_offset; 307 int pmu_mux_offset; 308 int grf_drv_offset; 309 int pmu_drv_offset; 310 struct rockchip_mux_recalced_data *iomux_recalced; 311 u32 niomux_recalced; 312 struct rockchip_mux_route_data *iomux_routes; 313 u32 niomux_routes; 314 315 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 316 317 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 318 319 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 320 int pin_num, struct regmap **regmap, 321 int *reg, u8 *bit); 322 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 323 int pin_num, struct regmap **regmap, 324 int *reg, u8 *bit); 325 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 326 int pin_num, struct regmap **regmap, 327 int *reg, u8 *bit); 328 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 329 int pin_num, struct regmap **regmap, 330 int *reg, u8 *bit); 331 }; 332 333 /** 334 */ 335 struct rockchip_pinctrl_priv { 336 struct rockchip_pin_ctrl *ctrl; 337 struct regmap *regmap_base; 338 struct regmap *regmap_pmu; 339 340 }; 341 342 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 343 { 344 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 345 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 346 347 if (bank >= ctrl->nr_banks) { 348 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 349 return -EINVAL; 350 } 351 352 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 353 debug("pin conf pin %d >= %d\n", pin, 354 MAX_ROCKCHIP_GPIO_PER_BANK); 355 return -EINVAL; 356 } 357 358 return 0; 359 } 360 361 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 362 { 363 .num = 1, 364 .pin = 0, 365 .reg = 0x418, 366 .bit = 0, 367 .mask = 0x3 368 }, { 369 .num = 1, 370 .pin = 1, 371 .reg = 0x418, 372 .bit = 2, 373 .mask = 0x3 374 }, { 375 .num = 1, 376 .pin = 2, 377 .reg = 0x418, 378 .bit = 4, 379 .mask = 0x3 380 }, { 381 .num = 1, 382 .pin = 3, 383 .reg = 0x418, 384 .bit = 6, 385 .mask = 0x3 386 }, { 387 .num = 1, 388 .pin = 4, 389 .reg = 0x418, 390 .bit = 8, 391 .mask = 0x3 392 }, { 393 .num = 1, 394 .pin = 5, 395 .reg = 0x418, 396 .bit = 10, 397 .mask = 0x3 398 }, { 399 .num = 1, 400 .pin = 6, 401 .reg = 0x418, 402 .bit = 12, 403 .mask = 0x3 404 }, { 405 .num = 1, 406 .pin = 7, 407 .reg = 0x418, 408 .bit = 14, 409 .mask = 0x3 410 }, { 411 .num = 1, 412 .pin = 8, 413 .reg = 0x41c, 414 .bit = 0, 415 .mask = 0x3 416 }, { 417 .num = 1, 418 .pin = 9, 419 .reg = 0x41c, 420 .bit = 2, 421 .mask = 0x3 422 }, 423 }; 424 425 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 426 { 427 .num = 2, 428 .pin = 20, 429 .reg = 0xe8, 430 .bit = 0, 431 .mask = 0x7 432 }, { 433 .num = 2, 434 .pin = 21, 435 .reg = 0xe8, 436 .bit = 4, 437 .mask = 0x7 438 }, { 439 .num = 2, 440 .pin = 22, 441 .reg = 0xe8, 442 .bit = 8, 443 .mask = 0x7 444 }, { 445 .num = 2, 446 .pin = 23, 447 .reg = 0xe8, 448 .bit = 12, 449 .mask = 0x7 450 }, { 451 .num = 2, 452 .pin = 24, 453 .reg = 0xd4, 454 .bit = 12, 455 .mask = 0x7 456 }, 457 }; 458 459 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 460 { 461 .num = 1, 462 .pin = 14, 463 .reg = 0x28, 464 .bit = 12, 465 .mask = 0x7 466 }, { 467 .num = 1, 468 .pin = 15, 469 .reg = 0x2c, 470 .bit = 0, 471 .mask = 0x3 472 }, { 473 .num = 1, 474 .pin = 18, 475 .reg = 0x30, 476 .bit = 4, 477 .mask = 0x7 478 }, { 479 .num = 1, 480 .pin = 19, 481 .reg = 0x30, 482 .bit = 8, 483 .mask = 0x7 484 }, { 485 .num = 1, 486 .pin = 20, 487 .reg = 0x30, 488 .bit = 12, 489 .mask = 0x7 490 }, { 491 .num = 1, 492 .pin = 21, 493 .reg = 0x34, 494 .bit = 0, 495 .mask = 0x7 496 }, { 497 .num = 1, 498 .pin = 22, 499 .reg = 0x34, 500 .bit = 4, 501 .mask = 0x7 502 }, { 503 .num = 1, 504 .pin = 23, 505 .reg = 0x34, 506 .bit = 8, 507 .mask = 0x7 508 }, { 509 .num = 3, 510 .pin = 12, 511 .reg = 0x68, 512 .bit = 8, 513 .mask = 0x7 514 }, { 515 .num = 3, 516 .pin = 13, 517 .reg = 0x68, 518 .bit = 12, 519 .mask = 0x7 520 }, 521 }; 522 523 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 524 { 525 .num = 1, 526 .pin = 14, 527 .reg = 0x28, 528 .bit = 12, 529 .mask = 0xf 530 }, { 531 .num = 1, 532 .pin = 15, 533 .reg = 0x2c, 534 .bit = 0, 535 .mask = 0x3 536 }, { 537 .num = 1, 538 .pin = 18, 539 .reg = 0x30, 540 .bit = 4, 541 .mask = 0xf 542 }, { 543 .num = 1, 544 .pin = 19, 545 .reg = 0x30, 546 .bit = 8, 547 .mask = 0xf 548 }, { 549 .num = 1, 550 .pin = 20, 551 .reg = 0x30, 552 .bit = 12, 553 .mask = 0xf 554 }, { 555 .num = 1, 556 .pin = 21, 557 .reg = 0x34, 558 .bit = 0, 559 .mask = 0xf 560 }, { 561 .num = 1, 562 .pin = 22, 563 .reg = 0x34, 564 .bit = 4, 565 .mask = 0xf 566 }, { 567 .num = 1, 568 .pin = 23, 569 .reg = 0x34, 570 .bit = 8, 571 .mask = 0xf 572 }, { 573 .num = 3, 574 .pin = 12, 575 .reg = 0x68, 576 .bit = 8, 577 .mask = 0xf 578 }, { 579 .num = 3, 580 .pin = 13, 581 .reg = 0x68, 582 .bit = 12, 583 .mask = 0xf 584 }, { 585 .num = 2, 586 .pin = 2, 587 .reg = 0x608, 588 .bit = 0, 589 .mask = 0x7 590 }, { 591 .num = 2, 592 .pin = 3, 593 .reg = 0x608, 594 .bit = 4, 595 .mask = 0x7 596 }, { 597 .num = 2, 598 .pin = 16, 599 .reg = 0x610, 600 .bit = 8, 601 .mask = 0x7 602 }, { 603 .num = 3, 604 .pin = 10, 605 .reg = 0x610, 606 .bit = 0, 607 .mask = 0x7 608 }, { 609 .num = 3, 610 .pin = 11, 611 .reg = 0x610, 612 .bit = 4, 613 .mask = 0x7 614 }, 615 }; 616 617 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 618 { 619 .num = 2, 620 .pin = 12, 621 .reg = 0x24, 622 .bit = 8, 623 .mask = 0x3 624 }, { 625 .num = 2, 626 .pin = 15, 627 .reg = 0x28, 628 .bit = 0, 629 .mask = 0x7 630 }, { 631 .num = 2, 632 .pin = 23, 633 .reg = 0x30, 634 .bit = 14, 635 .mask = 0x3 636 }, 637 }; 638 639 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 640 int *reg, u8 *bit, int *mask) 641 { 642 struct rockchip_pinctrl_priv *priv = bank->priv; 643 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 644 struct rockchip_mux_recalced_data *data; 645 int i; 646 647 for (i = 0; i < ctrl->niomux_recalced; i++) { 648 data = &ctrl->iomux_recalced[i]; 649 if (data->num == bank->bank_num && 650 data->pin == pin) 651 break; 652 } 653 654 if (i >= ctrl->niomux_recalced) 655 return; 656 657 *reg = data->reg; 658 *mask = data->mask; 659 *bit = data->bit; 660 } 661 662 static struct rockchip_mux_route_data px30_mux_route_data[] = { 663 { 664 /* cif-d2m0 */ 665 .bank_num = 2, 666 .pin = 0, 667 .func = 1, 668 .route_offset = 0x184, 669 .route_val = BIT(16 + 7), 670 }, { 671 /* cif-d2m1 */ 672 .bank_num = 3, 673 .pin = 3, 674 .func = 3, 675 .route_offset = 0x184, 676 .route_val = BIT(16 + 7) | BIT(7), 677 }, { 678 /* pdm-m0 */ 679 .bank_num = 3, 680 .pin = 22, 681 .func = 2, 682 .route_offset = 0x184, 683 .route_val = BIT(16 + 8), 684 }, { 685 /* pdm-m1 */ 686 .bank_num = 2, 687 .pin = 22, 688 .func = 1, 689 .route_offset = 0x184, 690 .route_val = BIT(16 + 8) | BIT(8), 691 }, { 692 /* uart2-rxm0 */ 693 .bank_num = 1, 694 .pin = 27, 695 .func = 2, 696 .route_offset = 0x184, 697 .route_val = BIT(16 + 10), 698 }, { 699 /* uart2-rxm1 */ 700 .bank_num = 2, 701 .pin = 14, 702 .func = 2, 703 .route_offset = 0x184, 704 .route_val = BIT(16 + 10) | BIT(10), 705 }, { 706 /* uart3-rxm0 */ 707 .bank_num = 0, 708 .pin = 17, 709 .func = 2, 710 .route_offset = 0x184, 711 .route_val = BIT(16 + 9), 712 }, { 713 /* uart3-rxm1 */ 714 .bank_num = 1, 715 .pin = 15, 716 .func = 2, 717 .route_offset = 0x184, 718 .route_val = BIT(16 + 9) | BIT(9), 719 }, 720 }; 721 722 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 723 { 724 /* i2c2m0_sda */ 725 .bank_num = 3, 726 .pin = 12, 727 .func = 2, 728 .route_offset = 0x190, 729 .route_val = BIT(16 + 3), 730 }, { 731 /* i2c2m1_sda */ 732 .bank_num = 1, 733 .pin = 13, 734 .func = 2, 735 .route_offset = 0x190, 736 .route_val = BIT(16 + 3) | BIT(3), 737 }, { 738 /* uart2_rxm0 */ 739 .bank_num = 4, 740 .pin = 3, 741 .func = 2, 742 .route_offset = 0x190, 743 .route_val = BIT(16 + 14) | BIT(16 + 15), 744 }, { 745 /* uart2_rxm1 */ 746 .bank_num = 2, 747 .pin = 25, 748 .func = 2, 749 .route_offset = 0x190, 750 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 751 }, { 752 /* uart2_rxm2 */ 753 .bank_num = 3, 754 .pin = 4, 755 .func = 2, 756 .route_offset = 0x190, 757 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 758 }, 759 }; 760 761 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 762 { 763 /* spi-0 */ 764 .bank_num = 1, 765 .pin = 10, 766 .func = 1, 767 .route_offset = 0x144, 768 .route_val = BIT(16 + 3) | BIT(16 + 4), 769 }, { 770 /* spi-1 */ 771 .bank_num = 1, 772 .pin = 27, 773 .func = 3, 774 .route_offset = 0x144, 775 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 776 }, { 777 /* spi-2 */ 778 .bank_num = 0, 779 .pin = 13, 780 .func = 2, 781 .route_offset = 0x144, 782 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 783 }, { 784 /* i2s-0 */ 785 .bank_num = 1, 786 .pin = 5, 787 .func = 1, 788 .route_offset = 0x144, 789 .route_val = BIT(16 + 5), 790 }, { 791 /* i2s-1 */ 792 .bank_num = 0, 793 .pin = 14, 794 .func = 1, 795 .route_offset = 0x144, 796 .route_val = BIT(16 + 5) | BIT(5), 797 }, { 798 /* emmc-0 */ 799 .bank_num = 1, 800 .pin = 22, 801 .func = 2, 802 .route_offset = 0x144, 803 .route_val = BIT(16 + 6), 804 }, { 805 /* emmc-1 */ 806 .bank_num = 2, 807 .pin = 4, 808 .func = 2, 809 .route_offset = 0x144, 810 .route_val = BIT(16 + 6) | BIT(6), 811 }, 812 }; 813 814 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 815 { 816 /* pwm0-0 */ 817 .bank_num = 0, 818 .pin = 26, 819 .func = 1, 820 .route_offset = 0x50, 821 .route_val = BIT(16), 822 }, { 823 /* pwm0-1 */ 824 .bank_num = 3, 825 .pin = 21, 826 .func = 1, 827 .route_offset = 0x50, 828 .route_val = BIT(16) | BIT(0), 829 }, { 830 /* pwm1-0 */ 831 .bank_num = 0, 832 .pin = 27, 833 .func = 1, 834 .route_offset = 0x50, 835 .route_val = BIT(16 + 1), 836 }, { 837 /* pwm1-1 */ 838 .bank_num = 0, 839 .pin = 30, 840 .func = 2, 841 .route_offset = 0x50, 842 .route_val = BIT(16 + 1) | BIT(1), 843 }, { 844 /* pwm2-0 */ 845 .bank_num = 0, 846 .pin = 28, 847 .func = 1, 848 .route_offset = 0x50, 849 .route_val = BIT(16 + 2), 850 }, { 851 /* pwm2-1 */ 852 .bank_num = 1, 853 .pin = 12, 854 .func = 2, 855 .route_offset = 0x50, 856 .route_val = BIT(16 + 2) | BIT(2), 857 }, { 858 /* pwm3-0 */ 859 .bank_num = 3, 860 .pin = 26, 861 .func = 1, 862 .route_offset = 0x50, 863 .route_val = BIT(16 + 3), 864 }, { 865 /* pwm3-1 */ 866 .bank_num = 1, 867 .pin = 11, 868 .func = 2, 869 .route_offset = 0x50, 870 .route_val = BIT(16 + 3) | BIT(3), 871 }, { 872 /* sdio-0_d0 */ 873 .bank_num = 1, 874 .pin = 1, 875 .func = 1, 876 .route_offset = 0x50, 877 .route_val = BIT(16 + 4), 878 }, { 879 /* sdio-1_d0 */ 880 .bank_num = 3, 881 .pin = 2, 882 .func = 1, 883 .route_offset = 0x50, 884 .route_val = BIT(16 + 4) | BIT(4), 885 }, { 886 /* spi-0_rx */ 887 .bank_num = 0, 888 .pin = 13, 889 .func = 2, 890 .route_offset = 0x50, 891 .route_val = BIT(16 + 5), 892 }, { 893 /* spi-1_rx */ 894 .bank_num = 2, 895 .pin = 0, 896 .func = 2, 897 .route_offset = 0x50, 898 .route_val = BIT(16 + 5) | BIT(5), 899 }, { 900 /* emmc-0_cmd */ 901 .bank_num = 1, 902 .pin = 22, 903 .func = 2, 904 .route_offset = 0x50, 905 .route_val = BIT(16 + 7), 906 }, { 907 /* emmc-1_cmd */ 908 .bank_num = 2, 909 .pin = 4, 910 .func = 2, 911 .route_offset = 0x50, 912 .route_val = BIT(16 + 7) | BIT(7), 913 }, { 914 /* uart2-0_rx */ 915 .bank_num = 1, 916 .pin = 19, 917 .func = 2, 918 .route_offset = 0x50, 919 .route_val = BIT(16 + 8), 920 }, { 921 /* uart2-1_rx */ 922 .bank_num = 1, 923 .pin = 10, 924 .func = 2, 925 .route_offset = 0x50, 926 .route_val = BIT(16 + 8) | BIT(8), 927 }, { 928 /* uart1-0_rx */ 929 .bank_num = 1, 930 .pin = 10, 931 .func = 1, 932 .route_offset = 0x50, 933 .route_val = BIT(16 + 11), 934 }, { 935 /* uart1-1_rx */ 936 .bank_num = 3, 937 .pin = 13, 938 .func = 1, 939 .route_offset = 0x50, 940 .route_val = BIT(16 + 11) | BIT(11), 941 }, 942 }; 943 944 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 945 { 946 /* edphdmi_cecinoutt1 */ 947 .bank_num = 7, 948 .pin = 16, 949 .func = 2, 950 .route_offset = 0x264, 951 .route_val = BIT(16 + 12) | BIT(12), 952 }, { 953 /* edphdmi_cecinout */ 954 .bank_num = 7, 955 .pin = 23, 956 .func = 4, 957 .route_offset = 0x264, 958 .route_val = BIT(16 + 12), 959 }, 960 }; 961 962 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 963 { 964 /* rtc_clk */ 965 .bank_num = 0, 966 .pin = 19, 967 .func = 1, 968 .route_offset = 0x314, 969 .route_val = BIT(16 + 0) | BIT(0), 970 }, { 971 /* uart2_rxm0 */ 972 .bank_num = 1, 973 .pin = 22, 974 .func = 2, 975 .route_offset = 0x314, 976 .route_val = BIT(16 + 2) | BIT(16 + 3), 977 }, { 978 /* uart2_rxm1 */ 979 .bank_num = 4, 980 .pin = 26, 981 .func = 2, 982 .route_offset = 0x314, 983 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 984 }, { 985 /* i2c3_sdam0 */ 986 .bank_num = 0, 987 .pin = 23, 988 .func = 2, 989 .route_offset = 0x314, 990 .route_val = BIT(16 + 4), 991 }, { 992 /* i2c3_sdam1 */ 993 .bank_num = 3, 994 .pin = 12, 995 .func = 2, 996 .route_offset = 0x314, 997 .route_val = BIT(16 + 4) | BIT(4), 998 }, { 999 /* i2s-8ch-1-sclktxm0 */ 1000 .bank_num = 1, 1001 .pin = 3, 1002 .func = 2, 1003 .route_offset = 0x308, 1004 .route_val = BIT(16 + 3), 1005 }, { 1006 /* i2s-8ch-1-sclkrxm0 */ 1007 .bank_num = 1, 1008 .pin = 4, 1009 .func = 2, 1010 .route_offset = 0x308, 1011 .route_val = BIT(16 + 3), 1012 }, { 1013 /* i2s-8ch-1-sclktxm1 */ 1014 .bank_num = 1, 1015 .pin = 13, 1016 .func = 2, 1017 .route_offset = 0x308, 1018 .route_val = BIT(16 + 3) | BIT(3), 1019 }, { 1020 /* i2s-8ch-1-sclkrxm1 */ 1021 .bank_num = 1, 1022 .pin = 14, 1023 .func = 2, 1024 .route_offset = 0x308, 1025 .route_val = BIT(16 + 3) | BIT(3), 1026 }, { 1027 /* pdm-clkm0 */ 1028 .bank_num = 1, 1029 .pin = 4, 1030 .func = 3, 1031 .route_offset = 0x308, 1032 .route_val = BIT(16 + 12) | BIT(16 + 13), 1033 }, { 1034 /* pdm-clkm1 */ 1035 .bank_num = 1, 1036 .pin = 14, 1037 .func = 4, 1038 .route_offset = 0x308, 1039 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1040 }, { 1041 /* pdm-clkm2 */ 1042 .bank_num = 2, 1043 .pin = 6, 1044 .func = 2, 1045 .route_offset = 0x308, 1046 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1047 }, { 1048 /* pdm-clkm-m2 */ 1049 .bank_num = 2, 1050 .pin = 4, 1051 .func = 3, 1052 .route_offset = 0x600, 1053 .route_val = BIT(16 + 2) | BIT(2), 1054 }, 1055 }; 1056 1057 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1058 { 1059 /* rtc_clk */ 1060 .bank_num = 0, 1061 .pin = 19, 1062 .func = 1, 1063 .route_offset = 0x314, 1064 .route_val = BIT(16 + 0) | BIT(0), 1065 }, { 1066 /* uart2_rxm0 */ 1067 .bank_num = 1, 1068 .pin = 22, 1069 .func = 2, 1070 .route_offset = 0x314, 1071 .route_val = BIT(16 + 2) | BIT(16 + 3), 1072 }, { 1073 /* uart2_rxm1 */ 1074 .bank_num = 4, 1075 .pin = 26, 1076 .func = 2, 1077 .route_offset = 0x314, 1078 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1079 }, { 1080 /* i2c3_sdam0 */ 1081 .bank_num = 0, 1082 .pin = 15, 1083 .func = 2, 1084 .route_offset = 0x608, 1085 .route_val = BIT(16 + 8) | BIT(16 + 9), 1086 }, { 1087 /* i2c3_sdam1 */ 1088 .bank_num = 3, 1089 .pin = 12, 1090 .func = 2, 1091 .route_offset = 0x608, 1092 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1093 }, { 1094 /* i2c3_sdam2 */ 1095 .bank_num = 2, 1096 .pin = 0, 1097 .func = 3, 1098 .route_offset = 0x608, 1099 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1100 }, { 1101 /* i2s-8ch-1-sclktxm0 */ 1102 .bank_num = 1, 1103 .pin = 3, 1104 .func = 2, 1105 .route_offset = 0x308, 1106 .route_val = BIT(16 + 3), 1107 }, { 1108 /* i2s-8ch-1-sclkrxm0 */ 1109 .bank_num = 1, 1110 .pin = 4, 1111 .func = 2, 1112 .route_offset = 0x308, 1113 .route_val = BIT(16 + 3), 1114 }, { 1115 /* i2s-8ch-1-sclktxm1 */ 1116 .bank_num = 1, 1117 .pin = 13, 1118 .func = 2, 1119 .route_offset = 0x308, 1120 .route_val = BIT(16 + 3) | BIT(3), 1121 }, { 1122 /* i2s-8ch-1-sclkrxm1 */ 1123 .bank_num = 1, 1124 .pin = 14, 1125 .func = 2, 1126 .route_offset = 0x308, 1127 .route_val = BIT(16 + 3) | BIT(3), 1128 }, { 1129 /* pdm-clkm0 */ 1130 .bank_num = 1, 1131 .pin = 4, 1132 .func = 3, 1133 .route_offset = 0x308, 1134 .route_val = BIT(16 + 12) | BIT(16 + 13), 1135 }, { 1136 /* pdm-clkm1 */ 1137 .bank_num = 1, 1138 .pin = 14, 1139 .func = 4, 1140 .route_offset = 0x308, 1141 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1142 }, { 1143 /* pdm-clkm2 */ 1144 .bank_num = 2, 1145 .pin = 6, 1146 .func = 2, 1147 .route_offset = 0x308, 1148 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1149 }, { 1150 /* pdm-clkm-m2 */ 1151 .bank_num = 2, 1152 .pin = 4, 1153 .func = 3, 1154 .route_offset = 0x600, 1155 .route_val = BIT(16 + 2) | BIT(2), 1156 }, { 1157 /* spi1_miso */ 1158 .bank_num = 3, 1159 .pin = 10, 1160 .func = 3, 1161 .route_offset = 0x314, 1162 .route_val = BIT(16 + 9), 1163 }, { 1164 /* spi1_miso_m1 */ 1165 .bank_num = 2, 1166 .pin = 4, 1167 .func = 2, 1168 .route_offset = 0x314, 1169 .route_val = BIT(16 + 9) | BIT(9), 1170 }, { 1171 /* owire_m0 */ 1172 .bank_num = 0, 1173 .pin = 11, 1174 .func = 3, 1175 .route_offset = 0x314, 1176 .route_val = BIT(16 + 10) | BIT(16 + 11), 1177 }, { 1178 /* owire_m1 */ 1179 .bank_num = 1, 1180 .pin = 22, 1181 .func = 7, 1182 .route_offset = 0x314, 1183 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1184 }, { 1185 /* owire_m2 */ 1186 .bank_num = 2, 1187 .pin = 2, 1188 .func = 5, 1189 .route_offset = 0x314, 1190 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1191 }, { 1192 /* can_rxd_m0 */ 1193 .bank_num = 0, 1194 .pin = 11, 1195 .func = 2, 1196 .route_offset = 0x314, 1197 .route_val = BIT(16 + 12) | BIT(16 + 13), 1198 }, { 1199 /* can_rxd_m1 */ 1200 .bank_num = 1, 1201 .pin = 22, 1202 .func = 5, 1203 .route_offset = 0x314, 1204 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1205 }, { 1206 /* can_rxd_m2 */ 1207 .bank_num = 2, 1208 .pin = 2, 1209 .func = 4, 1210 .route_offset = 0x314, 1211 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1212 }, { 1213 /* mac_rxd0_m0 */ 1214 .bank_num = 1, 1215 .pin = 20, 1216 .func = 3, 1217 .route_offset = 0x314, 1218 .route_val = BIT(16 + 14), 1219 }, { 1220 /* mac_rxd0_m1 */ 1221 .bank_num = 4, 1222 .pin = 2, 1223 .func = 2, 1224 .route_offset = 0x314, 1225 .route_val = BIT(16 + 14) | BIT(14), 1226 }, { 1227 /* uart3_rx */ 1228 .bank_num = 3, 1229 .pin = 12, 1230 .func = 4, 1231 .route_offset = 0x314, 1232 .route_val = BIT(16 + 15), 1233 }, { 1234 /* uart3_rx_m1 */ 1235 .bank_num = 0, 1236 .pin = 17, 1237 .func = 3, 1238 .route_offset = 0x314, 1239 .route_val = BIT(16 + 15) | BIT(15), 1240 }, 1241 }; 1242 1243 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1244 { 1245 /* uart2dbg_rxm0 */ 1246 .bank_num = 1, 1247 .pin = 1, 1248 .func = 2, 1249 .route_offset = 0x50, 1250 .route_val = BIT(16) | BIT(16 + 1), 1251 }, { 1252 /* uart2dbg_rxm1 */ 1253 .bank_num = 2, 1254 .pin = 1, 1255 .func = 1, 1256 .route_offset = 0x50, 1257 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1258 }, { 1259 /* gmac-m1_rxd0 */ 1260 .bank_num = 1, 1261 .pin = 11, 1262 .func = 2, 1263 .route_offset = 0x50, 1264 .route_val = BIT(16 + 2) | BIT(2), 1265 }, { 1266 /* gmac-m1-optimized_rxd3 */ 1267 .bank_num = 1, 1268 .pin = 14, 1269 .func = 2, 1270 .route_offset = 0x50, 1271 .route_val = BIT(16 + 10) | BIT(10), 1272 }, { 1273 /* pdm_sdi0m0 */ 1274 .bank_num = 2, 1275 .pin = 19, 1276 .func = 2, 1277 .route_offset = 0x50, 1278 .route_val = BIT(16 + 3), 1279 }, { 1280 /* pdm_sdi0m1 */ 1281 .bank_num = 1, 1282 .pin = 23, 1283 .func = 3, 1284 .route_offset = 0x50, 1285 .route_val = BIT(16 + 3) | BIT(3), 1286 }, { 1287 /* spi_rxdm2 */ 1288 .bank_num = 3, 1289 .pin = 2, 1290 .func = 4, 1291 .route_offset = 0x50, 1292 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1293 }, { 1294 /* i2s2_sdim0 */ 1295 .bank_num = 1, 1296 .pin = 24, 1297 .func = 1, 1298 .route_offset = 0x50, 1299 .route_val = BIT(16 + 6), 1300 }, { 1301 /* i2s2_sdim1 */ 1302 .bank_num = 3, 1303 .pin = 2, 1304 .func = 6, 1305 .route_offset = 0x50, 1306 .route_val = BIT(16 + 6) | BIT(6), 1307 }, { 1308 /* card_iom1 */ 1309 .bank_num = 2, 1310 .pin = 22, 1311 .func = 3, 1312 .route_offset = 0x50, 1313 .route_val = BIT(16 + 7) | BIT(7), 1314 }, { 1315 /* tsp_d5m1 */ 1316 .bank_num = 2, 1317 .pin = 16, 1318 .func = 3, 1319 .route_offset = 0x50, 1320 .route_val = BIT(16 + 8) | BIT(8), 1321 }, { 1322 /* cif_data5m1 */ 1323 .bank_num = 2, 1324 .pin = 16, 1325 .func = 4, 1326 .route_offset = 0x50, 1327 .route_val = BIT(16 + 9) | BIT(9), 1328 }, 1329 }; 1330 1331 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1332 { 1333 /* uart2dbga_rx */ 1334 .bank_num = 4, 1335 .pin = 8, 1336 .func = 2, 1337 .route_offset = 0xe21c, 1338 .route_val = BIT(16 + 10) | BIT(16 + 11), 1339 }, { 1340 /* uart2dbgb_rx */ 1341 .bank_num = 4, 1342 .pin = 16, 1343 .func = 2, 1344 .route_offset = 0xe21c, 1345 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1346 }, { 1347 /* uart2dbgc_rx */ 1348 .bank_num = 4, 1349 .pin = 19, 1350 .func = 1, 1351 .route_offset = 0xe21c, 1352 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1353 }, { 1354 /* pcie_clkreqn */ 1355 .bank_num = 2, 1356 .pin = 26, 1357 .func = 2, 1358 .route_offset = 0xe21c, 1359 .route_val = BIT(16 + 14), 1360 }, { 1361 /* pcie_clkreqnb */ 1362 .bank_num = 4, 1363 .pin = 24, 1364 .func = 1, 1365 .route_offset = 0xe21c, 1366 .route_val = BIT(16 + 14) | BIT(14), 1367 }, 1368 }; 1369 1370 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1371 int mux, u32 *reg, u32 *value) 1372 { 1373 struct rockchip_pinctrl_priv *priv = bank->priv; 1374 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1375 struct rockchip_mux_route_data *data; 1376 int i; 1377 1378 for (i = 0; i < ctrl->niomux_routes; i++) { 1379 data = &ctrl->iomux_routes[i]; 1380 if ((data->bank_num == bank->bank_num) && 1381 (data->pin == pin) && (data->func == mux)) 1382 break; 1383 } 1384 1385 if (i >= ctrl->niomux_routes) 1386 return false; 1387 1388 *reg = data->route_offset; 1389 *value = data->route_val; 1390 1391 return true; 1392 } 1393 1394 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1395 { 1396 struct rockchip_pinctrl_priv *priv = bank->priv; 1397 int iomux_num = (pin / 8); 1398 struct regmap *regmap; 1399 unsigned int val; 1400 int reg, ret, mask, mux_type; 1401 u8 bit; 1402 1403 if (iomux_num > 3) 1404 return -EINVAL; 1405 1406 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1407 debug("pin %d is unrouted\n", pin); 1408 return -EINVAL; 1409 } 1410 1411 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1412 return RK_FUNC_GPIO; 1413 1414 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1415 ? priv->regmap_pmu : priv->regmap_base; 1416 1417 /* get basic quadrupel of mux registers and the correct reg inside */ 1418 mux_type = bank->iomux[iomux_num].type; 1419 reg = bank->iomux[iomux_num].offset; 1420 if (mux_type & IOMUX_WIDTH_4BIT) { 1421 if ((pin % 8) >= 4) 1422 reg += 0x4; 1423 bit = (pin % 4) * 4; 1424 mask = 0xf; 1425 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1426 if ((pin % 8) >= 5) 1427 reg += 0x4; 1428 bit = (pin % 8 % 5) * 3; 1429 mask = 0x7; 1430 } else { 1431 bit = (pin % 8) * 2; 1432 mask = 0x3; 1433 } 1434 1435 if (bank->recalced_mask & BIT(pin)) 1436 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1437 1438 ret = regmap_read(regmap, reg, &val); 1439 if (ret) 1440 return ret; 1441 1442 return ((val >> bit) & mask); 1443 } 1444 1445 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1446 int index) 1447 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1448 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1449 1450 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1451 } 1452 1453 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1454 int pin, int mux) 1455 { 1456 int iomux_num = (pin / 8); 1457 1458 if (iomux_num > 3) 1459 return -EINVAL; 1460 1461 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1462 debug("pin %d is unrouted\n", pin); 1463 return -EINVAL; 1464 } 1465 1466 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1467 if (mux != IOMUX_GPIO_ONLY) { 1468 debug("pin %d only supports a gpio mux\n", pin); 1469 return -ENOTSUPP; 1470 } 1471 } 1472 1473 return 0; 1474 } 1475 1476 /* 1477 * Set a new mux function for a pin. 1478 * 1479 * The register is divided into the upper and lower 16 bit. When changing 1480 * a value, the previous register value is not read and changed. Instead 1481 * it seems the changed bits are marked in the upper 16 bit, while the 1482 * changed value gets set in the same offset in the lower 16 bit. 1483 * All pin settings seem to be 2 bit wide in both the upper and lower 1484 * parts. 1485 * @bank: pin bank to change 1486 * @pin: pin to change 1487 * @mux: new mux function to set 1488 */ 1489 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1490 { 1491 struct rockchip_pinctrl_priv *priv = bank->priv; 1492 int iomux_num = (pin / 8); 1493 struct regmap *regmap; 1494 int reg, ret, mask, mux_type; 1495 u8 bit; 1496 u32 data, route_reg, route_val; 1497 1498 ret = rockchip_verify_mux(bank, pin, mux); 1499 if (ret < 0) 1500 return ret; 1501 1502 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1503 return 0; 1504 1505 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1506 1507 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1508 ? priv->regmap_pmu : priv->regmap_base; 1509 1510 /* get basic quadrupel of mux registers and the correct reg inside */ 1511 mux_type = bank->iomux[iomux_num].type; 1512 reg = bank->iomux[iomux_num].offset; 1513 if (mux_type & IOMUX_WIDTH_4BIT) { 1514 if ((pin % 8) >= 4) 1515 reg += 0x4; 1516 bit = (pin % 4) * 4; 1517 mask = 0xf; 1518 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1519 if ((pin % 8) >= 5) 1520 reg += 0x4; 1521 bit = (pin % 8 % 5) * 3; 1522 mask = 0x7; 1523 } else { 1524 bit = (pin % 8) * 2; 1525 mask = 0x3; 1526 } 1527 1528 if (bank->recalced_mask & BIT(pin)) 1529 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1530 1531 if (bank->route_mask & BIT(pin)) { 1532 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1533 &route_val)) { 1534 ret = regmap_write(regmap, route_reg, route_val); 1535 if (ret) 1536 return ret; 1537 } 1538 } 1539 1540 if (mux_type & IOMUX_WRITABLE_32BIT) { 1541 regmap_read(regmap, reg, &data); 1542 data &= ~(mask << bit); 1543 } else { 1544 data = (mask << (bit + 16)); 1545 } 1546 1547 data |= (mux & mask) << bit; 1548 ret = regmap_write(regmap, reg, data); 1549 1550 return ret; 1551 } 1552 1553 #define PX30_PULL_PMU_OFFSET 0x10 1554 #define PX30_PULL_GRF_OFFSET 0x60 1555 #define PX30_PULL_BITS_PER_PIN 2 1556 #define PX30_PULL_PINS_PER_REG 8 1557 #define PX30_PULL_BANK_STRIDE 16 1558 1559 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1560 int pin_num, struct regmap **regmap, 1561 int *reg, u8 *bit) 1562 { 1563 struct rockchip_pinctrl_priv *priv = bank->priv; 1564 1565 /* The first 32 pins of the first bank are located in PMU */ 1566 if (bank->bank_num == 0) { 1567 *regmap = priv->regmap_pmu; 1568 *reg = PX30_PULL_PMU_OFFSET; 1569 } else { 1570 *regmap = priv->regmap_base; 1571 *reg = PX30_PULL_GRF_OFFSET; 1572 1573 /* correct the offset, as we're starting with the 2nd bank */ 1574 *reg -= 0x10; 1575 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1576 } 1577 1578 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1579 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1580 *bit *= PX30_PULL_BITS_PER_PIN; 1581 } 1582 1583 #define PX30_DRV_PMU_OFFSET 0x20 1584 #define PX30_DRV_GRF_OFFSET 0xf0 1585 #define PX30_DRV_BITS_PER_PIN 2 1586 #define PX30_DRV_PINS_PER_REG 8 1587 #define PX30_DRV_BANK_STRIDE 16 1588 1589 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1590 int pin_num, struct regmap **regmap, 1591 int *reg, u8 *bit) 1592 { 1593 struct rockchip_pinctrl_priv *priv = bank->priv; 1594 1595 /* The first 32 pins of the first bank are located in PMU */ 1596 if (bank->bank_num == 0) { 1597 *regmap = priv->regmap_pmu; 1598 *reg = PX30_DRV_PMU_OFFSET; 1599 } else { 1600 *regmap = priv->regmap_base; 1601 *reg = PX30_DRV_GRF_OFFSET; 1602 1603 /* correct the offset, as we're starting with the 2nd bank */ 1604 *reg -= 0x10; 1605 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1606 } 1607 1608 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1609 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1610 *bit *= PX30_DRV_BITS_PER_PIN; 1611 } 1612 1613 #define PX30_SCHMITT_PMU_OFFSET 0x38 1614 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1615 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1616 #define PX30_SCHMITT_BANK_STRIDE 16 1617 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1618 1619 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1620 int pin_num, 1621 struct regmap **regmap, 1622 int *reg, u8 *bit) 1623 { 1624 struct rockchip_pinctrl_priv *priv = bank->priv; 1625 int pins_per_reg; 1626 1627 if (bank->bank_num == 0) { 1628 *regmap = priv->regmap_pmu; 1629 *reg = PX30_SCHMITT_PMU_OFFSET; 1630 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1631 } else { 1632 *regmap = priv->regmap_base; 1633 *reg = PX30_SCHMITT_GRF_OFFSET; 1634 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1635 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1636 } 1637 *reg += ((pin_num / pins_per_reg) * 4); 1638 *bit = pin_num % pins_per_reg; 1639 1640 return 0; 1641 } 1642 1643 #define RV1108_PULL_PMU_OFFSET 0x10 1644 #define RV1108_PULL_OFFSET 0x110 1645 #define RV1108_PULL_PINS_PER_REG 8 1646 #define RV1108_PULL_BITS_PER_PIN 2 1647 #define RV1108_PULL_BANK_STRIDE 16 1648 1649 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1650 int pin_num, struct regmap **regmap, 1651 int *reg, u8 *bit) 1652 { 1653 struct rockchip_pinctrl_priv *priv = bank->priv; 1654 1655 /* The first 24 pins of the first bank are located in PMU */ 1656 if (bank->bank_num == 0) { 1657 *regmap = priv->regmap_pmu; 1658 *reg = RV1108_PULL_PMU_OFFSET; 1659 } else { 1660 *reg = RV1108_PULL_OFFSET; 1661 *regmap = priv->regmap_base; 1662 /* correct the offset, as we're starting with the 2nd bank */ 1663 *reg -= 0x10; 1664 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1665 } 1666 1667 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1668 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1669 *bit *= RV1108_PULL_BITS_PER_PIN; 1670 } 1671 1672 #define RV1108_DRV_PMU_OFFSET 0x20 1673 #define RV1108_DRV_GRF_OFFSET 0x210 1674 #define RV1108_DRV_BITS_PER_PIN 2 1675 #define RV1108_DRV_PINS_PER_REG 8 1676 #define RV1108_DRV_BANK_STRIDE 16 1677 1678 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1679 int pin_num, struct regmap **regmap, 1680 int *reg, u8 *bit) 1681 { 1682 struct rockchip_pinctrl_priv *priv = bank->priv; 1683 1684 /* The first 24 pins of the first bank are located in PMU */ 1685 if (bank->bank_num == 0) { 1686 *regmap = priv->regmap_pmu; 1687 *reg = RV1108_DRV_PMU_OFFSET; 1688 } else { 1689 *regmap = priv->regmap_base; 1690 *reg = RV1108_DRV_GRF_OFFSET; 1691 1692 /* correct the offset, as we're starting with the 2nd bank */ 1693 *reg -= 0x10; 1694 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1695 } 1696 1697 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1698 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1699 *bit *= RV1108_DRV_BITS_PER_PIN; 1700 } 1701 1702 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1703 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1704 #define RV1108_SCHMITT_BANK_STRIDE 8 1705 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1706 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1707 1708 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1709 int pin_num, 1710 struct regmap **regmap, 1711 int *reg, u8 *bit) 1712 { 1713 struct rockchip_pinctrl_priv *priv = bank->priv; 1714 int pins_per_reg; 1715 1716 if (bank->bank_num == 0) { 1717 *regmap = priv->regmap_pmu; 1718 *reg = RV1108_SCHMITT_PMU_OFFSET; 1719 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1720 } else { 1721 *regmap = priv->regmap_base; 1722 *reg = RV1108_SCHMITT_GRF_OFFSET; 1723 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1724 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1725 } 1726 *reg += ((pin_num / pins_per_reg) * 4); 1727 *bit = pin_num % pins_per_reg; 1728 1729 return 0; 1730 } 1731 1732 #define RK1808_PULL_PMU_OFFSET 0x10 1733 #define RK1808_PULL_GRF_OFFSET 0x80 1734 #define RK1808_PULL_PINS_PER_REG 8 1735 #define RK1808_PULL_BITS_PER_PIN 2 1736 #define RK1808_PULL_BANK_STRIDE 16 1737 1738 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1739 int pin_num, 1740 struct regmap **regmap, 1741 int *reg, u8 *bit) 1742 { 1743 struct rockchip_pinctrl_priv *priv = bank->priv; 1744 1745 if (bank->bank_num == 0) { 1746 *regmap = priv->regmap_pmu; 1747 *reg = RK1808_PULL_PMU_OFFSET; 1748 } else { 1749 *reg = RK1808_PULL_GRF_OFFSET; 1750 *regmap = priv->regmap_base; 1751 } 1752 1753 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1754 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1755 *bit *= RK1808_PULL_BITS_PER_PIN; 1756 } 1757 1758 #define RK1808_DRV_PMU_OFFSET 0x20 1759 #define RK1808_DRV_GRF_OFFSET 0x140 1760 #define RK1808_DRV_BITS_PER_PIN 2 1761 #define RK1808_DRV_PINS_PER_REG 8 1762 #define RK1808_DRV_BANK_STRIDE 16 1763 1764 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1765 int pin_num, 1766 struct regmap **regmap, 1767 int *reg, u8 *bit) 1768 { 1769 struct rockchip_pinctrl_priv *priv = bank->priv; 1770 1771 if (bank->bank_num == 0) { 1772 *regmap = priv->regmap_pmu; 1773 *reg = RK1808_DRV_PMU_OFFSET; 1774 } else { 1775 *regmap = priv->regmap_base; 1776 *reg = RK1808_DRV_GRF_OFFSET; 1777 } 1778 1779 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1780 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1781 *bit *= RK1808_DRV_BITS_PER_PIN; 1782 } 1783 1784 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1785 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1786 #define RK1808_SCHMITT_BANK_STRIDE 16 1787 #define RK1808_SCHMITT_PINS_PER_REG 8 1788 1789 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1790 int pin_num, 1791 struct regmap **regmap, 1792 int *reg, u8 *bit) 1793 { 1794 struct rockchip_pinctrl_priv *priv = bank->priv; 1795 1796 if (bank->bank_num == 0) { 1797 *regmap = priv->regmap_pmu; 1798 *reg = RK1808_SCHMITT_PMU_OFFSET; 1799 } else { 1800 *regmap = priv->regmap_base; 1801 *reg = RK1808_SCHMITT_GRF_OFFSET; 1802 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1803 } 1804 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1805 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1806 1807 return 0; 1808 } 1809 1810 #define RK2928_PULL_OFFSET 0x118 1811 #define RK2928_PULL_PINS_PER_REG 16 1812 #define RK2928_PULL_BANK_STRIDE 8 1813 1814 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1815 int pin_num, struct regmap **regmap, 1816 int *reg, u8 *bit) 1817 { 1818 struct rockchip_pinctrl_priv *priv = bank->priv; 1819 1820 *regmap = priv->regmap_base; 1821 *reg = RK2928_PULL_OFFSET; 1822 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1823 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1824 1825 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1826 }; 1827 1828 #define RK3128_PULL_OFFSET 0x118 1829 1830 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1831 int pin_num, struct regmap **regmap, 1832 int *reg, u8 *bit) 1833 { 1834 struct rockchip_pinctrl_priv *priv = bank->priv; 1835 1836 *regmap = priv->regmap_base; 1837 *reg = RK3128_PULL_OFFSET; 1838 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1839 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1840 1841 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1842 } 1843 1844 #define RK3188_PULL_OFFSET 0x164 1845 #define RK3188_PULL_BITS_PER_PIN 2 1846 #define RK3188_PULL_PINS_PER_REG 8 1847 #define RK3188_PULL_BANK_STRIDE 16 1848 #define RK3188_PULL_PMU_OFFSET 0x64 1849 1850 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1851 int pin_num, struct regmap **regmap, 1852 int *reg, u8 *bit) 1853 { 1854 struct rockchip_pinctrl_priv *priv = bank->priv; 1855 1856 /* The first 12 pins of the first bank are located elsewhere */ 1857 if (bank->bank_num == 0 && pin_num < 12) { 1858 *regmap = priv->regmap_pmu; 1859 *reg = RK3188_PULL_PMU_OFFSET; 1860 1861 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1862 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1863 *bit *= RK3188_PULL_BITS_PER_PIN; 1864 } else { 1865 *regmap = priv->regmap_base; 1866 *reg = RK3188_PULL_OFFSET; 1867 1868 /* correct the offset, as it is the 2nd pull register */ 1869 *reg -= 4; 1870 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1871 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1872 1873 /* 1874 * The bits in these registers have an inverse ordering 1875 * with the lowest pin being in bits 15:14 and the highest 1876 * pin in bits 1:0 1877 */ 1878 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1879 *bit *= RK3188_PULL_BITS_PER_PIN; 1880 } 1881 } 1882 1883 #define RK3288_PULL_OFFSET 0x140 1884 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1885 int pin_num, struct regmap **regmap, 1886 int *reg, u8 *bit) 1887 { 1888 struct rockchip_pinctrl_priv *priv = bank->priv; 1889 1890 /* The first 24 pins of the first bank are located in PMU */ 1891 if (bank->bank_num == 0) { 1892 *regmap = priv->regmap_pmu; 1893 *reg = RK3188_PULL_PMU_OFFSET; 1894 1895 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1896 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1897 *bit *= RK3188_PULL_BITS_PER_PIN; 1898 } else { 1899 *regmap = priv->regmap_base; 1900 *reg = RK3288_PULL_OFFSET; 1901 1902 /* correct the offset, as we're starting with the 2nd bank */ 1903 *reg -= 0x10; 1904 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1905 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1906 1907 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1908 *bit *= RK3188_PULL_BITS_PER_PIN; 1909 } 1910 } 1911 1912 #define RK3288_DRV_PMU_OFFSET 0x70 1913 #define RK3288_DRV_GRF_OFFSET 0x1c0 1914 #define RK3288_DRV_BITS_PER_PIN 2 1915 #define RK3288_DRV_PINS_PER_REG 8 1916 #define RK3288_DRV_BANK_STRIDE 16 1917 1918 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1919 int pin_num, struct regmap **regmap, 1920 int *reg, u8 *bit) 1921 { 1922 struct rockchip_pinctrl_priv *priv = bank->priv; 1923 1924 /* The first 24 pins of the first bank are located in PMU */ 1925 if (bank->bank_num == 0) { 1926 *regmap = priv->regmap_pmu; 1927 *reg = RK3288_DRV_PMU_OFFSET; 1928 1929 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1930 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1931 *bit *= RK3288_DRV_BITS_PER_PIN; 1932 } else { 1933 *regmap = priv->regmap_base; 1934 *reg = RK3288_DRV_GRF_OFFSET; 1935 1936 /* correct the offset, as we're starting with the 2nd bank */ 1937 *reg -= 0x10; 1938 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1939 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1940 1941 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1942 *bit *= RK3288_DRV_BITS_PER_PIN; 1943 } 1944 } 1945 1946 #define RK3228_PULL_OFFSET 0x100 1947 1948 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1949 int pin_num, struct regmap **regmap, 1950 int *reg, u8 *bit) 1951 { 1952 struct rockchip_pinctrl_priv *priv = bank->priv; 1953 1954 *regmap = priv->regmap_base; 1955 *reg = RK3228_PULL_OFFSET; 1956 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1957 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1958 1959 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1960 *bit *= RK3188_PULL_BITS_PER_PIN; 1961 } 1962 1963 #define RK3228_DRV_GRF_OFFSET 0x200 1964 1965 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1966 int pin_num, struct regmap **regmap, 1967 int *reg, u8 *bit) 1968 { 1969 struct rockchip_pinctrl_priv *priv = bank->priv; 1970 1971 *regmap = priv->regmap_base; 1972 *reg = RK3228_DRV_GRF_OFFSET; 1973 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1974 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1975 1976 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1977 *bit *= RK3288_DRV_BITS_PER_PIN; 1978 } 1979 1980 #define RK3308_PULL_OFFSET 0xa0 1981 1982 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1983 int pin_num, struct regmap **regmap, 1984 int *reg, u8 *bit) 1985 { 1986 struct rockchip_pinctrl_priv *priv = bank->priv; 1987 1988 *regmap = priv->regmap_base; 1989 *reg = RK3308_PULL_OFFSET; 1990 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1991 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1992 1993 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1994 *bit *= RK3188_PULL_BITS_PER_PIN; 1995 } 1996 1997 #define RK3308_DRV_GRF_OFFSET 0x100 1998 1999 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2000 int pin_num, struct regmap **regmap, 2001 int *reg, u8 *bit) 2002 { 2003 struct rockchip_pinctrl_priv *priv = bank->priv; 2004 2005 *regmap = priv->regmap_base; 2006 *reg = RK3308_DRV_GRF_OFFSET; 2007 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2008 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2009 2010 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2011 *bit *= RK3288_DRV_BITS_PER_PIN; 2012 } 2013 2014 #define RK3308_SCHMITT_PINS_PER_REG 8 2015 #define RK3308_SCHMITT_BANK_STRIDE 16 2016 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2017 2018 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2019 int pin_num, 2020 struct regmap **regmap, 2021 int *reg, u8 *bit) 2022 { 2023 struct rockchip_pinctrl_priv *priv = bank->priv; 2024 2025 *regmap = priv->regmap_base; 2026 *reg = RK3308_SCHMITT_GRF_OFFSET; 2027 2028 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2029 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2030 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2031 2032 return 0; 2033 } 2034 2035 #define RK3368_PULL_GRF_OFFSET 0x100 2036 #define RK3368_PULL_PMU_OFFSET 0x10 2037 2038 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2039 int pin_num, struct regmap **regmap, 2040 int *reg, u8 *bit) 2041 { 2042 struct rockchip_pinctrl_priv *priv = bank->priv; 2043 2044 /* The first 32 pins of the first bank are located in PMU */ 2045 if (bank->bank_num == 0) { 2046 *regmap = priv->regmap_pmu; 2047 *reg = RK3368_PULL_PMU_OFFSET; 2048 2049 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2050 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2051 *bit *= RK3188_PULL_BITS_PER_PIN; 2052 } else { 2053 *regmap = priv->regmap_base; 2054 *reg = RK3368_PULL_GRF_OFFSET; 2055 2056 /* correct the offset, as we're starting with the 2nd bank */ 2057 *reg -= 0x10; 2058 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2059 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2060 2061 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2062 *bit *= RK3188_PULL_BITS_PER_PIN; 2063 } 2064 } 2065 2066 #define RK3368_DRV_PMU_OFFSET 0x20 2067 #define RK3368_DRV_GRF_OFFSET 0x200 2068 2069 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2070 int pin_num, struct regmap **regmap, 2071 int *reg, u8 *bit) 2072 { 2073 struct rockchip_pinctrl_priv *priv = bank->priv; 2074 2075 /* The first 32 pins of the first bank are located in PMU */ 2076 if (bank->bank_num == 0) { 2077 *regmap = priv->regmap_pmu; 2078 *reg = RK3368_DRV_PMU_OFFSET; 2079 2080 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2081 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2082 *bit *= RK3288_DRV_BITS_PER_PIN; 2083 } else { 2084 *regmap = priv->regmap_base; 2085 *reg = RK3368_DRV_GRF_OFFSET; 2086 2087 /* correct the offset, as we're starting with the 2nd bank */ 2088 *reg -= 0x10; 2089 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2090 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2091 2092 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2093 *bit *= RK3288_DRV_BITS_PER_PIN; 2094 } 2095 } 2096 2097 #define RK3399_PULL_GRF_OFFSET 0xe040 2098 #define RK3399_PULL_PMU_OFFSET 0x40 2099 #define RK3399_DRV_3BITS_PER_PIN 3 2100 2101 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2102 int pin_num, struct regmap **regmap, 2103 int *reg, u8 *bit) 2104 { 2105 struct rockchip_pinctrl_priv *priv = bank->priv; 2106 2107 /* The bank0:16 and bank1:32 pins are located in PMU */ 2108 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2109 *regmap = priv->regmap_pmu; 2110 *reg = RK3399_PULL_PMU_OFFSET; 2111 2112 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2113 2114 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2115 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2116 *bit *= RK3188_PULL_BITS_PER_PIN; 2117 } else { 2118 *regmap = priv->regmap_base; 2119 *reg = RK3399_PULL_GRF_OFFSET; 2120 2121 /* correct the offset, as we're starting with the 3rd bank */ 2122 *reg -= 0x20; 2123 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2124 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2125 2126 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2127 *bit *= RK3188_PULL_BITS_PER_PIN; 2128 } 2129 } 2130 2131 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2132 int pin_num, struct regmap **regmap, 2133 int *reg, u8 *bit) 2134 { 2135 struct rockchip_pinctrl_priv *priv = bank->priv; 2136 int drv_num = (pin_num / 8); 2137 2138 /* The bank0:16 and bank1:32 pins are located in PMU */ 2139 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2140 *regmap = priv->regmap_pmu; 2141 else 2142 *regmap = priv->regmap_base; 2143 2144 *reg = bank->drv[drv_num].offset; 2145 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2146 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2147 *bit = (pin_num % 8) * 3; 2148 else 2149 *bit = (pin_num % 8) * 2; 2150 } 2151 2152 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2153 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2154 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2155 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2156 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2157 { 4, 7, 10, 13, 16, 19, 22, 26 } 2158 }; 2159 2160 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2161 int pin_num, int strength) 2162 { 2163 struct rockchip_pinctrl_priv *priv = bank->priv; 2164 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2165 struct regmap *regmap; 2166 int reg, ret, i; 2167 u32 data, rmask_bits, temp; 2168 u8 bit; 2169 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2170 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2171 2172 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2173 pin_num, strength); 2174 2175 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2176 2177 ret = -EINVAL; 2178 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2179 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2180 ret = i; 2181 break; 2182 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2183 ret = rockchip_perpin_drv_list[drv_type][i]; 2184 break; 2185 } 2186 } 2187 2188 if (ret < 0) { 2189 debug("unsupported driver strength %d\n", strength); 2190 return ret; 2191 } 2192 2193 switch (drv_type) { 2194 case DRV_TYPE_IO_1V8_3V0_AUTO: 2195 case DRV_TYPE_IO_3V3_ONLY: 2196 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2197 switch (bit) { 2198 case 0 ... 12: 2199 /* regular case, nothing to do */ 2200 break; 2201 case 15: 2202 /* 2203 * drive-strength offset is special, as it is spread 2204 * over 2 registers, the bit data[15] contains bit 0 2205 * of the value while temp[1:0] contains bits 2 and 1 2206 */ 2207 data = (ret & 0x1) << 15; 2208 temp = (ret >> 0x1) & 0x3; 2209 2210 data |= BIT(31); 2211 ret = regmap_write(regmap, reg, data); 2212 if (ret) 2213 return ret; 2214 2215 temp |= (0x3 << 16); 2216 reg += 0x4; 2217 ret = regmap_write(regmap, reg, temp); 2218 2219 return ret; 2220 case 18 ... 21: 2221 /* setting fully enclosed in the second register */ 2222 reg += 4; 2223 bit -= 16; 2224 break; 2225 default: 2226 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2227 bit, drv_type); 2228 return -EINVAL; 2229 } 2230 break; 2231 case DRV_TYPE_IO_DEFAULT: 2232 case DRV_TYPE_IO_1V8_OR_3V0: 2233 case DRV_TYPE_IO_1V8_ONLY: 2234 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2235 break; 2236 default: 2237 debug("unsupported pinctrl drive type: %d\n", 2238 drv_type); 2239 return -EINVAL; 2240 } 2241 2242 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2243 regmap_read(regmap, reg, &data); 2244 data &= ~(((1 << rmask_bits) - 1) << bit); 2245 } else { 2246 /* enable the write to the equivalent lower bits */ 2247 data = ((1 << rmask_bits) - 1) << (bit + 16); 2248 } 2249 2250 data |= (ret << bit); 2251 ret = regmap_write(regmap, reg, data); 2252 return ret; 2253 } 2254 2255 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2256 { 2257 PIN_CONFIG_BIAS_DISABLE, 2258 PIN_CONFIG_BIAS_PULL_UP, 2259 PIN_CONFIG_BIAS_PULL_DOWN, 2260 PIN_CONFIG_BIAS_BUS_HOLD 2261 }, 2262 { 2263 PIN_CONFIG_BIAS_DISABLE, 2264 PIN_CONFIG_BIAS_PULL_DOWN, 2265 PIN_CONFIG_BIAS_DISABLE, 2266 PIN_CONFIG_BIAS_PULL_UP 2267 }, 2268 }; 2269 2270 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2271 int pin_num, int pull) 2272 { 2273 struct rockchip_pinctrl_priv *priv = bank->priv; 2274 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2275 struct regmap *regmap; 2276 int reg, ret, i, pull_type; 2277 u8 bit; 2278 u32 data; 2279 2280 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2281 pin_num, pull); 2282 2283 /* rk3066b does support any pulls */ 2284 if (ctrl->type == RK3066B) 2285 return pull ? -EINVAL : 0; 2286 2287 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2288 2289 switch (ctrl->type) { 2290 case RK2928: 2291 case RK3128: 2292 data = BIT(bit + 16); 2293 if (pull == PIN_CONFIG_BIAS_DISABLE) 2294 data |= BIT(bit); 2295 ret = regmap_write(regmap, reg, data); 2296 break; 2297 case PX30: 2298 case RV1108: 2299 case RK1808: 2300 case RK3188: 2301 case RK3288: 2302 case RK3308: 2303 case RK3368: 2304 case RK3399: 2305 /* 2306 * Where need to clean the special mask for 2307 * rockchip_pull_list. 2308 */ 2309 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2310 ret = -EINVAL; 2311 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2312 i++) { 2313 if (rockchip_pull_list[pull_type][i] == pull) { 2314 ret = i; 2315 break; 2316 } 2317 } 2318 2319 if (ret < 0) { 2320 debug("unsupported pull setting %d\n", pull); 2321 return ret; 2322 } 2323 2324 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2325 regmap_read(regmap, reg, &data); 2326 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2327 } else { 2328 /* enable the write to the equivalent lower bits */ 2329 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2330 } 2331 2332 data |= (ret << bit); 2333 ret = regmap_write(regmap, reg, data); 2334 break; 2335 default: 2336 debug("unsupported pinctrl type\n"); 2337 return -EINVAL; 2338 } 2339 2340 return ret; 2341 } 2342 2343 #define RK3328_SCHMITT_BITS_PER_PIN 1 2344 #define RK3328_SCHMITT_PINS_PER_REG 16 2345 #define RK3328_SCHMITT_BANK_STRIDE 8 2346 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2347 2348 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2349 int pin_num, 2350 struct regmap **regmap, 2351 int *reg, u8 *bit) 2352 { 2353 struct rockchip_pinctrl_priv *priv = bank->priv; 2354 2355 *regmap = priv->regmap_base; 2356 *reg = RK3328_SCHMITT_GRF_OFFSET; 2357 2358 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2359 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2360 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2361 2362 return 0; 2363 } 2364 2365 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2366 int pin_num, int enable) 2367 { 2368 struct rockchip_pinctrl_priv *priv = bank->priv; 2369 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2370 struct regmap *regmap; 2371 int reg, ret; 2372 u8 bit; 2373 u32 data; 2374 2375 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2376 pin_num, enable); 2377 2378 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2379 if (ret) 2380 return ret; 2381 2382 /* enable the write to the equivalent lower bits */ 2383 data = BIT(bit + 16) | (enable << bit); 2384 2385 return regmap_write(regmap, reg, data); 2386 } 2387 2388 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2389 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2390 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2391 #define PX30_SLEW_RATE_BANK_STRIDE 16 2392 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2393 2394 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2395 int pin_num, 2396 struct regmap **regmap, 2397 int *reg, u8 *bit) 2398 { 2399 struct rockchip_pinctrl_priv *priv = bank->priv; 2400 int pins_per_reg; 2401 2402 if (bank->bank_num == 0) { 2403 *regmap = priv->regmap_pmu; 2404 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2405 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2406 } else { 2407 *regmap = priv->regmap_base; 2408 *reg = PX30_SCHMITT_GRF_OFFSET; 2409 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2410 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2411 } 2412 *reg += ((pin_num / pins_per_reg) * 4); 2413 *bit = pin_num % pins_per_reg; 2414 2415 return 0; 2416 } 2417 2418 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2419 int pin_num, int speed) 2420 { 2421 struct rockchip_pinctrl_priv *priv = bank->priv; 2422 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2423 struct regmap *regmap; 2424 int reg, ret; 2425 u8 bit; 2426 u32 data; 2427 2428 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2429 pin_num, speed); 2430 2431 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2432 if (ret) 2433 return ret; 2434 2435 /* enable the write to the equivalent lower bits */ 2436 data = BIT(bit + 16) | (speed << bit); 2437 2438 return regmap_write(regmap, reg, data); 2439 } 2440 2441 /* 2442 * Pinconf_ops handling 2443 */ 2444 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2445 unsigned int pull) 2446 { 2447 switch (ctrl->type) { 2448 case RK2928: 2449 case RK3128: 2450 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2451 pull == PIN_CONFIG_BIAS_DISABLE); 2452 case RK3066B: 2453 return pull ? false : true; 2454 case PX30: 2455 case RV1108: 2456 case RK1808: 2457 case RK3188: 2458 case RK3288: 2459 case RK3308: 2460 case RK3368: 2461 case RK3399: 2462 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2463 } 2464 2465 return false; 2466 } 2467 2468 /* set the pin config settings for a specified pin */ 2469 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2470 u32 pin, u32 param, u32 arg) 2471 { 2472 struct rockchip_pinctrl_priv *priv = bank->priv; 2473 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2474 int rc; 2475 2476 switch (param) { 2477 case PIN_CONFIG_BIAS_DISABLE: 2478 rc = rockchip_set_pull(bank, pin, param); 2479 if (rc) 2480 return rc; 2481 break; 2482 2483 case PIN_CONFIG_BIAS_PULL_UP: 2484 case PIN_CONFIG_BIAS_PULL_DOWN: 2485 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2486 case PIN_CONFIG_BIAS_BUS_HOLD: 2487 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2488 return -ENOTSUPP; 2489 2490 if (!arg) 2491 return -EINVAL; 2492 2493 rc = rockchip_set_pull(bank, pin, param); 2494 if (rc) 2495 return rc; 2496 break; 2497 2498 case PIN_CONFIG_DRIVE_STRENGTH: 2499 if (!ctrl->drv_calc_reg) 2500 return -ENOTSUPP; 2501 2502 rc = rockchip_set_drive_perpin(bank, pin, arg); 2503 if (rc < 0) 2504 return rc; 2505 break; 2506 2507 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2508 if (!ctrl->schmitt_calc_reg) 2509 return -ENOTSUPP; 2510 2511 rc = rockchip_set_schmitt(bank, pin, arg); 2512 if (rc < 0) 2513 return rc; 2514 break; 2515 2516 case PIN_CONFIG_SLEW_RATE: 2517 if (!ctrl->slew_rate_calc_reg) 2518 return -ENOTSUPP; 2519 2520 rc = rockchip_set_slew_rate(bank, 2521 pin - bank->pin_base, arg); 2522 if (rc < 0) 2523 return rc; 2524 break; 2525 2526 default: 2527 break; 2528 } 2529 2530 return 0; 2531 } 2532 2533 static const struct pinconf_param rockchip_conf_params[] = { 2534 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2535 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2536 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2537 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2538 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2539 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2540 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2541 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2542 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2543 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2544 }; 2545 2546 static int rockchip_pinconf_prop_name_to_param(const char *property, 2547 u32 *default_value) 2548 { 2549 const struct pinconf_param *p, *end; 2550 2551 p = rockchip_conf_params; 2552 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2553 2554 /* See if this pctldev supports this parameter */ 2555 for (; p < end; p++) { 2556 if (!strcmp(property, p->property)) { 2557 *default_value = p->default_value; 2558 return p->param; 2559 } 2560 } 2561 2562 *default_value = 0; 2563 return -EPERM; 2564 } 2565 2566 static int rockchip_pinctrl_set_state(struct udevice *dev, 2567 struct udevice *config) 2568 { 2569 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2570 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2571 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2572 u32 bank, pin, mux, conf, arg, default_val; 2573 int ret, count, i; 2574 const char *prop_name; 2575 const void *value; 2576 int prop_len, param; 2577 const u32 *data; 2578 ofnode node; 2579 #ifdef CONFIG_OF_LIVE 2580 const struct device_node *np; 2581 struct property *pp; 2582 #else 2583 int property_offset, pcfg_node; 2584 const void *blob = gd->fdt_blob; 2585 #endif 2586 data = dev_read_prop(config, "rockchip,pins", &count); 2587 if (count < 0) { 2588 debug("%s: bad array size %d\n", __func__, count); 2589 return -EINVAL; 2590 } 2591 2592 count /= sizeof(u32); 2593 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2594 debug("%s: unsupported pins array count %d\n", 2595 __func__, count); 2596 return -EINVAL; 2597 } 2598 2599 for (i = 0; i < count; i++) 2600 cells[i] = fdt32_to_cpu(data[i]); 2601 2602 for (i = 0; i < (count >> 2); i++) { 2603 bank = cells[4 * i + 0]; 2604 pin = cells[4 * i + 1]; 2605 mux = cells[4 * i + 2]; 2606 conf = cells[4 * i + 3]; 2607 2608 ret = rockchip_verify_config(dev, bank, pin); 2609 if (ret) 2610 return ret; 2611 2612 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2613 if (ret) 2614 return ret; 2615 2616 node = ofnode_get_by_phandle(conf); 2617 if (!ofnode_valid(node)) 2618 return -ENODEV; 2619 #ifdef CONFIG_OF_LIVE 2620 np = ofnode_to_np(node); 2621 for (pp = np->properties; pp; pp = pp->next) { 2622 prop_name = pp->name; 2623 prop_len = pp->length; 2624 value = pp->value; 2625 #else 2626 pcfg_node = ofnode_to_offset(node); 2627 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2628 value = fdt_getprop_by_offset(blob, property_offset, 2629 &prop_name, &prop_len); 2630 if (!value) 2631 return -ENOENT; 2632 #endif 2633 param = rockchip_pinconf_prop_name_to_param(prop_name, 2634 &default_val); 2635 if (param < 0) 2636 break; 2637 2638 if (prop_len >= sizeof(fdt32_t)) 2639 arg = fdt32_to_cpu(*(fdt32_t *)value); 2640 else 2641 arg = default_val; 2642 2643 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2644 param, arg); 2645 if (ret) { 2646 debug("%s: rockchip_pinconf_set fail: %d\n", 2647 __func__, ret); 2648 return ret; 2649 } 2650 } 2651 } 2652 2653 return 0; 2654 } 2655 2656 static struct pinctrl_ops rockchip_pinctrl_ops = { 2657 .set_state = rockchip_pinctrl_set_state, 2658 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2659 }; 2660 2661 /* Ctrl data specially handle */ 2662 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2663 { 2664 /* 2665 * Special for rk3308b, where we need to replace the recalced 2666 * and routed arrays. 2667 */ 2668 if (soc_is_rk3308b()) { 2669 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2670 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2671 ctrl->iomux_routes = rk3308b_mux_route_data; 2672 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2673 } 2674 2675 return 0; 2676 } 2677 2678 /* retrieve the soc specific data */ 2679 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2680 { 2681 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2682 struct rockchip_pin_ctrl *ctrl = 2683 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2684 struct rockchip_pin_bank *bank; 2685 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2686 2687 grf_offs = ctrl->grf_mux_offset; 2688 pmu_offs = ctrl->pmu_mux_offset; 2689 drv_pmu_offs = ctrl->pmu_drv_offset; 2690 drv_grf_offs = ctrl->grf_drv_offset; 2691 bank = ctrl->pin_banks; 2692 2693 /* Ctrl data re-initialize for some Socs */ 2694 if (ctrl->ctrl_data_re_init) { 2695 if (ctrl->ctrl_data_re_init(ctrl)) 2696 return NULL; 2697 } 2698 2699 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2700 int bank_pins = 0; 2701 2702 bank->priv = priv; 2703 bank->pin_base = ctrl->nr_pins; 2704 ctrl->nr_pins += bank->nr_pins; 2705 2706 /* calculate iomux and drv offsets */ 2707 for (j = 0; j < 4; j++) { 2708 struct rockchip_iomux *iom = &bank->iomux[j]; 2709 struct rockchip_drv *drv = &bank->drv[j]; 2710 int inc; 2711 2712 if (bank_pins >= bank->nr_pins) 2713 break; 2714 2715 /* preset iomux offset value, set new start value */ 2716 if (iom->offset >= 0) { 2717 if (iom->type & IOMUX_SOURCE_PMU) 2718 pmu_offs = iom->offset; 2719 else 2720 grf_offs = iom->offset; 2721 } else { /* set current iomux offset */ 2722 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2723 pmu_offs : grf_offs; 2724 } 2725 2726 /* preset drv offset value, set new start value */ 2727 if (drv->offset >= 0) { 2728 if (iom->type & IOMUX_SOURCE_PMU) 2729 drv_pmu_offs = drv->offset; 2730 else 2731 drv_grf_offs = drv->offset; 2732 } else { /* set current drv offset */ 2733 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2734 drv_pmu_offs : drv_grf_offs; 2735 } 2736 2737 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2738 i, j, iom->offset, drv->offset); 2739 2740 /* 2741 * Increase offset according to iomux width. 2742 * 4bit iomux'es are spread over two registers. 2743 */ 2744 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2745 IOMUX_WIDTH_3BIT | 2746 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2747 if (iom->type & IOMUX_SOURCE_PMU) 2748 pmu_offs += inc; 2749 else 2750 grf_offs += inc; 2751 2752 /* 2753 * Increase offset according to drv width. 2754 * 3bit drive-strenth'es are spread over two registers. 2755 */ 2756 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2757 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2758 inc = 8; 2759 else 2760 inc = 4; 2761 2762 if (iom->type & IOMUX_SOURCE_PMU) 2763 drv_pmu_offs += inc; 2764 else 2765 drv_grf_offs += inc; 2766 2767 bank_pins += 8; 2768 } 2769 2770 /* calculate the per-bank recalced_mask */ 2771 for (j = 0; j < ctrl->niomux_recalced; j++) { 2772 int pin = 0; 2773 2774 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2775 pin = ctrl->iomux_recalced[j].pin; 2776 bank->recalced_mask |= BIT(pin); 2777 } 2778 } 2779 2780 /* calculate the per-bank route_mask */ 2781 for (j = 0; j < ctrl->niomux_routes; j++) { 2782 int pin = 0; 2783 2784 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2785 pin = ctrl->iomux_routes[j].pin; 2786 bank->route_mask |= BIT(pin); 2787 } 2788 } 2789 } 2790 2791 return ctrl; 2792 } 2793 2794 /* SoC data specially handle */ 2795 2796 /* rk3308b SoC data initialize */ 2797 #define RK3308B_GRF_SOC_CON13 0x608 2798 #define RK3308B_GRF_SOC_CON15 0x610 2799 2800 /* RK3308B_GRF_SOC_CON13 */ 2801 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 2802 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2803 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2804 2805 /* RK3308B_GRF_SOC_CON15 */ 2806 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 2807 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2808 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2809 2810 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 2811 { 2812 int ret; 2813 2814 /* 2815 * Enable the special ctrl of selected sources. 2816 */ 2817 if (soc_is_rk3308b()) { 2818 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 2819 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 2820 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 2821 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 2822 if (ret) 2823 return ret; 2824 2825 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 2826 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 2827 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 2828 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 2829 if (ret) 2830 return ret; 2831 } 2832 2833 return 0; 2834 } 2835 2836 static int rockchip_pinctrl_probe(struct udevice *dev) 2837 { 2838 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2839 struct rockchip_pin_ctrl *ctrl; 2840 struct udevice *syscon; 2841 struct regmap *regmap; 2842 int ret = 0; 2843 2844 /* get rockchip grf syscon phandle */ 2845 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2846 &syscon); 2847 if (ret) { 2848 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2849 return ret; 2850 } 2851 2852 /* get grf-reg base address */ 2853 regmap = syscon_get_regmap(syscon); 2854 if (!regmap) { 2855 debug("unable to find rockchip grf regmap\n"); 2856 return -ENODEV; 2857 } 2858 priv->regmap_base = regmap; 2859 2860 /* option: get pmu-reg base address */ 2861 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2862 &syscon); 2863 if (!ret) { 2864 /* get pmugrf-reg base address */ 2865 regmap = syscon_get_regmap(syscon); 2866 if (!regmap) { 2867 debug("unable to find rockchip pmu regmap\n"); 2868 return -ENODEV; 2869 } 2870 priv->regmap_pmu = regmap; 2871 } 2872 2873 ctrl = rockchip_pinctrl_get_soc_data(dev); 2874 if (!ctrl) { 2875 debug("driver data not available\n"); 2876 return -EINVAL; 2877 } 2878 2879 /* Special handle for some Socs */ 2880 if (ctrl->soc_data_init) { 2881 ret = ctrl->soc_data_init(priv); 2882 if (ret) 2883 return ret; 2884 } 2885 2886 priv->ctrl = ctrl; 2887 return 0; 2888 } 2889 2890 static struct rockchip_pin_bank px30_pin_banks[] = { 2891 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2892 IOMUX_SOURCE_PMU, 2893 IOMUX_SOURCE_PMU, 2894 IOMUX_SOURCE_PMU 2895 ), 2896 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2897 IOMUX_WIDTH_4BIT, 2898 IOMUX_WIDTH_4BIT, 2899 IOMUX_WIDTH_4BIT 2900 ), 2901 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2902 IOMUX_WIDTH_4BIT, 2903 IOMUX_WIDTH_4BIT, 2904 IOMUX_WIDTH_4BIT 2905 ), 2906 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2907 IOMUX_WIDTH_4BIT, 2908 IOMUX_WIDTH_4BIT, 2909 IOMUX_WIDTH_4BIT 2910 ), 2911 }; 2912 2913 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2914 .pin_banks = px30_pin_banks, 2915 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2916 .label = "PX30-GPIO", 2917 .type = PX30, 2918 .grf_mux_offset = 0x0, 2919 .pmu_mux_offset = 0x0, 2920 .iomux_routes = px30_mux_route_data, 2921 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2922 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2923 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2924 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2925 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 2926 }; 2927 2928 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2929 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2930 IOMUX_SOURCE_PMU, 2931 IOMUX_SOURCE_PMU, 2932 IOMUX_SOURCE_PMU), 2933 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2934 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2935 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2936 }; 2937 2938 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2939 .pin_banks = rv1108_pin_banks, 2940 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2941 .label = "RV1108-GPIO", 2942 .type = RV1108, 2943 .grf_mux_offset = 0x10, 2944 .pmu_mux_offset = 0x0, 2945 .iomux_recalced = rv1108_mux_recalced_data, 2946 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2947 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2948 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2949 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2950 }; 2951 2952 static struct rockchip_pin_bank rk1808_pin_banks[] = { 2953 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 2954 IOMUX_SOURCE_PMU, 2955 IOMUX_SOURCE_PMU, 2956 IOMUX_SOURCE_PMU, 2957 IOMUX_SOURCE_PMU), 2958 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 2959 IOMUX_WIDTH_4BIT, 2960 IOMUX_WIDTH_4BIT, 2961 IOMUX_WIDTH_4BIT, 2962 IOMUX_WIDTH_4BIT), 2963 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 2964 IOMUX_WIDTH_4BIT, 2965 IOMUX_WIDTH_4BIT, 2966 IOMUX_WIDTH_4BIT, 2967 IOMUX_WIDTH_4BIT), 2968 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2969 IOMUX_WIDTH_4BIT, 2970 IOMUX_WIDTH_4BIT, 2971 IOMUX_WIDTH_4BIT, 2972 IOMUX_WIDTH_4BIT), 2973 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 2974 IOMUX_WIDTH_4BIT, 2975 IOMUX_WIDTH_4BIT, 2976 IOMUX_WIDTH_4BIT, 2977 IOMUX_WIDTH_4BIT), 2978 }; 2979 2980 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 2981 .pin_banks = rk1808_pin_banks, 2982 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 2983 .label = "RK1808-GPIO", 2984 .type = RK1808, 2985 .iomux_routes = rk1808_mux_route_data, 2986 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 2987 .grf_mux_offset = 0x0, 2988 .pmu_mux_offset = 0x0, 2989 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 2990 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 2991 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 2992 }; 2993 2994 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2995 PIN_BANK(0, 32, "gpio0"), 2996 PIN_BANK(1, 32, "gpio1"), 2997 PIN_BANK(2, 32, "gpio2"), 2998 PIN_BANK(3, 32, "gpio3"), 2999 }; 3000 3001 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3002 .pin_banks = rk2928_pin_banks, 3003 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3004 .label = "RK2928-GPIO", 3005 .type = RK2928, 3006 .grf_mux_offset = 0xa8, 3007 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3008 }; 3009 3010 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3011 PIN_BANK(0, 32, "gpio0"), 3012 PIN_BANK(1, 32, "gpio1"), 3013 PIN_BANK(2, 32, "gpio2"), 3014 }; 3015 3016 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3017 .pin_banks = rk3036_pin_banks, 3018 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3019 .label = "RK3036-GPIO", 3020 .type = RK2928, 3021 .grf_mux_offset = 0xa8, 3022 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3023 }; 3024 3025 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3026 PIN_BANK(0, 32, "gpio0"), 3027 PIN_BANK(1, 32, "gpio1"), 3028 PIN_BANK(2, 32, "gpio2"), 3029 PIN_BANK(3, 32, "gpio3"), 3030 PIN_BANK(4, 32, "gpio4"), 3031 PIN_BANK(6, 16, "gpio6"), 3032 }; 3033 3034 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3035 .pin_banks = rk3066a_pin_banks, 3036 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3037 .label = "RK3066a-GPIO", 3038 .type = RK2928, 3039 .grf_mux_offset = 0xa8, 3040 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3041 }; 3042 3043 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3044 PIN_BANK(0, 32, "gpio0"), 3045 PIN_BANK(1, 32, "gpio1"), 3046 PIN_BANK(2, 32, "gpio2"), 3047 PIN_BANK(3, 32, "gpio3"), 3048 }; 3049 3050 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3051 .pin_banks = rk3066b_pin_banks, 3052 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3053 .label = "RK3066b-GPIO", 3054 .type = RK3066B, 3055 .grf_mux_offset = 0x60, 3056 }; 3057 3058 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3059 PIN_BANK(0, 32, "gpio0"), 3060 PIN_BANK(1, 32, "gpio1"), 3061 PIN_BANK(2, 32, "gpio2"), 3062 PIN_BANK(3, 32, "gpio3"), 3063 }; 3064 3065 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3066 .pin_banks = rk3128_pin_banks, 3067 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3068 .label = "RK3128-GPIO", 3069 .type = RK3128, 3070 .grf_mux_offset = 0xa8, 3071 .iomux_recalced = rk3128_mux_recalced_data, 3072 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3073 .iomux_routes = rk3128_mux_route_data, 3074 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3075 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3076 }; 3077 3078 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3079 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3080 PIN_BANK(1, 32, "gpio1"), 3081 PIN_BANK(2, 32, "gpio2"), 3082 PIN_BANK(3, 32, "gpio3"), 3083 }; 3084 3085 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3086 .pin_banks = rk3188_pin_banks, 3087 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3088 .label = "RK3188-GPIO", 3089 .type = RK3188, 3090 .grf_mux_offset = 0x60, 3091 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3092 }; 3093 3094 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3095 PIN_BANK(0, 32, "gpio0"), 3096 PIN_BANK(1, 32, "gpio1"), 3097 PIN_BANK(2, 32, "gpio2"), 3098 PIN_BANK(3, 32, "gpio3"), 3099 }; 3100 3101 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3102 .pin_banks = rk3228_pin_banks, 3103 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3104 .label = "RK3228-GPIO", 3105 .type = RK3288, 3106 .grf_mux_offset = 0x0, 3107 .iomux_routes = rk3228_mux_route_data, 3108 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3109 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3110 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3111 }; 3112 3113 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3114 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3115 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3116 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3117 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3118 IOMUX_UNROUTED, 3119 DRV_TYPE_WRITABLE_32BIT, 3120 DRV_TYPE_WRITABLE_32BIT, 3121 DRV_TYPE_WRITABLE_32BIT, 3122 0, 3123 PULL_TYPE_WRITABLE_32BIT, 3124 PULL_TYPE_WRITABLE_32BIT, 3125 PULL_TYPE_WRITABLE_32BIT, 3126 0 3127 ), 3128 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3129 IOMUX_UNROUTED, 3130 IOMUX_UNROUTED, 3131 0 3132 ), 3133 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3134 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3135 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3136 IOMUX_WIDTH_4BIT, 3137 0, 3138 0 3139 ), 3140 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3141 0, 3142 0, 3143 IOMUX_UNROUTED 3144 ), 3145 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3146 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3147 0, 3148 IOMUX_WIDTH_4BIT, 3149 IOMUX_UNROUTED 3150 ), 3151 PIN_BANK(8, 16, "gpio8"), 3152 }; 3153 3154 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3155 .pin_banks = rk3288_pin_banks, 3156 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3157 .label = "RK3288-GPIO", 3158 .type = RK3288, 3159 .grf_mux_offset = 0x0, 3160 .pmu_mux_offset = 0x84, 3161 .iomux_routes = rk3288_mux_route_data, 3162 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3163 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3164 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3165 }; 3166 3167 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3168 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3169 IOMUX_8WIDTH_2BIT, 3170 IOMUX_8WIDTH_2BIT, 3171 IOMUX_8WIDTH_2BIT), 3172 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3173 IOMUX_8WIDTH_2BIT, 3174 IOMUX_8WIDTH_2BIT, 3175 IOMUX_8WIDTH_2BIT), 3176 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3177 IOMUX_8WIDTH_2BIT, 3178 IOMUX_8WIDTH_2BIT, 3179 IOMUX_8WIDTH_2BIT), 3180 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3181 IOMUX_8WIDTH_2BIT, 3182 IOMUX_8WIDTH_2BIT, 3183 IOMUX_8WIDTH_2BIT), 3184 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3185 IOMUX_8WIDTH_2BIT, 3186 IOMUX_8WIDTH_2BIT, 3187 IOMUX_8WIDTH_2BIT), 3188 }; 3189 3190 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3191 .pin_banks = rk3308_pin_banks, 3192 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3193 .label = "RK3308-GPIO", 3194 .type = RK3308, 3195 .grf_mux_offset = 0x0, 3196 .iomux_recalced = rk3308_mux_recalced_data, 3197 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3198 .iomux_routes = rk3308_mux_route_data, 3199 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3200 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3201 .soc_data_init = rk3308b_soc_data_init, 3202 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3203 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3204 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3205 }; 3206 3207 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3208 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3209 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3210 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3211 IOMUX_WIDTH_3BIT, 3212 IOMUX_WIDTH_3BIT, 3213 0), 3214 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3215 IOMUX_WIDTH_3BIT, 3216 IOMUX_WIDTH_3BIT, 3217 0, 3218 0), 3219 }; 3220 3221 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3222 .pin_banks = rk3328_pin_banks, 3223 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3224 .label = "RK3328-GPIO", 3225 .type = RK3288, 3226 .grf_mux_offset = 0x0, 3227 .iomux_recalced = rk3328_mux_recalced_data, 3228 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3229 .iomux_routes = rk3328_mux_route_data, 3230 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3231 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3232 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3233 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3234 }; 3235 3236 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3237 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3238 IOMUX_SOURCE_PMU, 3239 IOMUX_SOURCE_PMU, 3240 IOMUX_SOURCE_PMU 3241 ), 3242 PIN_BANK(1, 32, "gpio1"), 3243 PIN_BANK(2, 32, "gpio2"), 3244 PIN_BANK(3, 32, "gpio3"), 3245 }; 3246 3247 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3248 .pin_banks = rk3368_pin_banks, 3249 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3250 .label = "RK3368-GPIO", 3251 .type = RK3368, 3252 .grf_mux_offset = 0x0, 3253 .pmu_mux_offset = 0x0, 3254 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3255 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3256 }; 3257 3258 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3259 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3260 IOMUX_SOURCE_PMU, 3261 IOMUX_SOURCE_PMU, 3262 IOMUX_SOURCE_PMU, 3263 IOMUX_SOURCE_PMU, 3264 DRV_TYPE_IO_1V8_ONLY, 3265 DRV_TYPE_IO_1V8_ONLY, 3266 DRV_TYPE_IO_DEFAULT, 3267 DRV_TYPE_IO_DEFAULT, 3268 0x80, 3269 0x88, 3270 -1, 3271 -1, 3272 PULL_TYPE_IO_1V8_ONLY, 3273 PULL_TYPE_IO_1V8_ONLY, 3274 PULL_TYPE_IO_DEFAULT, 3275 PULL_TYPE_IO_DEFAULT 3276 ), 3277 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3278 IOMUX_SOURCE_PMU, 3279 IOMUX_SOURCE_PMU, 3280 IOMUX_SOURCE_PMU, 3281 DRV_TYPE_IO_1V8_OR_3V0, 3282 DRV_TYPE_IO_1V8_OR_3V0, 3283 DRV_TYPE_IO_1V8_OR_3V0, 3284 DRV_TYPE_IO_1V8_OR_3V0, 3285 0xa0, 3286 0xa8, 3287 0xb0, 3288 0xb8 3289 ), 3290 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3291 DRV_TYPE_IO_1V8_OR_3V0, 3292 DRV_TYPE_IO_1V8_ONLY, 3293 DRV_TYPE_IO_1V8_ONLY, 3294 PULL_TYPE_IO_DEFAULT, 3295 PULL_TYPE_IO_DEFAULT, 3296 PULL_TYPE_IO_1V8_ONLY, 3297 PULL_TYPE_IO_1V8_ONLY 3298 ), 3299 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3300 DRV_TYPE_IO_3V3_ONLY, 3301 DRV_TYPE_IO_3V3_ONLY, 3302 DRV_TYPE_IO_1V8_OR_3V0 3303 ), 3304 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3305 DRV_TYPE_IO_1V8_3V0_AUTO, 3306 DRV_TYPE_IO_1V8_OR_3V0, 3307 DRV_TYPE_IO_1V8_OR_3V0 3308 ), 3309 }; 3310 3311 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3312 .pin_banks = rk3399_pin_banks, 3313 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3314 .label = "RK3399-GPIO", 3315 .type = RK3399, 3316 .grf_mux_offset = 0xe000, 3317 .pmu_mux_offset = 0x0, 3318 .grf_drv_offset = 0xe100, 3319 .pmu_drv_offset = 0x80, 3320 .iomux_routes = rk3399_mux_route_data, 3321 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3322 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3323 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3324 }; 3325 3326 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3327 { .compatible = "rockchip,px30-pinctrl", 3328 .data = (ulong)&px30_pin_ctrl }, 3329 { .compatible = "rockchip,rv1108-pinctrl", 3330 .data = (ulong)&rv1108_pin_ctrl }, 3331 { .compatible = "rockchip,rk1808-pinctrl", 3332 .data = (ulong)&rk1808_pin_ctrl }, 3333 { .compatible = "rockchip,rk2928-pinctrl", 3334 .data = (ulong)&rk2928_pin_ctrl }, 3335 { .compatible = "rockchip,rk3036-pinctrl", 3336 .data = (ulong)&rk3036_pin_ctrl }, 3337 { .compatible = "rockchip,rk3066a-pinctrl", 3338 .data = (ulong)&rk3066a_pin_ctrl }, 3339 { .compatible = "rockchip,rk3066b-pinctrl", 3340 .data = (ulong)&rk3066b_pin_ctrl }, 3341 { .compatible = "rockchip,rk3128-pinctrl", 3342 .data = (ulong)&rk3128_pin_ctrl }, 3343 { .compatible = "rockchip,rk3188-pinctrl", 3344 .data = (ulong)&rk3188_pin_ctrl }, 3345 { .compatible = "rockchip,rk3228-pinctrl", 3346 .data = (ulong)&rk3228_pin_ctrl }, 3347 { .compatible = "rockchip,rk3288-pinctrl", 3348 .data = (ulong)&rk3288_pin_ctrl }, 3349 { .compatible = "rockchip,rk3308-pinctrl", 3350 .data = (ulong)&rk3308_pin_ctrl }, 3351 { .compatible = "rockchip,rk3328-pinctrl", 3352 .data = (ulong)&rk3328_pin_ctrl }, 3353 { .compatible = "rockchip,rk3368-pinctrl", 3354 .data = (ulong)&rk3368_pin_ctrl }, 3355 { .compatible = "rockchip,rk3399-pinctrl", 3356 .data = (ulong)&rk3399_pin_ctrl }, 3357 {}, 3358 }; 3359 3360 U_BOOT_DRIVER(pinctrl_rockchip) = { 3361 .name = "rockchip_pinctrl", 3362 .id = UCLASS_PINCTRL, 3363 .of_match = rockchip_pinctrl_dt_match, 3364 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3365 .ops = &rockchip_pinctrl_ops, 3366 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3367 .bind = dm_scan_fdt_dev, 3368 #endif 3369 .probe = rockchip_pinctrl_probe, 3370 }; 3371