1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/gpio.h> 11 #include <asm/arch-rockchip/clock.h> 12 #include <asm/arch/vendor.h> 13 #include <edid.h> 14 #include <dm/device.h> 15 #include <dm/of_access.h> 16 #include <dm/ofnode.h> 17 #include <dm/read.h> 18 #include <linux/hdmi.h> 19 #include <linux/media-bus-format.h> 20 #include <linux/dw_hdmi.h> 21 #include <asm/io.h> 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "dw_hdmi.h" 26 #include "rockchip_phy.h" 27 28 #define HDCP_PRIVATE_KEY_SIZE 280 29 #define HDCP_KEY_SHA_SIZE 20 30 #define HDMI_HDCP1X_ID 5 31 /* 32 * Unless otherwise noted, entries in this table are 100% optimization. 33 * Values can be obtained from hdmi_compute_n() but that function is 34 * slow so we pre-compute values we expect to see. 35 * 36 * All 32k and 48k values are expected to be the same (due to the way 37 * the math works) for any rate that's an exact kHz. 38 */ 39 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 40 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 41 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 42 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 43 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 44 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 45 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 46 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 47 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 48 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 49 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 50 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 51 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 52 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 53 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 54 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 55 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 56 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 57 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 58 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 59 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 60 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 61 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 62 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 63 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 64 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 65 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 66 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 67 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 68 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 69 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 70 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 71 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 72 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 73 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 74 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 75 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 76 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 77 78 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 79 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 80 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 81 82 /* End of table */ 83 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 84 }; 85 86 static const u16 csc_coeff_default[3][4] = { 87 { 0x2000, 0x0000, 0x0000, 0x0000 }, 88 { 0x0000, 0x2000, 0x0000, 0x0000 }, 89 { 0x0000, 0x0000, 0x2000, 0x0000 } 90 }; 91 92 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 93 { 0x2000, 0x6926, 0x74fd, 0x010e }, 94 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 95 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 96 }; 97 98 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 99 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 100 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 101 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 102 }; 103 104 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 105 { 0x2591, 0x1322, 0x074b, 0x0000 }, 106 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 107 { 0x6acd, 0x7534, 0x2000, 0x0200 } 108 }; 109 110 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 111 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 112 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 113 { 0x6756, 0x78ab, 0x2000, 0x0200 } 114 }; 115 116 static const u16 csc_coeff_full_to_limited[3][4] = { 117 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 118 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 119 { 0x0000, 0x0000, 0x36f7, 0x0040 } 120 }; 121 122 struct hdmi_vmode { 123 bool mdataenablepolarity; 124 125 unsigned int mpixelclock; 126 unsigned int mpixelrepetitioninput; 127 unsigned int mpixelrepetitionoutput; 128 unsigned int mtmdsclock; 129 }; 130 131 struct hdmi_data_info { 132 unsigned int enc_in_bus_format; 133 unsigned int enc_out_bus_format; 134 unsigned int enc_in_encoding; 135 unsigned int enc_out_encoding; 136 unsigned int quant_range; 137 unsigned int pix_repet_factor; 138 struct hdmi_vmode video_mode; 139 }; 140 141 struct dw_hdmi_phy_data { 142 enum dw_hdmi_phy_type type; 143 const char *name; 144 unsigned int gen; 145 bool has_svsret; 146 int (*configure)(struct dw_hdmi *hdmi, 147 const struct dw_hdmi_plat_data *pdata, 148 unsigned long mpixelclock); 149 }; 150 151 struct hdcp_keys { 152 u8 KSV[8]; 153 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 154 u8 sha1[HDCP_KEY_SHA_SIZE]; 155 u8 seeds[2]; 156 }; 157 158 struct dw_hdmi_i2c { 159 u8 slave_reg; 160 bool is_regaddr; 161 bool is_segment; 162 163 unsigned int scl_high_ns; 164 unsigned int scl_low_ns; 165 }; 166 167 struct dw_hdmi { 168 int id; 169 enum dw_hdmi_devtype dev_type; 170 unsigned int version; 171 struct hdmi_data_info hdmi_data; 172 struct hdmi_edid_data edid_data; 173 const struct dw_hdmi_plat_data *plat_data; 174 struct ddc_adapter adap; 175 176 int vic; 177 int io_width; 178 179 unsigned long bus_format; 180 bool cable_plugin; 181 bool sink_is_hdmi; 182 bool sink_has_audio; 183 void *regs; 184 void *grf; 185 void *gpio_base; 186 struct dw_hdmi_i2c *i2c; 187 188 struct { 189 const struct dw_hdmi_phy_ops *ops; 190 const char *name; 191 void *data; 192 bool enabled; 193 } phy; 194 195 struct drm_display_mode previous_mode; 196 197 unsigned int sample_rate; 198 unsigned int audio_cts; 199 unsigned int audio_n; 200 bool audio_enable; 201 bool scramble_low_rates; 202 203 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 204 u8 (*read)(struct dw_hdmi *hdmi, int offset); 205 206 bool hdcp1x_enable; 207 bool output_bus_format_rgb; 208 209 struct gpio_desc hpd_gpiod; 210 }; 211 212 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 213 { 214 writel(val, hdmi->regs + (offset << 2)); 215 } 216 217 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 218 { 219 return readl(hdmi->regs + (offset << 2)); 220 } 221 222 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 223 { 224 writeb(val, hdmi->regs + offset); 225 } 226 227 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 228 { 229 return readb(hdmi->regs + offset); 230 } 231 232 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 233 { 234 hdmi->write(hdmi, val, offset); 235 } 236 237 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 238 { 239 return hdmi->read(hdmi, offset); 240 } 241 242 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 243 { 244 u8 val = hdmi_readb(hdmi, reg) & ~mask; 245 246 val |= data & mask; 247 hdmi_writeb(hdmi, val, reg); 248 } 249 250 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 251 u8 shift, u8 mask) 252 { 253 hdmi_modb(hdmi, data << shift, mask, reg); 254 } 255 256 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 257 { 258 switch (bus_format) { 259 case MEDIA_BUS_FMT_RGB888_1X24: 260 case MEDIA_BUS_FMT_RGB101010_1X30: 261 case MEDIA_BUS_FMT_RGB121212_1X36: 262 case MEDIA_BUS_FMT_RGB161616_1X48: 263 return true; 264 265 default: 266 return false; 267 } 268 } 269 270 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 271 { 272 switch (bus_format) { 273 case MEDIA_BUS_FMT_YUV8_1X24: 274 case MEDIA_BUS_FMT_YUV10_1X30: 275 case MEDIA_BUS_FMT_YUV12_1X36: 276 case MEDIA_BUS_FMT_YUV16_1X48: 277 return true; 278 279 default: 280 return false; 281 } 282 } 283 284 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 285 { 286 switch (bus_format) { 287 case MEDIA_BUS_FMT_UYVY8_1X16: 288 case MEDIA_BUS_FMT_UYVY10_1X20: 289 case MEDIA_BUS_FMT_UYVY12_1X24: 290 return true; 291 292 default: 293 return false; 294 } 295 } 296 297 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 298 { 299 switch (bus_format) { 300 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 301 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 302 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 303 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 304 return true; 305 306 default: 307 return false; 308 } 309 } 310 311 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 312 { 313 switch (bus_format) { 314 case MEDIA_BUS_FMT_RGB888_1X24: 315 case MEDIA_BUS_FMT_YUV8_1X24: 316 case MEDIA_BUS_FMT_UYVY8_1X16: 317 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 318 return 8; 319 320 case MEDIA_BUS_FMT_RGB101010_1X30: 321 case MEDIA_BUS_FMT_YUV10_1X30: 322 case MEDIA_BUS_FMT_UYVY10_1X20: 323 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 324 return 10; 325 326 case MEDIA_BUS_FMT_RGB121212_1X36: 327 case MEDIA_BUS_FMT_YUV12_1X36: 328 case MEDIA_BUS_FMT_UYVY12_1X24: 329 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 330 return 12; 331 332 case MEDIA_BUS_FMT_RGB161616_1X48: 333 case MEDIA_BUS_FMT_YUV16_1X48: 334 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 335 return 16; 336 337 default: 338 return 0; 339 } 340 } 341 342 static int is_color_space_conversion(struct dw_hdmi *hdmi) 343 { 344 struct drm_display_mode *mode = 345 hdmi->edid_data.preferred_mode; 346 bool is_cea_default; 347 348 is_cea_default = (drm_match_cea_mode(mode) > 1) && 349 (hdmi->hdmi_data.quant_range == 350 HDMI_QUANTIZATION_RANGE_DEFAULT); 351 352 /* 353 * When output is rgb limited range or default range with 354 * cea mode, csc should be enabled. 355 */ 356 if (hdmi->hdmi_data.enc_in_bus_format != 357 hdmi->hdmi_data.enc_out_bus_format || 358 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 359 is_cea_default) && 360 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 361 return 1; 362 363 return 0; 364 } 365 366 static int is_color_space_decimation(struct dw_hdmi *hdmi) 367 { 368 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 369 return 0; 370 371 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 372 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 373 return 1; 374 375 return 0; 376 } 377 378 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 379 unsigned char bit) 380 { 381 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 382 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 383 } 384 385 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 386 unsigned char bit) 387 { 388 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 389 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 390 } 391 392 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 393 unsigned char bit) 394 { 395 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 396 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 397 } 398 399 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 400 unsigned char bit) 401 { 402 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 403 } 404 405 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 406 unsigned char bit) 407 { 408 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 409 } 410 411 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 412 unsigned char *buf, unsigned int length) 413 { 414 struct dw_hdmi_i2c *i2c = hdmi->i2c; 415 int interrupt = 0, i = 20; 416 417 if (!i2c->is_regaddr) { 418 printf("set read register address to 0\n"); 419 i2c->slave_reg = 0x00; 420 i2c->is_regaddr = true; 421 } 422 423 while (length--) { 424 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 425 if (i2c->is_segment) 426 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 427 HDMI_I2CM_OPERATION); 428 else 429 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 430 HDMI_I2CM_OPERATION); 431 432 while (i--) { 433 udelay(1000); 434 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 435 if (interrupt) 436 hdmi_writeb(hdmi, interrupt, 437 HDMI_IH_I2CM_STAT0); 438 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 439 m_I2CM_ERROR)) 440 break; 441 } 442 443 if (!interrupt) { 444 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 445 __func__, i2c->slave_reg); 446 return -EAGAIN; 447 } 448 449 /* Check for error condition on the bus */ 450 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 451 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 452 __func__, i2c->slave_reg, interrupt); 453 return -EIO; 454 } 455 456 i = 20; 457 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 458 } 459 i2c->is_segment = false; 460 461 return 0; 462 } 463 464 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 465 unsigned char *buf, unsigned int length) 466 { 467 struct dw_hdmi_i2c *i2c = hdmi->i2c; 468 int i = 20; 469 u8 interrupt = 0; 470 471 if (!i2c->is_regaddr) { 472 /* Use the first write byte as register address */ 473 i2c->slave_reg = buf[0]; 474 length--; 475 buf++; 476 i2c->is_regaddr = true; 477 } 478 479 while (length--) { 480 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 481 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 482 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 483 HDMI_I2CM_OPERATION); 484 485 while (i--) { 486 udelay(1000); 487 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 488 if (interrupt) 489 hdmi_writeb(hdmi, 490 interrupt, HDMI_IH_I2CM_STAT0); 491 492 if (interrupt & (m_SCDC_READREQ | 493 m_I2CM_DONE | m_I2CM_ERROR)) 494 break; 495 } 496 497 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 498 printf("[%s] write data error\n", __func__); 499 return -EIO; 500 } else if (interrupt & m_I2CM_DONE) { 501 printf("[%s] write offset %02x success\n", 502 __func__, i2c->slave_reg); 503 return -EAGAIN; 504 } 505 506 i = 20; 507 } 508 509 return 0; 510 } 511 512 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 513 struct i2c_msg *msgs, int num) 514 { 515 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 516 struct dw_hdmi_i2c *i2c = hdmi->i2c; 517 u8 addr = msgs[0].addr; 518 int i, ret = 0; 519 520 printf("xfer: num: %d, addr: %#x\n", num, addr); 521 for (i = 0; i < num; i++) { 522 if (msgs[i].len == 0) { 523 printf("unsupported transfer %d/%d, no data\n", 524 i + 1, num); 525 return -EOPNOTSUPP; 526 } 527 } 528 529 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 530 531 /* Set slave device address taken from the first I2C message */ 532 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 533 addr = DDC_ADDR; 534 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 535 536 /* Set slave device register address on transfer */ 537 i2c->is_regaddr = false; 538 539 /* Set segment pointer for I2C extended read mode operation */ 540 i2c->is_segment = false; 541 542 for (i = 0; i < num; i++) { 543 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 544 i + 1, num, msgs[i].len, msgs[i].flags); 545 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 546 i2c->is_segment = true; 547 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 548 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 549 } else { 550 if (msgs[i].flags & I2C_M_RD) 551 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 552 msgs[i].len); 553 else 554 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 555 msgs[i].len); 556 } 557 if (ret < 0) 558 break; 559 } 560 561 if (!ret) 562 ret = num; 563 564 /* Mute DONE and ERROR interrupts */ 565 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 566 HDMI_IH_MUTE_I2CM_STAT0); 567 568 return ret; 569 } 570 571 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 572 { 573 u32 val; 574 575 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 576 if (msec-- == 0) 577 return false; 578 udelay(1000); 579 } 580 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 581 582 return true; 583 } 584 585 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 586 unsigned char addr) 587 { 588 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 589 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 590 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 591 HDMI_PHY_I2CM_DATAO_1_ADDR); 592 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 593 HDMI_PHY_I2CM_DATAO_0_ADDR); 594 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 595 HDMI_PHY_I2CM_OPERATION_ADDR); 596 hdmi_phy_wait_i2c_done(hdmi, 1000); 597 } 598 599 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 600 { 601 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 602 HDMI_PHY_CONF0_PDZ_OFFSET, 603 HDMI_PHY_CONF0_PDZ_MASK); 604 } 605 606 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 607 { 608 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 609 HDMI_PHY_CONF0_ENTMDS_OFFSET, 610 HDMI_PHY_CONF0_ENTMDS_MASK); 611 } 612 613 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 614 { 615 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 616 HDMI_PHY_CONF0_SVSRET_OFFSET, 617 HDMI_PHY_CONF0_SVSRET_MASK); 618 } 619 620 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 621 { 622 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 623 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 624 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 625 } 626 627 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 628 { 629 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 630 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 631 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 632 } 633 634 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 635 { 636 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 637 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 638 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 639 } 640 641 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 642 { 643 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 644 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 645 HDMI_PHY_CONF0_SELDIPIF_MASK); 646 } 647 648 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 649 { 650 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 651 unsigned int i; 652 u16 val; 653 654 if (phy->gen == 1) { 655 dw_hdmi_phy_enable_tmds(hdmi, 0); 656 dw_hdmi_phy_enable_powerdown(hdmi, true); 657 return; 658 } 659 660 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 661 662 /* 663 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 664 * to low power mode. 665 */ 666 for (i = 0; i < 5; ++i) { 667 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 668 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 669 break; 670 671 udelay(2000); 672 } 673 674 if (val & HDMI_PHY_TX_PHY_LOCK) 675 printf("PHY failed to power down\n"); 676 else 677 printf("PHY powered down in %u iterations\n", i); 678 679 dw_hdmi_phy_gen2_pddq(hdmi, 1); 680 } 681 682 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 683 { 684 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 685 unsigned int i; 686 u8 val; 687 688 if (phy->gen == 1) { 689 dw_hdmi_phy_enable_powerdown(hdmi, false); 690 691 /* Toggle TMDS enable. */ 692 dw_hdmi_phy_enable_tmds(hdmi, 0); 693 dw_hdmi_phy_enable_tmds(hdmi, 1); 694 return 0; 695 } 696 697 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 698 dw_hdmi_phy_gen2_pddq(hdmi, 0); 699 700 /* Wait for PHY PLL lock */ 701 for (i = 0; i < 5; ++i) { 702 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 703 if (val) 704 break; 705 706 udelay(2000); 707 } 708 709 if (!val) { 710 printf("PHY PLL failed to lock\n"); 711 return -ETIMEDOUT; 712 } 713 printf("PHY PLL locked %u iterations\n", i); 714 715 return 0; 716 } 717 718 /* 719 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 720 * information the DWC MHL PHY has the same register layout and is thus also 721 * supported by this function. 722 */ 723 static 724 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 725 const struct dw_hdmi_plat_data *pdata, 726 unsigned long mpixelclock) 727 { 728 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 729 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 730 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 731 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 732 unsigned int depth = 733 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 734 735 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 736 pdata->mpll_cfg_420) 737 mpll_config = pdata->mpll_cfg_420; 738 739 /* PLL/MPLL Cfg - always match on final entry */ 740 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 741 if (mpixelclock <= mpll_config->mpixelclock) 742 break; 743 744 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 745 if (tmdsclock <= curr_ctrl->mpixelclock) 746 break; 747 748 for (; phy_config->mpixelclock != ~0UL; phy_config++) 749 if (tmdsclock <= phy_config->mpixelclock) 750 break; 751 752 if (mpll_config->mpixelclock == ~0UL || 753 curr_ctrl->mpixelclock == ~0UL || 754 phy_config->mpixelclock == ~0UL) 755 return -EINVAL; 756 757 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 758 depth = fls(depth - 8); 759 else 760 depth = 0; 761 if (depth) 762 depth--; 763 764 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 765 HDMI_3D_TX_PHY_CPCE_CTRL); 766 767 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 768 HDMI_3D_TX_PHY_GMPCTRL); 769 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 770 HDMI_3D_TX_PHY_CURRCTRL); 771 772 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 773 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 774 HDMI_3D_TX_PHY_MSM_CTRL); 775 776 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 777 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 778 HDMI_3D_TX_PHY_CKSYMTXCTRL); 779 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 780 HDMI_3D_TX_PHY_VLEVCTRL); 781 782 return 0; 783 } 784 785 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 786 { 787 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 788 .name = "DWC HDMI TX PHY", 789 .gen = 1, 790 }, { 791 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 792 .name = "DWC MHL PHY + HEAC PHY", 793 .gen = 2, 794 .has_svsret = true, 795 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 796 }, { 797 .type = DW_HDMI_PHY_DWC_MHL_PHY, 798 .name = "DWC MHL PHY", 799 .gen = 2, 800 .has_svsret = true, 801 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 802 }, { 803 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 804 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 805 .gen = 2, 806 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 807 }, { 808 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 809 .name = "DWC HDMI 3D TX PHY", 810 .gen = 2, 811 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 812 }, { 813 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 814 .name = "DWC HDMI 2.0 TX PHY", 815 .gen = 2, 816 .has_svsret = true, 817 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 818 }, { 819 .type = DW_HDMI_PHY_VENDOR_PHY, 820 .name = "Vendor PHY", 821 } 822 }; 823 824 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 825 int enable) 826 { 827 u8 stat; 828 829 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 830 831 if (stat < 0) { 832 debug("Failed to read tmds config\n"); 833 return false; 834 } 835 836 if (enable == 1) { 837 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 838 stat |= SCDC_SCRAMBLING_ENABLE; 839 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 840 /* TMDS software reset request */ 841 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 842 HDMI_MC_SWRSTZ); 843 /* Enable/Disable Scrambling */ 844 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 845 } else { 846 /* Enable/Disable Scrambling */ 847 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 848 /* TMDS software reset request */ 849 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 850 HDMI_MC_SWRSTZ); 851 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 852 stat &= ~SCDC_SCRAMBLING_ENABLE; 853 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 854 } 855 856 return 0; 857 } 858 859 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 860 { 861 u8 stat; 862 863 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 864 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 865 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 866 else 867 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 868 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 869 } 870 871 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 872 { 873 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 874 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 875 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 876 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 877 int ret; 878 879 dw_hdmi_phy_power_off(hdmi); 880 881 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 882 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 883 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 884 885 /* Leave low power consumption mode by asserting SVSRET. */ 886 if (phy->has_svsret) 887 dw_hdmi_phy_enable_svsret(hdmi, 1); 888 889 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 890 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 891 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 892 893 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 894 895 hdmi_phy_test_clear(hdmi, 1); 896 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 897 HDMI_PHY_I2CM_SLAVE_ADDR); 898 hdmi_phy_test_clear(hdmi, 0); 899 900 /* Write to the PHY as configured by the platform */ 901 if (pdata->configure_phy) 902 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 903 else 904 ret = phy->configure(hdmi, pdata, mpixelclock); 905 if (ret) { 906 printf("PHY configuration failed (clock %lu)\n", 907 mpixelclock); 908 return ret; 909 } 910 911 /* Wait for resuming transmission of TMDS clock and data */ 912 if (mtmdsclock > 340000000) 913 mdelay(100); 914 915 return dw_hdmi_phy_power_on(hdmi); 916 } 917 918 static int dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 919 void *data) 920 { 921 int i, ret; 922 923 /* HDMI Phy spec says to do the phy initialization sequence twice */ 924 for (i = 0; i < 2; i++) { 925 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 926 dw_hdmi_phy_sel_interface_control(hdmi, 0); 927 ret = hdmi_phy_configure(hdmi); 928 if (ret) 929 return ret; 930 } 931 932 return 0; 933 } 934 935 static void dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 936 void *data) 937 { 938 dw_hdmi_phy_power_off(hdmi); 939 } 940 941 static enum drm_connector_status 942 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 943 { 944 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 945 connector_status_connected : connector_status_disconnected; 946 } 947 948 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 949 .init = dw_hdmi_phy_init, 950 .disable = dw_hdmi_phy_disable, 951 .read_hpd = dw_hdmi_phy_read_hpd, 952 }; 953 954 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 955 { 956 unsigned int i; 957 u8 phy_type; 958 959 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 960 961 /* 962 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 963 * but it has a vedor phy. 964 */ 965 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 966 hdmi->dev_type == RK3528_HDMI || 967 hdmi->dev_type == RK3328_HDMI || 968 hdmi->dev_type == RK3228_HDMI) { 969 /* Vendor PHYs require support from the glue layer. */ 970 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 971 printf( 972 "Vendor HDMI PHY not supported by glue layer\n"); 973 return -ENODEV; 974 } 975 976 hdmi->phy.ops = hdmi->plat_data->phy_ops; 977 hdmi->phy.data = hdmi->plat_data->phy_data; 978 hdmi->phy.name = hdmi->plat_data->phy_name; 979 return 0; 980 } 981 982 /* Synopsys PHYs are handled internally. */ 983 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 984 if (dw_hdmi_phys[i].type == phy_type) { 985 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 986 hdmi->phy.name = dw_hdmi_phys[i].name; 987 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 988 989 if (!dw_hdmi_phys[i].configure && 990 !hdmi->plat_data->configure_phy) { 991 printf("%s requires platform support\n", 992 hdmi->phy.name); 993 return -ENODEV; 994 } 995 996 return 0; 997 } 998 } 999 1000 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 1001 return -ENODEV; 1002 } 1003 1004 static unsigned int 1005 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 1006 { 1007 unsigned int tmdsclock = mpixelclock; 1008 unsigned int depth = 1009 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1010 1011 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1012 switch (depth) { 1013 case 16: 1014 tmdsclock = mpixelclock * 2; 1015 break; 1016 case 12: 1017 tmdsclock = mpixelclock * 3 / 2; 1018 break; 1019 case 10: 1020 tmdsclock = mpixelclock * 5 / 4; 1021 break; 1022 default: 1023 break; 1024 } 1025 } 1026 1027 return tmdsclock; 1028 } 1029 1030 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1031 const struct drm_display_mode *mode) 1032 { 1033 u8 bytes = 0, inv_val = 0; 1034 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1035 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1036 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1037 unsigned int hdisplay, vdisplay; 1038 1039 vmode->mpixelclock = mode->crtc_clock * 1000; 1040 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1041 DRM_MODE_FLAG_3D_FRAME_PACKING) 1042 vmode->mpixelclock *= 2; 1043 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1044 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1045 vmode->mtmdsclock /= 2; 1046 printf("final pixclk = %d tmdsclk = %d\n", 1047 vmode->mpixelclock, vmode->mtmdsclock); 1048 1049 /* Set up HDMI_FC_INVIDCONF 1050 * fc_invidconf.HDCP_keepout must be set (1'b1) 1051 * when activate the scrambler feature. 1052 */ 1053 inv_val = (vmode->mtmdsclock > 340000000 || 1054 (hdmi_info->scdc.scrambling.low_rates && 1055 hdmi->scramble_low_rates) ? 1056 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1057 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1058 1059 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1060 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1061 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1062 1063 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1064 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1065 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1066 1067 inv_val |= (vmode->mdataenablepolarity ? 1068 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1069 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1070 1071 if (hdmi->vic == 39) 1072 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1073 else 1074 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1075 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1076 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1077 1078 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1079 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1080 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1081 1082 inv_val |= hdmi->sink_is_hdmi ? 1083 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1084 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1085 1086 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1087 1088 hdisplay = mode->hdisplay; 1089 hblank = mode->htotal - mode->hdisplay; 1090 h_de_hs = mode->hsync_start - mode->hdisplay; 1091 hsync_len = mode->hsync_end - mode->hsync_start; 1092 1093 /* 1094 * When we're setting a YCbCr420 mode, we need 1095 * to adjust the horizontal timing to suit. 1096 */ 1097 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1098 hdisplay /= 2; 1099 hblank /= 2; 1100 h_de_hs /= 2; 1101 hsync_len /= 2; 1102 } 1103 1104 vdisplay = mode->vdisplay; 1105 vblank = mode->vtotal - mode->vdisplay; 1106 v_de_vs = mode->vsync_start - mode->vdisplay; 1107 vsync_len = mode->vsync_end - mode->vsync_start; 1108 1109 /* 1110 * When we're setting an interlaced mode, we need 1111 * to adjust the vertical timing to suit. 1112 */ 1113 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1114 vdisplay /= 2; 1115 vblank /= 2; 1116 v_de_vs /= 2; 1117 vsync_len /= 2; 1118 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1119 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1120 vdisplay += mode->vtotal; 1121 } 1122 1123 /* Scrambling Control */ 1124 if (hdmi_info->scdc.supported) { 1125 if (vmode->mtmdsclock > 340000000 || 1126 (hdmi_info->scdc.scrambling.low_rates && 1127 hdmi->scramble_low_rates)) { 1128 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1129 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1130 bytes); 1131 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1132 } else { 1133 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1134 } 1135 } 1136 1137 /* Set up horizontal active pixel width */ 1138 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1139 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1140 1141 /* Set up vertical active lines */ 1142 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1143 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1144 1145 /* Set up horizontal blanking pixel region width */ 1146 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1147 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1148 1149 /* Set up vertical blanking pixel region width */ 1150 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1151 1152 /* Set up HSYNC active edge delay width (in pixel clks) */ 1153 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1154 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1155 1156 /* Set up VSYNC active edge delay (in lines) */ 1157 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1158 1159 /* Set up HSYNC active pulse width (in pixel clks) */ 1160 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1161 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1162 1163 /* Set up VSYNC active edge delay (in lines) */ 1164 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1165 } 1166 1167 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1168 { 1169 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1170 unsigned i; 1171 u32 csc_scale = 1; 1172 int enc_out_rgb, enc_in_rgb; 1173 1174 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1175 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1176 1177 if (is_color_space_conversion(hdmi)) { 1178 if (enc_out_rgb && enc_in_rgb) { 1179 csc_coeff = &csc_coeff_full_to_limited; 1180 csc_scale = 0; 1181 } else if (enc_out_rgb) { 1182 if (hdmi->hdmi_data.enc_out_encoding == 1183 V4L2_YCBCR_ENC_601) 1184 csc_coeff = &csc_coeff_rgb_out_eitu601; 1185 else 1186 csc_coeff = &csc_coeff_rgb_out_eitu709; 1187 } else if (enc_in_rgb) { 1188 if (hdmi->hdmi_data.enc_out_encoding == 1189 V4L2_YCBCR_ENC_601) 1190 csc_coeff = &csc_coeff_rgb_in_eitu601; 1191 else 1192 csc_coeff = &csc_coeff_rgb_in_eitu709; 1193 csc_scale = 0; 1194 } 1195 } 1196 1197 /* The CSC registers are sequential, alternating MSB then LSB */ 1198 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1199 u16 coeff_a = (*csc_coeff)[0][i]; 1200 u16 coeff_b = (*csc_coeff)[1][i]; 1201 u16 coeff_c = (*csc_coeff)[2][i]; 1202 1203 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1204 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1205 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1206 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1207 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1208 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1209 } 1210 1211 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1212 HDMI_CSC_SCALE); 1213 } 1214 1215 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1216 { 1217 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1218 return 0; 1219 1220 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1221 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1222 return 1; 1223 1224 return 0; 1225 } 1226 1227 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1228 { 1229 int color_depth = 0; 1230 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1231 int decimation = 0; 1232 1233 /* YCC422 interpolation to 444 mode */ 1234 if (is_color_space_interpolation(hdmi)) 1235 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1236 else if (is_color_space_decimation(hdmi)) 1237 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1238 1239 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1240 case 8: 1241 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1242 break; 1243 case 10: 1244 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1245 break; 1246 case 12: 1247 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1248 break; 1249 case 16: 1250 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1251 break; 1252 1253 default: 1254 return; 1255 } 1256 1257 /* Configure the CSC registers */ 1258 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1259 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1260 HDMI_CSC_SCALE); 1261 1262 dw_hdmi_update_csc_coeffs(hdmi); 1263 } 1264 1265 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1266 { 1267 u8 clkdis; 1268 1269 /* control period minimum duration */ 1270 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1271 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1272 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1273 1274 /* Set to fill TMDS data channels */ 1275 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1276 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1277 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1278 1279 /* Enable pixel clock and tmds data path */ 1280 clkdis = 0x7F; 1281 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1282 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1283 1284 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1285 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1286 1287 /* Enable csc path */ 1288 if (is_color_space_conversion(hdmi)) { 1289 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1290 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1291 } 1292 1293 /* Enable pixel repetition path */ 1294 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1295 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1296 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1297 } 1298 1299 /* Enable color space conversion if needed */ 1300 if (is_color_space_conversion(hdmi)) 1301 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1302 HDMI_MC_FLOWCTRL); 1303 else 1304 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1305 HDMI_MC_FLOWCTRL); 1306 } 1307 1308 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1309 { 1310 unsigned int count; 1311 unsigned int i; 1312 u8 val; 1313 1314 /* 1315 * Under some circumstances the Frame Composer arithmetic unit can miss 1316 * an FC register write due to being busy processing the previous one. 1317 * The issue can be worked around by issuing a TMDS software reset and 1318 * then write one of the FC registers several times. 1319 * 1320 * The number of iterations matters and depends on the HDMI TX revision 1321 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1322 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1323 * 4 and 1 iterations respectively. 1324 */ 1325 1326 switch (hdmi->version) { 1327 case 0x130a: 1328 count = 4; 1329 break; 1330 case 0x131a: 1331 case 0x200a: 1332 case 0x201a: 1333 case 0x211a: 1334 count = 1; 1335 break; 1336 default: 1337 return; 1338 } 1339 1340 /* TMDS software reset */ 1341 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1342 1343 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1344 for (i = 0; i < count; i++) 1345 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1346 } 1347 1348 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1349 { 1350 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1351 HDMI_IH_MUTE_FC_STAT2); 1352 } 1353 1354 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1355 { 1356 unsigned int color_depth = 0; 1357 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1358 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1359 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1360 u8 val, vp_conf; 1361 1362 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1363 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1364 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1365 switch (hdmi_bus_fmt_color_depth( 1366 hdmi->hdmi_data.enc_out_bus_format)) { 1367 case 8: 1368 color_depth = 0; 1369 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1370 break; 1371 case 10: 1372 color_depth = 5; 1373 break; 1374 case 12: 1375 color_depth = 6; 1376 break; 1377 case 16: 1378 color_depth = 7; 1379 break; 1380 default: 1381 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1382 } 1383 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1384 switch (hdmi_bus_fmt_color_depth( 1385 hdmi->hdmi_data.enc_out_bus_format)) { 1386 case 0: 1387 case 8: 1388 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1389 break; 1390 case 10: 1391 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1392 break; 1393 case 12: 1394 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1395 break; 1396 1397 default: 1398 return; 1399 } 1400 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1401 } else { 1402 return; 1403 } 1404 1405 /* set the packetizer registers */ 1406 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1407 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1408 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1409 1410 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1411 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1412 1413 /* Data from pixel repeater block */ 1414 if (hdmi_data->pix_repet_factor > 0) { 1415 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1416 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1417 } else { /* data from packetizer block */ 1418 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1419 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1420 } 1421 1422 hdmi_modb(hdmi, vp_conf, 1423 HDMI_VP_CONF_PR_EN_MASK | 1424 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1425 1426 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1427 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1428 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1429 HDMI_VP_STUFF); 1430 else 1431 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1432 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1433 1434 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1435 1436 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1437 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1438 HDMI_VP_CONF_PP_EN_ENABLE | 1439 HDMI_VP_CONF_YCC422_EN_DISABLE; 1440 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1441 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1442 HDMI_VP_CONF_PP_EN_DISABLE | 1443 HDMI_VP_CONF_YCC422_EN_ENABLE; 1444 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1445 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1446 HDMI_VP_CONF_PP_EN_DISABLE | 1447 HDMI_VP_CONF_YCC422_EN_DISABLE; 1448 } else { 1449 return; 1450 } 1451 1452 hdmi_modb(hdmi, vp_conf, 1453 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1454 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1455 1456 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1457 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1458 HDMI_VP_STUFF_PP_STUFFING_MASK | 1459 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1460 1461 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1462 HDMI_VP_CONF); 1463 } 1464 1465 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1466 { 1467 int color_format = 0; 1468 u8 val; 1469 1470 switch (hdmi->hdmi_data.enc_in_bus_format) { 1471 case MEDIA_BUS_FMT_RGB888_1X24: 1472 color_format = 0x01; 1473 break; 1474 case MEDIA_BUS_FMT_RGB101010_1X30: 1475 color_format = 0x03; 1476 break; 1477 case MEDIA_BUS_FMT_RGB121212_1X36: 1478 color_format = 0x05; 1479 break; 1480 case MEDIA_BUS_FMT_RGB161616_1X48: 1481 color_format = 0x07; 1482 break; 1483 1484 case MEDIA_BUS_FMT_YUV8_1X24: 1485 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1486 color_format = 0x09; 1487 break; 1488 case MEDIA_BUS_FMT_YUV10_1X30: 1489 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1490 color_format = 0x0B; 1491 break; 1492 case MEDIA_BUS_FMT_YUV12_1X36: 1493 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1494 color_format = 0x0D; 1495 break; 1496 case MEDIA_BUS_FMT_YUV16_1X48: 1497 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1498 color_format = 0x0F; 1499 break; 1500 1501 case MEDIA_BUS_FMT_UYVY8_1X16: 1502 color_format = 0x16; 1503 break; 1504 case MEDIA_BUS_FMT_UYVY10_1X20: 1505 color_format = 0x14; 1506 break; 1507 case MEDIA_BUS_FMT_UYVY12_1X24: 1508 color_format = 0x12; 1509 break; 1510 1511 default: 1512 return; 1513 } 1514 1515 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1516 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1517 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1518 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1519 1520 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1521 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1522 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1523 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1524 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1525 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1526 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1527 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1528 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1529 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1530 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1531 } 1532 1533 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 1534 struct display_state *state) 1535 { 1536 if (hdmi->phy.enabled) { 1537 hdmi->phy.ops->disable(conn, hdmi, state); 1538 hdmi->phy.enabled = false; 1539 } 1540 } 1541 1542 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1543 { 1544 struct hdmi_avi_infoframe frame; 1545 u8 val; 1546 bool is_hdmi2 = false; 1547 enum hdmi_quantization_range rgb_quant_range = 1548 hdmi->hdmi_data.quant_range; 1549 1550 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1551 hdmi->edid_data.display_info.hdmi.scdc.supported) 1552 is_hdmi2 = true; 1553 /* Initialise info frame from DRM mode */ 1554 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1555 1556 /* 1557 * Ignore monitor selectable quantization, use quantization set 1558 * by the user 1559 */ 1560 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1561 true); 1562 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1563 frame.colorspace = HDMI_COLORSPACE_YUV444; 1564 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1565 frame.colorspace = HDMI_COLORSPACE_YUV422; 1566 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1567 frame.colorspace = HDMI_COLORSPACE_YUV420; 1568 else 1569 frame.colorspace = HDMI_COLORSPACE_RGB; 1570 1571 /* Set up colorimetry */ 1572 switch (hdmi->hdmi_data.enc_out_encoding) { 1573 case V4L2_YCBCR_ENC_601: 1574 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1575 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1576 else 1577 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1578 frame.extended_colorimetry = 1579 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1580 break; 1581 case V4L2_YCBCR_ENC_709: 1582 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1583 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1584 else 1585 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1586 frame.extended_colorimetry = 1587 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1588 break; 1589 default: /* Carries no data */ 1590 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1591 frame.extended_colorimetry = 1592 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1593 break; 1594 } 1595 1596 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1597 1598 /* 1599 * The Designware IP uses a different byte format from standard 1600 * AVI info frames, though generally the bits are in the correct 1601 * bytes. 1602 */ 1603 1604 /* 1605 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1606 * 5,6,7, active aspect present in bit 6 rather than 4. 1607 */ 1608 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1609 if (frame.active_aspect & 15) 1610 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1611 if (frame.top_bar || frame.bottom_bar) 1612 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1613 if (frame.left_bar || frame.right_bar) 1614 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1615 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1616 1617 /* AVI data byte 2 differences: none */ 1618 val = ((frame.colorimetry & 0x3) << 6) | 1619 ((frame.picture_aspect & 0x3) << 4) | 1620 (frame.active_aspect & 0xf); 1621 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1622 1623 /* AVI data byte 3 differences: none */ 1624 val = ((frame.extended_colorimetry & 0x7) << 4) | 1625 ((frame.quantization_range & 0x3) << 2) | 1626 (frame.nups & 0x3); 1627 if (frame.itc) 1628 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1629 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1630 1631 /* AVI data byte 4 differences: none */ 1632 val = frame.video_code & 0x7f; 1633 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1634 1635 /* AVI Data Byte 5- set up input and output pixel repetition */ 1636 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1637 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1638 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1639 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1640 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1641 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1642 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1643 1644 /* 1645 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1646 * ycc range in bits 2,3 rather than 6,7 1647 */ 1648 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1649 (frame.content_type & 0x3); 1650 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1651 1652 /* AVI Data Bytes 6-13 */ 1653 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1654 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1655 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1656 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1657 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1658 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1659 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1660 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1661 } 1662 1663 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1664 struct drm_display_mode *mode) 1665 { 1666 struct hdmi_vendor_infoframe frame; 1667 u8 buffer[10]; 1668 ssize_t err; 1669 1670 /* Disable HDMI vendor specific infoframe send */ 1671 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1672 HDMI_FC_DATAUTO0_VSD_MASK); 1673 1674 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1675 if (err < 0) 1676 /* 1677 * Going into that statement does not means vendor infoframe 1678 * fails. It just informed us that vendor infoframe is not 1679 * needed for the selected mode. Only 4k or stereoscopic 3D 1680 * mode requires vendor infoframe. So just simply return. 1681 */ 1682 return; 1683 1684 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1685 if (err < 0) { 1686 printf("Failed to pack vendor infoframe: %zd\n", err); 1687 return; 1688 } 1689 1690 /* Set the length of HDMI vendor specific InfoFrame payload */ 1691 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1692 1693 /* Set 24bit IEEE Registration Identifier */ 1694 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1695 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1696 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1697 1698 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1699 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1700 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1701 1702 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1703 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1704 1705 /* Packet frame interpolation */ 1706 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1707 1708 /* Auto packets per frame and line spacing */ 1709 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1710 1711 /* Configures the Frame Composer On RDRB mode */ 1712 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1713 HDMI_FC_DATAUTO0_VSD_MASK); 1714 } 1715 1716 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1717 unsigned int n) 1718 { 1719 /* Must be set/cleared first */ 1720 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1721 1722 /* nshift factor = 0 */ 1723 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1724 1725 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1726 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1727 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1728 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1729 1730 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1731 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1732 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1733 } 1734 1735 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1736 unsigned long pixel_clk, 1737 unsigned long freq) 1738 { 1739 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1740 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1741 int i; 1742 1743 if (plat_data->tmds_n_table) { 1744 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1745 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1746 tmds_n = &plat_data->tmds_n_table[i]; 1747 break; 1748 } 1749 } 1750 } 1751 1752 if (!tmds_n) { 1753 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1754 if (pixel_clk == common_tmds_n_table[i].tmds) { 1755 tmds_n = &common_tmds_n_table[i]; 1756 break; 1757 } 1758 } 1759 } 1760 1761 if (!tmds_n) 1762 return -ENOENT; 1763 1764 switch (freq) { 1765 case 32000: 1766 return tmds_n->n_32k; 1767 case 44100: 1768 case 88200: 1769 case 176400: 1770 return (freq / 44100) * tmds_n->n_44k1; 1771 case 48000: 1772 case 96000: 1773 case 192000: 1774 return (freq / 48000) * tmds_n->n_48k; 1775 default: 1776 return -ENOENT; 1777 } 1778 } 1779 1780 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1781 unsigned int pixel_clk) 1782 { 1783 u64 final, diff; 1784 u64 cts; 1785 1786 final = (u64)pixel_clk * n; 1787 1788 cts = final; 1789 do_div(cts, 128 * freq); 1790 1791 diff = final - (u64)cts * (128 * freq); 1792 1793 return diff; 1794 } 1795 1796 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1797 unsigned long pixel_clk, 1798 unsigned long freq) 1799 { 1800 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1801 unsigned int max_n = (128 * freq) / 300; 1802 unsigned int ideal_n = (128 * freq) / 1000; 1803 unsigned int best_n_distance = ideal_n; 1804 unsigned int best_n = 0; 1805 u64 best_diff = U64_MAX; 1806 int n; 1807 1808 /* If the ideal N could satisfy the audio math, then just take it */ 1809 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1810 return ideal_n; 1811 1812 for (n = min_n; n <= max_n; n++) { 1813 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1814 1815 if (diff < best_diff || (diff == best_diff && 1816 abs(n - ideal_n) < best_n_distance)) { 1817 best_n = n; 1818 best_diff = diff; 1819 best_n_distance = abs(best_n - ideal_n); 1820 } 1821 1822 /* 1823 * The best N already satisfy the audio math, and also be 1824 * the closest value to ideal N, so just cut the loop. 1825 */ 1826 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1827 break; 1828 } 1829 1830 return best_n; 1831 } 1832 1833 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1834 unsigned long sample_rate) 1835 { 1836 int n; 1837 1838 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1839 if (n > 0) 1840 return n; 1841 1842 printf("Rate %lu missing; compute N dynamically\n", 1843 pixel_clk); 1844 1845 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1846 } 1847 1848 static 1849 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1850 unsigned int sample_rate) 1851 { 1852 unsigned long ftdms = pixel_clk; 1853 unsigned int n, cts; 1854 u64 tmp; 1855 1856 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1857 1858 /* 1859 * Compute the CTS value from the N value. Note that CTS and N 1860 * can be up to 20 bits in total, so we need 64-bit math. Also 1861 * note that our TDMS clock is not fully accurate; it is accurate 1862 * to kHz. This can introduce an unnecessary remainder in the 1863 * calculation below, so we don't try to warn about that. 1864 */ 1865 tmp = (u64)ftdms * n; 1866 do_div(tmp, 128 * sample_rate); 1867 cts = tmp; 1868 1869 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1870 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1871 1872 hdmi->audio_n = n; 1873 hdmi->audio_cts = cts; 1874 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1875 } 1876 1877 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1878 { 1879 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1880 hdmi->sample_rate); 1881 } 1882 1883 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1884 { 1885 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1886 } 1887 1888 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1889 { 1890 hdmi->sample_rate = rate; 1891 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1892 hdmi->sample_rate); 1893 } 1894 1895 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1896 { 1897 int i, j, ret, val; 1898 struct hdcp_keys *hdcp_keys; 1899 1900 val = sizeof(*hdcp_keys); 1901 hdcp_keys = malloc(val); 1902 if (!hdcp_keys) 1903 return -ENOMEM; 1904 1905 memset(hdcp_keys, 0, val); 1906 1907 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1908 if (ret < val) { 1909 printf("HDCP: read size %d\n", ret); 1910 free(hdcp_keys); 1911 return -EINVAL; 1912 } 1913 1914 if (hdcp_keys->KSV[0] == 0x00 && 1915 hdcp_keys->KSV[1] == 0x00 && 1916 hdcp_keys->KSV[2] == 0x00 && 1917 hdcp_keys->KSV[3] == 0x00 && 1918 hdcp_keys->KSV[4] == 0x00) { 1919 printf("HDCP: Invalid hdcp key\n"); 1920 free(hdcp_keys); 1921 return -EINVAL; 1922 } 1923 1924 /* Disable decryption logic */ 1925 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1926 /* Poll untile DPK write is allowed */ 1927 do { 1928 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1929 } while ((val & DPK_WR_OK_STS) == 0); 1930 1931 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1932 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1933 1934 /* The useful data in ksv should be 5 byte */ 1935 for (i = 4; i >= 0; i--) 1936 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1937 /* Poll untile DPK write is allowed */ 1938 do { 1939 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1940 } while ((val & DPK_WR_OK_STS) == 0); 1941 1942 /* Enable decryption logic */ 1943 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1944 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1945 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1946 1947 /* Write encrypt device private key */ 1948 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1949 for (j = 6; j >= 0; j--) 1950 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1951 HDMI_HDCPREG_DPK0 + j); 1952 do { 1953 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1954 } while ((val & DPK_WR_OK_STS) == 0); 1955 } 1956 1957 free(hdcp_keys); 1958 return 0; 1959 } 1960 1961 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1962 const struct drm_display_mode *mode) 1963 { 1964 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1965 1966 if (!hdmi->hdcp1x_enable) 1967 return; 1968 1969 /* Configure the video polarity */ 1970 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1971 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1972 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1973 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1974 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1975 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1976 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1977 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1978 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1979 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1980 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1981 HDMI_A_VIDPOLCFG); 1982 1983 /* Config the display mode */ 1984 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1985 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1986 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1987 HDMI_A_HDCPCFG0); 1988 1989 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1990 dw_hdmi_hdcp_load_key(hdmi); 1991 1992 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1993 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1994 HDMI_FC_INVIDCONF); 1995 1996 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1997 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1998 HDMI_HDCP2_FORCE_DISABLE, 1999 HDMI_HDCP2_OVR_EN_MASK | 2000 HDMI_HDCP2_FORCE_MASK, 2001 HDMI_HDCP2REG_CTRL); 2002 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 2003 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 2004 } 2005 2006 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 2007 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2008 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2009 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2010 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2011 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2012 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2013 2014 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2015 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2016 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2017 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2018 2019 /* Reset HDCP Engine */ 2020 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2021 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2022 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2023 } 2024 2025 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2026 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2027 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2028 2029 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2030 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2031 2032 printf("%s success\n", __func__); 2033 } 2034 2035 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2036 struct rockchip_connector *conn, 2037 struct drm_display_mode *mode, 2038 struct display_state *state) 2039 { 2040 int ret; 2041 void *data = hdmi->plat_data->phy_data; 2042 2043 hdmi_disable_overflow_interrupts(hdmi); 2044 if (!hdmi->vic) 2045 printf("Non-CEA mode used in HDMI\n"); 2046 else 2047 printf("CEA mode used vic=%d\n", hdmi->vic); 2048 2049 if (hdmi->plat_data->get_enc_out_encoding) 2050 hdmi->hdmi_data.enc_out_encoding = 2051 hdmi->plat_data->get_enc_out_encoding(data); 2052 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2053 hdmi->vic == 21 || hdmi->vic == 22 || 2054 hdmi->vic == 2 || hdmi->vic == 3 || 2055 hdmi->vic == 17 || hdmi->vic == 18) 2056 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2057 else 2058 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2059 2060 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2061 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2062 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2063 } else { 2064 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2065 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2066 } 2067 2068 /* TOFIX: Get input encoding from plat data or fallback to none */ 2069 if (hdmi->plat_data->get_enc_in_encoding) 2070 hdmi->hdmi_data.enc_in_encoding = 2071 hdmi->plat_data->get_enc_in_encoding(data); 2072 else if (hdmi->plat_data->input_bus_encoding) 2073 hdmi->hdmi_data.enc_in_encoding = 2074 hdmi->plat_data->input_bus_encoding; 2075 else 2076 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2077 2078 if (hdmi->plat_data->get_quant_range) 2079 hdmi->hdmi_data.quant_range = 2080 hdmi->plat_data->get_quant_range(data); 2081 else 2082 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2083 2084 /* 2085 * According to the dw-hdmi specification 6.4.2 2086 * vp_pr_cd[3:0]: 2087 * 0000b: No pixel repetition (pixel sent only once) 2088 * 0001b: Pixel sent two times (pixel repeated once) 2089 */ 2090 hdmi->hdmi_data.pix_repet_factor = 2091 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2092 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2093 2094 /* HDMI Initialization Step B.1 */ 2095 hdmi_av_composer(hdmi, mode); 2096 2097 /* HDMI Initialization Step B.2 */ 2098 ret = hdmi->phy.ops->init(conn, hdmi, state); 2099 if (ret) 2100 return ret; 2101 hdmi->phy.enabled = true; 2102 2103 /* HDMI Initializateion Step B.3 */ 2104 dw_hdmi_enable_video_path(hdmi); 2105 2106 /* HDMI Initialization Step E - Configure audio */ 2107 if (hdmi->sink_has_audio) { 2108 printf("sink has audio support\n"); 2109 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2110 hdmi_enable_audio_clk(hdmi); 2111 } 2112 2113 /* not for DVI mode */ 2114 if (hdmi->sink_is_hdmi) { 2115 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2116 hdmi_config_AVI(hdmi, mode); 2117 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2118 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2119 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2120 HDMI_A_HDCPCFG0); 2121 } else { 2122 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2123 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2124 HDMI_A_HDCPCFG0); 2125 printf("%s DVI mode\n", __func__); 2126 } 2127 2128 hdmi_video_packetize(hdmi); 2129 hdmi_video_csc(hdmi); 2130 hdmi_video_sample(hdmi); 2131 hdmi_tx_hdcp_config(hdmi, mode); 2132 dw_hdmi_clear_overflow(hdmi); 2133 2134 return 0; 2135 } 2136 2137 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2138 struct display_state *state) 2139 { 2140 return hdmi->phy.ops->read_hpd(hdmi, state); 2141 } 2142 2143 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2144 { 2145 switch (hdmi->io_width) { 2146 case 4: 2147 hdmi->write = dw_hdmi_writel; 2148 hdmi->read = dw_hdmi_readl; 2149 break; 2150 case 1: 2151 hdmi->write = dw_hdmi_writeb; 2152 hdmi->read = dw_hdmi_readb; 2153 break; 2154 default: 2155 printf("reg-io-width must be 1 or 4\n"); 2156 return -EINVAL; 2157 } 2158 2159 return 0; 2160 } 2161 2162 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2163 { 2164 /*mute unnecessary interrupt, only enable hpd */ 2165 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2166 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2167 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2168 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2169 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2170 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2171 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2172 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2173 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2174 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2175 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2176 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2177 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2178 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2179 2180 /*Force output black*/ 2181 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2182 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2183 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2184 } 2185 2186 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2187 { 2188 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2189 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2190 2191 initialize_hdmi_mutes(hdmi); 2192 } 2193 2194 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2195 { 2196 unsigned long low_ns, high_ns; 2197 unsigned long div_low, div_high; 2198 2199 /* Standard-mode */ 2200 if (hdmi->i2c->scl_high_ns < 4000) 2201 high_ns = 4708; 2202 else 2203 high_ns = hdmi->i2c->scl_high_ns; 2204 2205 if (hdmi->i2c->scl_low_ns < 4700) 2206 low_ns = 4916; 2207 else 2208 low_ns = hdmi->i2c->scl_low_ns; 2209 2210 div_low = (24000 * low_ns) / 1000000; 2211 if ((24000 * low_ns) % 1000000) 2212 div_low++; 2213 2214 div_high = (24000 * high_ns) / 1000000; 2215 if ((24000 * high_ns) % 1000000) 2216 div_high++; 2217 2218 /* Maximum divider supported by hw is 0xffff */ 2219 if (div_low > 0xffff) 2220 div_low = 0xffff; 2221 2222 if (div_high > 0xffff) 2223 div_high = 0xffff; 2224 2225 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2226 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2227 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2228 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2229 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2230 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2231 } 2232 2233 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2234 { 2235 /* Software reset */ 2236 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2237 2238 /* Set Standard Mode speed */ 2239 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2240 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2241 2242 /* Set done, not acknowledged and arbitration interrupt polarities */ 2243 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2244 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2245 HDMI_I2CM_CTLINT); 2246 2247 /* Clear DONE and ERROR interrupts */ 2248 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2249 HDMI_IH_I2CM_STAT0); 2250 2251 /* Mute DONE and ERROR interrupts */ 2252 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2253 HDMI_IH_MUTE_I2CM_STAT0); 2254 2255 /* set SDA high level holding time */ 2256 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2257 2258 dw_hdmi_i2c_set_divs(hdmi); 2259 } 2260 2261 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2262 { 2263 hdmi->audio_enable = true; 2264 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2265 } 2266 2267 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2268 { 2269 hdmi->audio_enable = false; 2270 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2271 } 2272 2273 int rockchip_dw_hdmi_init(struct rockchip_connector *conn, struct display_state *state) 2274 { 2275 struct connector_state *conn_state = &state->conn_state; 2276 const struct dw_hdmi_plat_data *pdata = 2277 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 2278 struct crtc_state *crtc_state = &state->crtc_state; 2279 struct dw_hdmi *hdmi; 2280 struct drm_display_mode *mode_buf; 2281 ofnode hdmi_node = conn->dev->node; 2282 u32 val; 2283 struct device_node *ddc_node; 2284 int ret; 2285 2286 hdmi = malloc(sizeof(struct dw_hdmi)); 2287 if (!hdmi) 2288 return -ENOMEM; 2289 2290 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2291 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2292 if (!mode_buf) 2293 return -ENOMEM; 2294 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 2295 if (hdmi->id < 0) 2296 hdmi->id = 0; 2297 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 2298 2299 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2300 2301 hdmi->dev_type = pdata->dev_type; 2302 hdmi->plat_data = pdata; 2303 2304 hdmi->regs = dev_read_addr_ptr(conn->dev); 2305 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2306 2307 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2308 hdmi->scramble_low_rates = true; 2309 2310 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2311 hdmi->hdcp1x_enable = true; 2312 else 2313 hdmi->hdcp1x_enable = false; 2314 2315 if (ofnode_read_bool(hdmi_node, "force_output_bus_format_RGB") || 2316 ofnode_read_bool(hdmi_node, "unsupported-yuv-input")) 2317 hdmi->output_bus_format_rgb = true; 2318 else 2319 hdmi->output_bus_format_rgb = false; 2320 2321 ret = dev_read_size(conn->dev, "rockchip,phy-table"); 2322 if (ret > 0 && hdmi->plat_data->phy_config) { 2323 u32 phy_config[ret / 4]; 2324 int i; 2325 2326 dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4); 2327 2328 for (i = 0; i < ret / 16; i++) { 2329 if (phy_config[i * 4] != 0) 2330 hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4]; 2331 else 2332 hdmi->plat_data->phy_config[i].mpixelclock = ~0UL; 2333 hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1]; 2334 hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2]; 2335 hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3]; 2336 } 2337 } 2338 2339 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 2340 if (ddc_node) { 2341 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 2342 &hdmi->adap.i2c_bus); 2343 if (hdmi->adap.i2c_bus) 2344 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 2345 } 2346 2347 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2348 if (hdmi->grf <= 0) { 2349 printf("%s: Get syscon grf failed (ret=%p)\n", 2350 __func__, hdmi->grf); 2351 return -ENXIO; 2352 } 2353 2354 hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1); 2355 if (!hdmi->gpio_base) 2356 return -ENODEV; 2357 2358 ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0, 2359 &hdmi->hpd_gpiod, GPIOD_IS_IN); 2360 if (ret && ret != -ENOENT) { 2361 printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret); 2362 return ret; 2363 } 2364 2365 dw_hdmi_set_reg_wr(hdmi); 2366 2367 if (pdata->grf_vop_sel_reg) { 2368 if (crtc_state->crtc_id) 2369 val = ((1 << pdata->vop_sel_bit) | 2370 (1 << (16 + pdata->vop_sel_bit))); 2371 else 2372 val = ((0 << pdata->vop_sel_bit) | 2373 (1 << (16 + pdata->vop_sel_bit))); 2374 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2375 } 2376 2377 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2378 if (!hdmi->i2c) 2379 return -ENOMEM; 2380 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2381 2382 /* 2383 * Read high and low time from device tree. If not available use 2384 * the default timing scl clock rate is about 99.6KHz. 2385 */ 2386 hdmi->i2c->scl_high_ns = 2387 ofnode_read_s32_default(hdmi_node, 2388 "ddc-i2c-scl-high-time-ns", 4708); 2389 hdmi->i2c->scl_low_ns = 2390 ofnode_read_s32_default(hdmi_node, 2391 "ddc-i2c-scl-low-time-ns", 4916); 2392 2393 dw_hdmi_i2c_init(hdmi); 2394 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2395 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2396 2397 hdmi->edid_data.mode_buf = mode_buf; 2398 hdmi->sample_rate = 48000; 2399 2400 conn->data = hdmi; 2401 dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base, 2402 &hdmi->hpd_gpiod, hdmi->dev_type); 2403 dw_hdmi_detect_phy(hdmi); 2404 dw_hdmi_dev_init(hdmi); 2405 2406 return 0; 2407 } 2408 2409 void rockchip_dw_hdmi_deinit(struct rockchip_connector *conn, struct display_state *state) 2410 { 2411 struct dw_hdmi *hdmi = conn->data; 2412 2413 if (hdmi->i2c) 2414 free(hdmi->i2c); 2415 if (hdmi->edid_data.mode_buf) 2416 free(hdmi->edid_data.mode_buf); 2417 if (hdmi) 2418 free(hdmi); 2419 } 2420 2421 int rockchip_dw_hdmi_prepare(struct rockchip_connector *conn, struct display_state *state) 2422 { 2423 return 0; 2424 } 2425 2426 int rockchip_dw_hdmi_enable(struct rockchip_connector *conn, struct display_state *state) 2427 { 2428 struct connector_state *conn_state = &state->conn_state; 2429 struct drm_display_mode *mode = &conn_state->mode; 2430 struct dw_hdmi *hdmi = conn->data; 2431 2432 if (!hdmi) 2433 return -EFAULT; 2434 2435 /* Store the display mode for plugin/DKMS poweron events */ 2436 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2437 2438 dw_hdmi_setup(hdmi, conn, mode, state); 2439 2440 return 0; 2441 } 2442 2443 int rockchip_dw_hdmi_disable(struct rockchip_connector *conn, struct display_state *state) 2444 { 2445 struct dw_hdmi *hdmi = conn->data; 2446 2447 dw_hdmi_disable(conn, hdmi, state); 2448 return 0; 2449 } 2450 2451 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state) 2452 { 2453 int ret, i; 2454 struct connector_state *conn_state = &state->conn_state; 2455 struct drm_display_mode *mode = &conn_state->mode; 2456 struct dw_hdmi *hdmi = conn->data; 2457 struct edid *edid = (struct edid *)conn_state->edid; 2458 unsigned int bus_format; 2459 unsigned long enc_out_encoding; 2460 struct overscan *overscan = &conn_state->overscan; 2461 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2462 2463 if (!hdmi) 2464 return -EFAULT; 2465 2466 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2467 2468 if (!ret) { 2469 hdmi->sink_is_hdmi = 2470 drm_detect_hdmi_monitor(edid); 2471 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2472 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2473 } 2474 if (ret < 0) { 2475 hdmi->sink_is_hdmi = true; 2476 hdmi->sink_has_audio = true; 2477 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2478 sizeof(def_modes_vic)); 2479 hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED; 2480 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2481 printf("failed to get edid\n"); 2482 } 2483 drm_rk_filter_whitelist(&hdmi->edid_data); 2484 if (hdmi->phy.ops->mode_valid) 2485 hdmi->phy.ops->mode_valid(conn, hdmi, state); 2486 drm_mode_max_resolution_filter(&hdmi->edid_data, 2487 &state->crtc_state.max_output); 2488 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2489 printf("can't find valid hdmi mode\n"); 2490 return -EINVAL; 2491 } 2492 2493 for (i = 0; i < hdmi->edid_data.modes; i++) 2494 hdmi->edid_data.mode_buf[i].vrefresh = 2495 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2496 2497 drm_mode_sort(&hdmi->edid_data); 2498 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format, 2499 overscan, hdmi->dev_type, hdmi->output_bus_format_rgb); 2500 2501 *mode = *hdmi->edid_data.preferred_mode; 2502 hdmi->vic = drm_match_cea_mode(mode); 2503 2504 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2505 if (state->force_output) 2506 bus_format = state->force_bus_format; 2507 conn_state->bus_format = bus_format; 2508 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2509 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2510 2511 switch (bus_format) { 2512 case MEDIA_BUS_FMT_UYVY10_1X20: 2513 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2514 hdmi->hdmi_data.enc_in_bus_format = 2515 MEDIA_BUS_FMT_YUV10_1X30; 2516 break; 2517 case MEDIA_BUS_FMT_UYVY8_1X16: 2518 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2519 hdmi->hdmi_data.enc_in_bus_format = 2520 MEDIA_BUS_FMT_YUV8_1X24; 2521 break; 2522 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2523 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2524 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2525 break; 2526 } 2527 2528 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2529 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2530 hdmi->vic == 17 || hdmi->vic == 18) 2531 enc_out_encoding = V4L2_YCBCR_ENC_601; 2532 else 2533 enc_out_encoding = V4L2_YCBCR_ENC_709; 2534 2535 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2536 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2537 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2538 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2539 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2540 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2541 conn_state->color_space = V4L2_COLORSPACE_REC709; 2542 else 2543 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2544 2545 return 0; 2546 } 2547 2548 int rockchip_dw_hdmi_detect(struct rockchip_connector *conn, struct display_state *state) 2549 { 2550 int ret; 2551 struct dw_hdmi *hdmi = conn->data; 2552 2553 if (!hdmi) 2554 return -EFAULT; 2555 2556 ret = dw_hdmi_detect_hotplug(hdmi, state); 2557 2558 return ret; 2559 } 2560 2561 int rockchip_dw_hdmi_get_edid(struct rockchip_connector *conn, struct display_state *state) 2562 { 2563 int ret; 2564 struct connector_state *conn_state = &state->conn_state; 2565 struct dw_hdmi *hdmi = conn->data; 2566 2567 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2568 2569 return ret; 2570 } 2571 2572 int inno_dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2573 { 2574 struct display_state *state = (struct display_state *)data; 2575 struct connector_state *conn_state = &state->conn_state; 2576 u32 color_depth, bus_width; 2577 2578 color_depth = 2579 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2580 2581 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2582 bus_width = color_depth / 2; 2583 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2584 bus_width = color_depth; 2585 else 2586 bus_width = 8; 2587 rockchip_phy_set_bus_width(conn->phy, bus_width); 2588 rockchip_phy_set_pll(conn->phy, 2589 conn_state->mode.crtc_clock * 1000); 2590 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2591 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2592 rockchip_phy_power_on(conn->phy); 2593 2594 return 0; 2595 } 2596 2597 void inno_dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2598 { 2599 } 2600 2601 enum drm_connector_status 2602 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2603 { 2604 enum drm_connector_status status; 2605 struct display_state *state = (struct display_state *)data; 2606 2607 status = dw_hdmi_phy_read_hpd(hdmi, state); 2608 2609 if (hdmi->dev_type == RK3328_HDMI) { 2610 if (status == connector_status_connected) 2611 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2612 else 2613 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2614 } 2615 2616 return status; 2617 } 2618 2619 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2620 { 2621 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2622 unsigned long rate; 2623 int i, ret; 2624 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2625 2626 for (i = 0; i < edid_data->modes; i++) { 2627 if (edid_data->mode_buf[i].invalid) 2628 continue; 2629 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2630 rate = mode_buf[i].clock * 1000 * 2; 2631 else 2632 rate = mode_buf[i].clock * 1000; 2633 2634 /* Check whether mode is out of phy cfg range. */ 2635 ret = rockchip_phy_round_rate(conn->phy, rate); 2636 2637 if (ret < 0) 2638 edid_data->mode_buf[i].invalid = true; 2639 } 2640 } 2641