xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3399-u-boot.dtsi (revision 6aa65bb1ee0951865e27da81dde1de76c6d4687e) 
1/*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &sdhci;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdhci, &sdmmc;
16	};
17};
18
19&uart2 {
20	clock-frequency = <24000000>;
21	u-boot,dm-pre-reloc;
22};
23
24&saradc {
25	u-boot,dm-pre-reloc;
26};
27
28&sdmmc {
29	u-boot,dm-pre-reloc;
30};
31
32&sdhci {
33	u-boot,dm-pre-reloc;
34};
35
36&pmu {
37	u-boot,dm-pre-reloc;
38};
39
40&pmugrf {
41	u-boot,dm-pre-reloc;
42};
43
44&pmusgrf {
45	u-boot,dm-pre-reloc;
46};
47
48&pmucru {
49	u-boot,dm-pre-reloc;
50};
51
52&cru {
53	u-boot,dm-pre-reloc;
54};
55
56&grf {
57	u-boot,dm-pre-reloc;
58};
59
60&cic {
61	u-boot,dm-pre-reloc;
62};
63
64&dmc {
65	u-boot,dm-pre-reloc;
66};
67
68&dwc3_typec0 {
69	u-boot,dm-pre-reloc;
70};
71
72&dwc3_typec1 {
73	u-boot,dm-pre-reloc;
74};
75
76&emmc_phy {
77	u-boot,dm-pre-reloc;
78};
79
80&u2phy0 {
81	u-boot,dm-pre-reloc;
82	status = "okay";
83};
84
85&u2phy0_otg {
86	u-boot,dm-pre-reloc;
87	status = "okay";
88};
89