1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 #include <bidram.h> 44 #include <sysmem.h> 45 46 /* 47 * Pointer to initial global data area 48 * 49 * Here we initialize it if needed. 50 */ 51 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 53 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 54 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 55 #else 56 DECLARE_GLOBAL_DATA_PTR; 57 #endif 58 59 /* 60 * TODO(sjg@chromium.org): IMO this code should be 61 * refactored to a single function, something like: 62 * 63 * void led_set_state(enum led_colour_t colour, int on); 64 */ 65 /************************************************************************ 66 * Coloured LED functionality 67 ************************************************************************ 68 * May be supplied by boards if desired 69 */ 70 __weak void coloured_LED_init(void) {} 71 __weak void red_led_on(void) {} 72 __weak void red_led_off(void) {} 73 __weak void green_led_on(void) {} 74 __weak void green_led_off(void) {} 75 __weak void yellow_led_on(void) {} 76 __weak void yellow_led_off(void) {} 77 __weak void blue_led_on(void) {} 78 __weak void blue_led_off(void) {} 79 80 /* 81 * Why is gd allocated a register? Prior to reloc it might be better to 82 * just pass it around to each function in this file? 83 * 84 * After reloc one could argue that it is hardly used and doesn't need 85 * to be in a register. Or if it is it should perhaps hold pointers to all 86 * global data for all modules, so that post-reloc we can avoid the massive 87 * literal pool we get on ARM. Or perhaps just encourage each module to use 88 * a structure... 89 */ 90 91 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 92 static int init_func_watchdog_init(void) 93 { 94 # if defined(CONFIG_HW_WATCHDOG) && \ 95 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 96 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 97 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 98 defined(CONFIG_IMX_WATCHDOG)) 99 hw_watchdog_init(); 100 puts(" Watchdog enabled\n"); 101 # endif 102 WATCHDOG_RESET(); 103 104 return 0; 105 } 106 107 int init_func_watchdog_reset(void) 108 { 109 WATCHDOG_RESET(); 110 111 return 0; 112 } 113 #endif /* CONFIG_WATCHDOG */ 114 115 __weak void board_add_ram_info(int use_default) 116 { 117 /* please define platform specific board_add_ram_info() */ 118 } 119 120 static int init_baud_rate(void) 121 { 122 if (gd && gd->serial.baudrate) 123 gd->baudrate = gd->serial.baudrate; 124 else 125 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 126 127 return 0; 128 } 129 130 static int display_text_info(void) 131 { 132 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 133 ulong bss_start, bss_end, text_base; 134 135 bss_start = (ulong)&__bss_start; 136 bss_end = (ulong)&__bss_end; 137 138 #ifdef CONFIG_SYS_TEXT_BASE 139 text_base = CONFIG_SYS_TEXT_BASE; 140 #else 141 text_base = CONFIG_SYS_MONITOR_BASE; 142 #endif 143 144 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 145 text_base, bss_start, bss_end); 146 #endif 147 148 return 0; 149 } 150 151 static int announce_serial(void) 152 { 153 if (gd && gd->serial.using_pre_serial) 154 printf("PreSerial: %d, ", gd->serial.id); 155 else 156 printf("Serial: "); 157 158 #ifdef CONFIG_DEBUG_UART_ALWAYS 159 printf("raw"); 160 #else 161 printf("console"); 162 #endif 163 printf(", 0x%lx\n", gd->serial.addr); 164 165 return 0; 166 } 167 168 static int announce_dram_init(void) 169 { 170 #ifndef CONFIG_SUPPORT_USBPLUG 171 puts("DRAM: "); 172 #endif 173 return 0; 174 } 175 176 static int show_dram_config(void) 177 { 178 unsigned long long size; 179 180 #ifdef CONFIG_NR_DRAM_BANKS 181 int i; 182 183 debug("\nRAM Configuration:\n"); 184 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 185 size += gd->bd->bi_dram[i].size; 186 debug("Bank #%d: %llx ", i, 187 (unsigned long long)(gd->bd->bi_dram[i].start)); 188 #ifdef DEBUG 189 print_size(gd->bd->bi_dram[i].size, "\n"); 190 #endif 191 } 192 debug("\nDRAM: "); 193 #else 194 size = gd->ram_size; 195 #endif 196 197 #ifdef CONFIG_BIDRAM 198 size += bidram_append_size(); 199 #endif 200 201 #ifndef CONFIG_SUPPORT_USBPLUG 202 print_size(size, ""); 203 board_add_ram_info(0); 204 putc('\n'); 205 #endif 206 return 0; 207 } 208 209 __weak int dram_init_banksize(void) 210 { 211 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 212 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 213 gd->bd->bi_dram[0].size = get_effective_memsize(); 214 #endif 215 216 return 0; 217 } 218 219 #if defined(CONFIG_SYS_I2C) 220 static int init_func_i2c(void) 221 { 222 puts("I2C: "); 223 #ifdef CONFIG_SYS_I2C 224 i2c_init_all(); 225 #else 226 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 227 #endif 228 puts("ready\n"); 229 return 0; 230 } 231 #endif 232 233 #if defined(CONFIG_HARD_SPI) 234 static int init_func_spi(void) 235 { 236 puts("SPI: "); 237 spi_init(); 238 puts("ready\n"); 239 return 0; 240 } 241 #endif 242 243 static int setup_mon_len(void) 244 { 245 #if defined(__ARM__) || defined(__MICROBLAZE__) 246 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 247 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 248 gd->mon_len = (ulong)&_end - (ulong)_init; 249 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 250 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 251 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 252 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 253 #elif defined(CONFIG_SYS_MONITOR_BASE) 254 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 255 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 256 #endif 257 return 0; 258 } 259 260 __weak int arch_cpu_init(void) 261 { 262 return 0; 263 } 264 265 __weak int mach_cpu_init(void) 266 { 267 return 0; 268 } 269 270 /* Get the top of usable RAM */ 271 __weak ulong board_get_usable_ram_top(ulong total_size) 272 { 273 #ifdef CONFIG_SYS_SDRAM_BASE 274 /* 275 * Detect whether we have so much RAM that it goes past the end of our 276 * 32-bit address space. If so, clip the usable RAM so it doesn't. 277 */ 278 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 279 /* 280 * Will wrap back to top of 32-bit space when reservations 281 * are made. 282 */ 283 return 0; 284 #endif 285 return gd->ram_top; 286 } 287 288 static int setup_dest_addr(void) 289 { 290 debug("Monitor len: %08lX\n", gd->mon_len); 291 /* 292 * Ram is setup, size stored in gd !! 293 */ 294 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 295 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 296 /* 297 * Subtract specified amount of memory to hide so that it won't 298 * get "touched" at all by U-Boot. By fixing up gd->ram_size 299 * the Linux kernel should now get passed the now "corrected" 300 * memory size and won't touch it either. This should work 301 * for arch/ppc and arch/powerpc. Only Linux board ports in 302 * arch/powerpc with bootwrapper support, that recalculate the 303 * memory size from the SDRAM controller setup will have to 304 * get fixed. 305 */ 306 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 307 #endif 308 #ifdef CONFIG_SYS_SDRAM_BASE 309 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 310 #endif 311 gd->ram_top += get_effective_memsize(); 312 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 313 gd->relocaddr = gd->ram_top; 314 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 315 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 316 /* 317 * We need to make sure the location we intend to put secondary core 318 * boot code is reserved and not used by any part of u-boot 319 */ 320 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 321 gd->relocaddr = determine_mp_bootpg(NULL); 322 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 323 } 324 #endif 325 return 0; 326 } 327 328 #ifdef CONFIG_PRAM 329 /* reserve protected RAM */ 330 static int reserve_pram(void) 331 { 332 ulong reg; 333 334 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 335 gd->relocaddr -= (reg << 10); /* size is in kB */ 336 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 337 gd->relocaddr); 338 return 0; 339 } 340 #endif /* CONFIG_PRAM */ 341 342 /* Round memory pointer down to next 4 kB limit */ 343 static int reserve_round_4k(void) 344 { 345 gd->relocaddr &= ~(4096 - 1); 346 return 0; 347 } 348 349 #ifdef CONFIG_ARM 350 __weak int reserve_mmu(void) 351 { 352 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 353 /* reserve TLB table */ 354 gd->arch.tlb_size = PGTABLE_SIZE; 355 gd->relocaddr -= gd->arch.tlb_size; 356 357 /* round down to next 64 kB limit */ 358 gd->relocaddr &= ~(0x10000 - 1); 359 360 gd->arch.tlb_addr = gd->relocaddr; 361 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 362 gd->arch.tlb_addr + gd->arch.tlb_size); 363 364 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 365 /* 366 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 367 * with location within secure ram. 368 */ 369 gd->arch.tlb_allocated = gd->arch.tlb_addr; 370 #endif 371 #endif 372 373 return 0; 374 } 375 #endif 376 377 static int reserve_video(void) 378 { 379 #ifdef CONFIG_DM_VIDEO 380 ulong addr; 381 int ret; 382 383 addr = gd->relocaddr; 384 ret = video_reserve(&addr); 385 if (ret) 386 return ret; 387 gd->relocaddr = addr; 388 #elif defined(CONFIG_LCD) 389 # ifdef CONFIG_FB_ADDR 390 gd->fb_base = CONFIG_FB_ADDR; 391 # else 392 /* reserve memory for LCD display (always full pages) */ 393 gd->relocaddr = lcd_setmem(gd->relocaddr); 394 gd->fb_base = gd->relocaddr; 395 # endif /* CONFIG_FB_ADDR */ 396 #elif defined(CONFIG_VIDEO) && \ 397 (!defined(CONFIG_PPC)) && \ 398 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 399 !defined(CONFIG_M68K) 400 /* reserve memory for video display (always full pages) */ 401 gd->relocaddr = video_setmem(gd->relocaddr); 402 gd->fb_base = gd->relocaddr; 403 #endif 404 405 return 0; 406 } 407 408 static int reserve_trace(void) 409 { 410 #ifdef CONFIG_TRACE 411 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 412 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 413 debug("Reserving %dk for trace data at: %08lx\n", 414 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 415 #endif 416 417 return 0; 418 } 419 420 static int reserve_uboot(void) 421 { 422 /* 423 * reserve memory for U-Boot code, data & bss 424 * round down to next 4 kB limit 425 */ 426 gd->relocaddr -= gd->mon_len; 427 gd->relocaddr &= ~(4096 - 1); 428 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 429 /* round down to next 64 kB limit so that IVPR stays aligned */ 430 gd->relocaddr &= ~(65536 - 1); 431 #endif 432 433 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 434 gd->relocaddr); 435 436 gd->start_addr_sp = gd->relocaddr; 437 438 return 0; 439 } 440 441 /* reserve memory for malloc() area */ 442 static int reserve_malloc(void) 443 { 444 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 445 debug("Reserving %dk for malloc() at: %08lx\n", 446 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 447 return 0; 448 } 449 450 #ifdef CONFIG_SYS_NONCACHED_MEMORY 451 static int reserve_noncached(void) 452 { 453 phys_addr_t start, end; 454 size_t size; 455 456 end = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 457 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 458 start = end - size; 459 gd->start_addr_sp = start; 460 debug("Reserving %zu for noncached_alloc() at: %08lx\n", 461 size, gd->start_addr_sp); 462 463 return 0; 464 } 465 #endif 466 467 /* (permanently) allocate a Board Info struct */ 468 static int reserve_board(void) 469 { 470 if (!gd->bd) { 471 gd->start_addr_sp -= sizeof(bd_t); 472 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 473 memset(gd->bd, '\0', sizeof(bd_t)); 474 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 475 sizeof(bd_t), gd->start_addr_sp); 476 } 477 return 0; 478 } 479 480 static int setup_machine(void) 481 { 482 #ifdef CONFIG_MACH_TYPE 483 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 484 #endif 485 return 0; 486 } 487 488 static int reserve_global_data(void) 489 { 490 gd->start_addr_sp -= sizeof(gd_t); 491 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 492 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 493 sizeof(gd_t), gd->start_addr_sp); 494 return 0; 495 } 496 497 static int reserve_fdt(void) 498 { 499 #ifndef CONFIG_OF_EMBED 500 /* 501 * If the device tree is sitting immediately above our image then we 502 * must relocate it. If it is embedded in the data section, then it 503 * will be relocated with other data. 504 */ 505 if (gd->fdt_blob) { 506 u32 extrasize = 0; 507 508 if (gd->fdt_blob_kern) 509 extrasize = fdt_totalsize(gd->fdt_blob_kern); 510 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + extrasize + 0x1000, 32); 511 gd->start_addr_sp -= gd->fdt_size; 512 513 /* 8-byte align */ 514 gd->start_addr_sp -= 8; 515 gd->start_addr_sp &= ~0x7; 516 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 517 518 if (gd->fdt_blob_kern) 519 gd->fdt_blob_kern = (ulong *)ALIGN((ulong)gd->new_fdt + 520 fdt_totalsize(gd->fdt_blob), 8); 521 debug("Reserving %lu Bytes for FDT at: %08lx\n", 522 gd->fdt_size, gd->start_addr_sp); 523 } 524 #endif 525 526 return 0; 527 } 528 529 static int reserve_bootstage(void) 530 { 531 #ifdef CONFIG_BOOTSTAGE 532 int size = bootstage_get_size(); 533 534 gd->start_addr_sp -= size; 535 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 536 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 537 gd->start_addr_sp); 538 #endif 539 540 return 0; 541 } 542 543 int arch_reserve_stacks(void) 544 { 545 return 0; 546 } 547 548 static int reserve_stacks(void) 549 { 550 /* make stack pointer 16-byte aligned */ 551 gd->start_addr_sp -= 16; 552 gd->start_addr_sp &= ~0xf; 553 554 /* 555 * let the architecture-specific code tailor gd->start_addr_sp and 556 * gd->irq_sp 557 */ 558 return arch_reserve_stacks(); 559 } 560 561 static int display_new_sp(void) 562 { 563 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 564 565 return 0; 566 } 567 568 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 569 defined(CONFIG_SH) 570 static int setup_board_part1(void) 571 { 572 bd_t *bd = gd->bd; 573 574 /* 575 * Save local variables to board info struct 576 */ 577 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 578 bd->bi_memsize = gd->ram_size; /* size in bytes */ 579 580 #ifdef CONFIG_SYS_SRAM_BASE 581 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 582 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 583 #endif 584 585 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 586 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 587 #endif 588 #if defined(CONFIG_M68K) 589 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 590 #endif 591 #if defined(CONFIG_MPC83xx) 592 bd->bi_immrbar = CONFIG_SYS_IMMR; 593 #endif 594 595 return 0; 596 } 597 #endif 598 599 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 600 static int setup_board_part2(void) 601 { 602 bd_t *bd = gd->bd; 603 604 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 605 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 606 #if defined(CONFIG_CPM2) 607 bd->bi_cpmfreq = gd->arch.cpm_clk; 608 bd->bi_brgfreq = gd->arch.brg_clk; 609 bd->bi_sccfreq = gd->arch.scc_clk; 610 bd->bi_vco = gd->arch.vco_out; 611 #endif /* CONFIG_CPM2 */ 612 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 613 bd->bi_pcifreq = gd->pci_clk; 614 #endif 615 #if defined(CONFIG_EXTRA_CLOCK) 616 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 617 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 618 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 619 #endif 620 621 return 0; 622 } 623 #endif 624 625 #ifdef CONFIG_POST 626 static int init_post(void) 627 { 628 post_bootmode_init(); 629 post_run(NULL, POST_ROM | post_bootmode_get(0)); 630 631 return 0; 632 } 633 #endif 634 635 static int reloc_fdt(void) 636 { 637 #ifndef CONFIG_OF_EMBED 638 if (gd->flags & GD_FLG_SKIP_RELOC) 639 return 0; 640 if (gd->new_fdt) { 641 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 642 gd->fdt_blob = gd->new_fdt; 643 #ifdef CONFIG_USING_KERNEL_DTB 644 gd->ufdt_blob = gd->new_fdt; 645 #endif 646 } 647 #endif 648 649 return 0; 650 } 651 652 static int reloc_bootstage(void) 653 { 654 #ifdef CONFIG_BOOTSTAGE 655 if (gd->flags & GD_FLG_SKIP_RELOC) 656 return 0; 657 if (gd->new_bootstage) { 658 int size = bootstage_get_size(); 659 660 debug("Copying bootstage from %p to %p, size %x\n", 661 gd->bootstage, gd->new_bootstage, size); 662 memcpy(gd->new_bootstage, gd->bootstage, size); 663 gd->bootstage = gd->new_bootstage; 664 } 665 #endif 666 667 return 0; 668 } 669 670 static int setup_reloc(void) 671 { 672 if (gd->flags & GD_FLG_SKIP_RELOC) { 673 debug("Skipping relocation due to flag\n"); 674 return 0; 675 } 676 677 #ifndef CONFIG_SKIP_RELOCATE_UBOOT 678 #ifdef CONFIG_SYS_TEXT_BASE 679 #ifdef ARM 680 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 681 #elif defined(CONFIG_M68K) 682 /* 683 * On all ColdFire arch cpu, monitor code starts always 684 * just after the default vector table location, so at 0x400 685 */ 686 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 687 #else 688 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 689 #endif 690 #endif 691 692 #else 693 gd->reloc_off = 0; 694 #endif 695 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 696 697 #ifndef CONFIG_SUPPORT_USBPLUG 698 printf("Relocation Offset: %08lx\n", gd->reloc_off); 699 700 printf("Relocation fdt: %08lx - %08lx", (ulong)gd->new_fdt, 701 (ulong)gd->new_fdt + fdt_totalsize(gd->fdt_blob)); 702 if (gd->fdt_blob_kern) { 703 printf(", kfdt: %08lx - %08lx", (ulong)gd->fdt_blob_kern, 704 (ulong)gd->fdt_blob_kern + fdt_totalsize(gd->fdt_blob_kern)); 705 } 706 puts("\n"); 707 #endif 708 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 709 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 710 gd->start_addr_sp); 711 712 return 0; 713 } 714 715 #ifdef CONFIG_OF_BOARD_FIXUP 716 static int fix_fdt(void) 717 { 718 return board_fix_fdt((void *)gd->fdt_blob); 719 } 720 #endif 721 722 /* ARM calls relocate_code from its crt0.S */ 723 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 724 !CONFIG_IS_ENABLED(X86_64) 725 726 static int jump_to_copy(void) 727 { 728 if (gd->flags & GD_FLG_SKIP_RELOC) 729 return 0; 730 /* 731 * x86 is special, but in a nice way. It uses a trampoline which 732 * enables the dcache if possible. 733 * 734 * For now, other archs use relocate_code(), which is implemented 735 * similarly for all archs. When we do generic relocation, hopefully 736 * we can make all archs enable the dcache prior to relocation. 737 */ 738 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 739 /* 740 * SDRAM and console are now initialised. The final stack can now 741 * be setup in SDRAM. Code execution will continue in Flash, but 742 * with the stack in SDRAM and Global Data in temporary memory 743 * (CPU cache) 744 */ 745 arch_setup_gd(gd->new_gd); 746 board_init_f_r_trampoline(gd->start_addr_sp); 747 #else 748 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 749 #endif 750 751 return 0; 752 } 753 #endif 754 755 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 756 static int initf_bootstage(void) 757 { 758 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 759 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 760 int ret; 761 762 ret = bootstage_init(!from_spl); 763 if (ret) 764 return ret; 765 if (from_spl) { 766 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 767 CONFIG_BOOTSTAGE_STASH_SIZE); 768 769 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 770 if (ret && ret != -ENOENT) { 771 debug("Failed to unstash bootstage: err=%d\n", ret); 772 return ret; 773 } 774 } 775 776 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 777 778 return 0; 779 } 780 781 static int initf_console_record(void) 782 { 783 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 784 return console_record_init(); 785 #else 786 return 0; 787 #endif 788 } 789 790 static int initf_dm(void) 791 { 792 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 793 int ret; 794 795 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 796 ret = dm_init_and_scan(true); 797 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 798 if (ret) 799 return ret; 800 #endif 801 #ifdef CONFIG_TIMER_EARLY 802 ret = dm_timer_init(); 803 if (ret) 804 return ret; 805 #endif 806 807 return 0; 808 } 809 810 /* Architecture-specific memory reservation */ 811 __weak int reserve_arch(void) 812 { 813 return 0; 814 } 815 816 __weak int arch_cpu_init_dm(void) 817 { 818 return 0; 819 } 820 821 static const init_fnc_t init_sequence_f[] = { 822 setup_mon_len, 823 #ifdef CONFIG_OF_CONTROL 824 fdtdec_setup, 825 #endif 826 #ifdef CONFIG_TRACE 827 trace_early_init, 828 #endif 829 initf_malloc, 830 log_init, 831 initf_bootstage, /* uses its own timer, so does not need DM */ 832 initf_console_record, 833 #if defined(CONFIG_HAVE_FSP) 834 arch_fsp_init, 835 #endif 836 arch_cpu_init, /* basic arch cpu dependent setup */ 837 mach_cpu_init, /* SoC/machine dependent CPU setup */ 838 initf_dm, 839 arch_cpu_init_dm, 840 #if defined(CONFIG_BOARD_EARLY_INIT_F) 841 board_early_init_f, 842 #endif 843 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 844 /* get CPU and bus clocks according to the environment variable */ 845 get_clocks, /* get CPU and bus clocks (etc.) */ 846 #endif 847 #if !defined(CONFIG_M68K) 848 timer_init, /* initialize timer */ 849 #endif 850 #if defined(CONFIG_BOARD_POSTCLK_INIT) 851 board_postclk_init, 852 #endif 853 env_init, /* initialize environment */ 854 init_baud_rate, /* initialze baudrate settings */ 855 serial_init, /* serial communications setup */ 856 console_init_f, /* stage 1 init of console */ 857 display_options, /* say that we are here */ 858 display_text_info, /* show debugging info if required */ 859 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 860 defined(CONFIG_X86) 861 checkcpu, 862 #endif 863 #if defined(CONFIG_DISPLAY_CPUINFO) 864 print_cpuinfo, /* display cpu info (and speed) */ 865 #endif 866 #if defined(CONFIG_DTB_RESELECT) 867 embedded_dtb_select, 868 #endif 869 #if defined(CONFIG_DISPLAY_BOARDINFO) 870 show_board_info, 871 #endif 872 INIT_FUNC_WATCHDOG_INIT 873 #if defined(CONFIG_MISC_INIT_F) 874 misc_init_f, 875 #endif 876 INIT_FUNC_WATCHDOG_RESET 877 #if defined(CONFIG_SYS_I2C) 878 init_func_i2c, 879 #endif 880 #if defined(CONFIG_HARD_SPI) 881 init_func_spi, 882 #endif 883 announce_serial, 884 885 announce_dram_init, 886 dram_init, /* configure available RAM banks */ 887 #ifdef CONFIG_POST 888 post_init_f, 889 #endif 890 INIT_FUNC_WATCHDOG_RESET 891 #if defined(CONFIG_SYS_DRAM_TEST) 892 testdram, 893 #endif /* CONFIG_SYS_DRAM_TEST */ 894 INIT_FUNC_WATCHDOG_RESET 895 896 #ifdef CONFIG_POST 897 init_post, 898 #endif 899 INIT_FUNC_WATCHDOG_RESET 900 /* 901 * Now that we have DRAM mapped and working, we can 902 * relocate the code and continue running from DRAM. 903 * 904 * Reserve memory at end of RAM for (top down in that order): 905 * - area that won't get touched by U-Boot and Linux (optional) 906 * - kernel log buffer 907 * - protected RAM 908 * - LCD framebuffer 909 * - monitor code 910 * - board info struct 911 */ 912 setup_dest_addr, 913 #ifdef CONFIG_PRAM 914 reserve_pram, 915 #endif 916 reserve_round_4k, 917 #ifdef CONFIG_ARM 918 reserve_mmu, 919 #endif 920 reserve_video, 921 reserve_trace, 922 reserve_uboot, 923 reserve_malloc, 924 #ifdef CONFIG_SYS_NONCACHED_MEMORY 925 reserve_noncached, 926 #endif 927 reserve_board, 928 setup_machine, 929 reserve_global_data, 930 reserve_fdt, 931 reserve_bootstage, 932 reserve_arch, 933 reserve_stacks, 934 dram_init_banksize, 935 show_dram_config, 936 #ifdef CONFIG_SYSMEM 937 sysmem_init, /* Validate above reserve memory */ 938 #endif 939 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 940 defined(CONFIG_SH) 941 setup_board_part1, 942 #endif 943 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 944 INIT_FUNC_WATCHDOG_RESET 945 setup_board_part2, 946 #endif 947 display_new_sp, 948 #ifdef CONFIG_OF_BOARD_FIXUP 949 fix_fdt, 950 #endif 951 INIT_FUNC_WATCHDOG_RESET 952 reloc_fdt, 953 reloc_bootstage, 954 setup_reloc, 955 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 956 copy_uboot_to_ram, 957 do_elf_reloc_fixups, 958 clear_bss, 959 #endif 960 #if defined(CONFIG_XTENSA) 961 clear_bss, 962 #endif 963 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 964 !CONFIG_IS_ENABLED(X86_64) 965 jump_to_copy, 966 #endif 967 NULL, 968 }; 969 970 void board_init_f(ulong boot_flags) 971 { 972 gd->flags = boot_flags; 973 gd->have_console = 0; 974 975 if (initcall_run_list(init_sequence_f)) 976 hang(); 977 978 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 979 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 980 /* NOTREACHED - jump_to_copy() does not return */ 981 hang(); 982 #endif 983 } 984 985 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 986 /* 987 * For now this code is only used on x86. 988 * 989 * init_sequence_f_r is the list of init functions which are run when 990 * U-Boot is executing from Flash with a semi-limited 'C' environment. 991 * The following limitations must be considered when implementing an 992 * '_f_r' function: 993 * - 'static' variables are read-only 994 * - Global Data (gd->xxx) is read/write 995 * 996 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 997 * supported). It _should_, if possible, copy global data to RAM and 998 * initialise the CPU caches (to speed up the relocation process) 999 * 1000 * NOTE: At present only x86 uses this route, but it is intended that 1001 * all archs will move to this when generic relocation is implemented. 1002 */ 1003 static const init_fnc_t init_sequence_f_r[] = { 1004 #if !CONFIG_IS_ENABLED(X86_64) 1005 init_cache_f_r, 1006 #endif 1007 1008 NULL, 1009 }; 1010 1011 void board_init_f_r(void) 1012 { 1013 if (initcall_run_list(init_sequence_f_r)) 1014 hang(); 1015 1016 /* 1017 * The pre-relocation drivers may be using memory that has now gone 1018 * away. Mark serial as unavailable - this will fall back to the debug 1019 * UART if available. 1020 * 1021 * Do the same with log drivers since the memory may not be available. 1022 */ 1023 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1024 #ifdef CONFIG_TIMER 1025 gd->timer = NULL; 1026 #endif 1027 1028 /* 1029 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1030 * Transfer execution from Flash to RAM by calculating the address 1031 * of the in-RAM copy of board_init_r() and calling it 1032 */ 1033 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1034 1035 /* NOTREACHED - board_init_r() does not return */ 1036 hang(); 1037 } 1038 #endif /* CONFIG_X86 */ 1039