1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci: psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 amba { 160 compatible = "arm,amba-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 interrupt-parent = <&gic>; 164 ranges; 165 166 pdma: pdma@20078000 { 167 compatible = "arm,pl330", "arm,primecell"; 168 reg = <0x20078000 0x4000>; 169 arm,pl330-broken-no-flushp;//2 170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 172 #dma-cells = <1>; 173 clocks = <&cru ACLK_DMAC>; 174 clock-names = "apb_pclk"; 175 }; 176 }; 177 178 xin24m: xin24m { 179 compatible = "fixed-clock"; 180 clock-frequency = <24000000>; 181 clock-output-names = "xin24m"; 182 #clock-cells = <0>; 183 }; 184 185 xin12m: xin12m { 186 compatible = "fixed-clock"; 187 clocks = <&xin24m>; 188 clock-frequency = <12000000>; 189 clock-output-names = "xin12m"; 190 #clock-cells = <0>; 191 }; 192 193 194 timer { 195 compatible = "arm,armv7-timer"; 196 arm,cpu-registers-not-fw-configured; 197 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 198 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 199 clock-frequency = <24000000>; 200 }; 201 202 timer@20044000 { 203 compatible = "arm,armv7-timer"; 204 reg = <0x20044000 0xb8>; 205 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 206 rockchip,broadcast = <1>; 207 }; 208 209 watchdog: wdt@2004c000 { 210 compatible = "rockchip,watch dog"; 211 reg = <0x2004c000 0x100>; 212 clock-names = "pclk_wdt"; 213 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 214 rockchip,irq = <1>; 215 rockchip,timeout = <60>; 216 rockchip,atboot = <1>; 217 rockchip,debug = <0>; 218 }; 219 220 reset: reset@20000110 { 221 compatible = "rockchip,reset"; 222 reg = <0x20000110 0x24>; 223 #reset-cells = <1>; 224 }; 225 nandc: nandc@10500000 { 226 compatible = "rockchip,rk-nandc"; 227 reg = <0x10500000 0x4000>; 228 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 229 nandc_id = <0>; 230 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 231 clock-names = "clk_nandc", "hclk_nandc"; 232 status = "disabled"; 233 }; 234 235 dmc: dmc@20004000 { 236 compatible = "rockchip,rk3128-dmc", "syscon"; 237 reg = <0x0 0x20004000 0x0 0x1000>; 238 }; 239 240 cru: clock-controller@20000000 { 241 compatible = "rockchip,rk3128-cru"; 242 reg = <0x20000000 0x1000>; 243 rockchip,grf = <&grf>; 244 #clock-cells = <1>; 245 #reset-cells = <1>; 246 assigned-clocks = <&cru PLL_GPLL>; 247 assigned-clock-rates = <594000000>; 248 }; 249 250 uart0: serial0@20060000 { 251 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 252 reg = <0x20060000 0x100>; 253 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 254 reg-shift = <2>; 255 reg-io-width = <4>; 256 clock-frequency = <24000000>; 257 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 258 clock-names = "baudclk", "apb_pclk"; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 261 dmas = <&pdma 2>, <&pdma 3>; 262 #dma-cells = <2>; 263 }; 264 265 uart1: serial1@20064000 { 266 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 267 reg = <0x20064000 0x100>; 268 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 269 reg-shift = <2>; 270 reg-io-width = <4>; 271 clock-frequency = <24000000>; 272 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 273 clock-names = "baudclk", "apb_pclk"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&uart1_xfer>; 276 dmas = <&pdma 4>, <&pdma 5>; 277 #dma-cells = <2>; 278 }; 279 280 uart2: serial2@20068000 { 281 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 282 reg = <0x20068000 0x100>; 283 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 284 reg-shift = <2>; 285 reg-io-width = <4>; 286 clock-frequency = <24000000>; 287 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 288 clock-names = "baudclk", "apb_pclk"; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&uart2_xfer>; 291 dmas = <&pdma 6>, <&pdma 7>; 292 #dma-cells = <2>; 293 }; 294 295 saradc: saradc@2006c000 { 296 compatible = "rockchip,saradc"; 297 reg = <0x2006c000 0x100>; 298 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 299 #io-channel-cells = <1>; 300 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 301 clock-names = "saradc", "apb_pclk"; 302 resets = <&cru SRST_SARADC>; 303 reset-names = "saradc-apb"; 304 status = "disabled"; 305 }; 306 307 pwm0: pwm0@20050000 { 308 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 309 reg = <0x20050000 0x10>; 310 #pwm-cells = <3>; 311 pinctrl-names = "active"; 312 pinctrl-0 = <&pwm0_pin>; 313 clocks = <&cru PCLK_PWM>; 314 clock-names = "pwm"; 315 }; 316 317 pwm1: pwm1@20050010 { 318 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 319 reg = <0x20050010 0x10>; 320 #pwm-cells = <2>; 321 pinctrl-names = "active"; 322 pinctrl-0 = <&pwm1_pin>; 323 clocks = <&cru PCLK_PWM>; 324 clock-names = "pwm"; 325 }; 326 327 pwm2: pwm2@20050020 { 328 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 329 reg = <0x20050020 0x10>; 330 #pwm-cells = <2>; 331 pinctrl-names = "active"; 332 pinctrl-0 = <&pwm2_pin>; 333 clocks = <&cru PCLK_PWM>; 334 clock-names = "pwm"; 335 }; 336 337 pwm3: pwm3@20050030 { 338 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 339 reg = <0x20050030 0x10>; 340 #pwm-cells = <2>; 341 pinctrl-names = "active"; 342 pinctrl-0 = <&pwm3_pin>; 343 clocks = <&cru PCLK_PWM>; 344 clock-names = "pwm"; 345 }; 346 347 sram: sram@10080400 { 348 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 349 reg = <0x10080400 0x1C00>; 350 map-exec; 351 map-cacheable; 352 }; 353 354 pmu: syscon@100a0000 { 355 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 356 reg = <0x100a0000 0x1000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 }; 360 361 vop: vop@1010e000 { 362 compatible = "rockchip,rk3126-vop"; 363 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 364 reg-names = "regs", "gamma_lut"; 365 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>; 367 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 368 status = "disabled"; 369 370 vop_out: port { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 vop_out_lvds: endpoint@0 { 375 reg = <0>; 376 remote-endpoint = <&lvds_in_vop>; 377 }; 378 379 vop_out_dsi: endpoint@1 { 380 reg = <1>; 381 remote-endpoint = <&dsi_in_vop>; 382 }; 383 384 vop_out_rgb: endpoint@2 { 385 reg = <2>; 386 remote-endpoint = <&rgb_in_vop>; 387 }; 388 }; 389 }; 390 391 dsi: dsi@10110000 { 392 compatible = "rockchip,rk3128-mipi-dsi"; 393 reg = <0x10110000 0x4000>; 394 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>; 396 clock-names = "pclk", "h2p", "hs_clk"; 397 resets = <&cru SRST_VIO_MIPI_DSI>; 398 reset-names = "apb"; 399 phys = <&video_phy>; 400 phy-names = "mipi_dphy"; 401 rockchip,grf = <&grf>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 406 ports { 407 port { 408 dsi_in_vop: endpoint { 409 remote-endpoint = <&vop_out_dsi>; 410 }; 411 }; 412 }; 413 }; 414 415 display_subsystem: display-subsystem { 416 compatible = "rockchip,display-subsystem"; 417 ports = <&vop_out>; 418 419 route { 420 route_lvds: route-lvds { 421 logo,uboot = "logo.bmp"; 422 logo,kernel = "logo_kernel.bmp"; 423 logo,mode = "fullscreen"; 424 charge_logo,mode = "center"; 425 connect = <&vop_out_lvds>; 426 }; 427 428 route_dsi: route-dsi { 429 logo,uboot = "logo.bmp"; 430 logo,kernel = "logo_kernel.bmp"; 431 logo,mode = "fullscreen"; 432 charge_logo,mode = "center"; 433 connect = <&vop_out_dsi>; 434 }; 435 }; 436 }; 437 438 gic: interrupt-controller@10139000 { 439 compatible = "arm,gic-400"; 440 interrupt-controller; 441 #interrupt-cells = <3>; 442 #address-cells = <0>; 443 reg = <0x10139000 0x1000>, 444 <0x1013a000 0x1000>, 445 <0x1013c000 0x2000>, 446 <0x1013e000 0x2000>; 447 interrupts = <GIC_PPI 9 0xf04>; 448 }; 449 450 usb_otg: usb@10180000 { 451 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 452 "snps,dwc2"; 453 reg = <0x10180000 0x40000>; 454 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 455 dr_mode = "otg"; 456 g-use-dma; 457 hnp-srp-disable; 458 phys = <&u2phy_otg>; 459 phy-names = "usb"; 460 status = "disabled"; 461 }; 462 463 usb_host_ehci: usb@101c0000 { 464 compatible = "generic-ehci"; 465 reg = <0x101c0000 0x20000>; 466 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 467 phys = <&u2phy_host>; 468 phy-names = "usb"; 469 status = "disabled"; 470 }; 471 472 usb_host_ohci: usb@101e0000 { 473 compatible = "generic-ohci"; 474 reg = <0x101e0000 0x20000>; 475 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 476 phys = <&u2phy_host>; 477 phy-names = "usb"; 478 status = "disabled"; 479 }; 480 481 sdmmc: dwmmc@10214000 { 482 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 483 reg = <0x10214000 0x4000>; 484 max-frequency = <150000000>; 485 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 487 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 488 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 489 fifo-depth = <0x100>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 492 bus-width = <4>; 493 status = "disabled"; 494 }; 495 496 emmc: dwmmc@1021c000 { 497 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 498 reg = <0x1021c000 0x4000>; 499 max-frequency = <150000000>; 500 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 502 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 503 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 504 bus-width = <8>; 505 default-sample-phase = <158>; 506 num-slots = <1>; 507 fifo-depth = <0x100>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 510 resets = <&cru SRST_EMMC>; 511 reset-names = "reset"; 512 status = "disabled"; 513 }; 514 515 video_phy: video-phy@20038000 { 516 compatible = "rockchip,rk3128-video-phy"; 517 reg = <0x20038000 0x4000>, <0x10110000 0x4000>; 518 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, 519 <&cru PCLK_MIPI>; 520 clock-names = "ref", "pclk_phy", "pclk_host"; 521 #clock-cells = <0>; 522 resets = <&cru SRST_MIPIPHY_P>; 523 reset-names = "rst"; 524 #phy-cells = <0>; 525 status = "disabled"; 526 }; 527 528 i2c0: i2c0@20072000 { 529 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 530 reg = <0x20072000 0x1000>; 531 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 clock-names = "i2c"; 535 clocks = <&cru PCLK_I2C0>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&i2c0_xfer>; 538 }; 539 540 i2c1: i2c1@20056000 { 541 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 542 reg = <0x20056000 0x1000>; 543 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clock-names = "i2c"; 547 clocks = <&cru PCLK_I2C1>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2c1_xfer>; 550 }; 551 552 i2c2: i2c2@2005a000 { 553 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 554 reg = <0x2005a000 0x1000>; 555 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clock-names = "i2c"; 559 clocks = <&cru PCLK_I2C2>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c2_xfer>; 562 }; 563 564 i2c3: i2c3@2005e000 { 565 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 566 reg = <0x2005e000 0x1000>; 567 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clock-names = "i2c"; 571 clocks = <&cru PCLK_I2C3>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c3_xfer>; 574 }; 575 576 spi0: spi@20074000 { 577 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 578 reg = <0x20074000 0x1000>; 579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 582 clock-names = "spiclk", "apb_pclk"; 583 dmas = <&pdma 8>, <&pdma 9>; 584 dma-names = "tx", "rx"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 grf: syscon@20008000 { 591 compatible = "rockchip,rk3128-grf", "syscon"; 592 reg = <0x20008000 0x1000>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 596 lvds: lvds { 597 compatible = "rockchip,rk3126-lvds"; 598 phys = <&video_phy>; 599 phy-names = "phy"; 600 status = "disabled"; 601 602 ports { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 606 port@0 { 607 reg = <0>; 608 609 lvds_in_vop: endpoint { 610 remote-endpoint = <&vop_out_lvds>; 611 }; 612 }; 613 }; 614 }; 615 616 rgb: rgb { 617 compatible = "rockchip,rk3128-rgb"; 618 phys = <&video_phy>; 619 phy-names = "phy"; 620 pinctrl-names = "default", "sleep"; 621 pinctrl-0 = <&lcdc_rgb_pins>; 622 pinctrl-1 = <&lcdc_sleep_pins>; 623 status = "disabled"; 624 625 ports { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 629 port@0 { 630 reg = <0>; 631 632 rgb_in_vop: endpoint { 633 remote-endpoint = <&vop_out_rgb>; 634 }; 635 }; 636 }; 637 }; 638 639 u2phy: usb2-phy@17c { 640 compatible = "rockchip,rk3128-usb2phy"; 641 reg = <0x017c 0x0c>; 642 clocks = <&cru SCLK_OTGPHY0>; 643 clock-names = "phyclk"; 644 #clock-cells = <0>; 645 clock-output-names = "usb480m_phy"; 646 assigned-clocks = <&cru SCLK_USB480M>; 647 assigned-clock-parents = <&u2phy>; 648 status = "disabled"; 649 650 u2phy_otg: otg-port { 651 #phy-cells = <0>; 652 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "otg-bvalid", "otg-id", 656 "linestate"; 657 status = "disabled"; 658 }; 659 660 u2phy_host: host-port { 661 #phy-cells = <0>; 662 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 663 interrupt-names = "linestate"; 664 status = "disabled"; 665 }; 666 }; 667 }; 668 669 pinctrl: pinctrl@20008000 { 670 compatible = "rockchip,rk3128-pinctrl"; 671 reg = <0x20008000 0xA8>, 672 <0x200080A8 0x4C>, 673 <0x20008118 0x20>, 674 <0x20008100 0x04>; 675 reg-names = "base", "mux", "pull", "drv"; 676 rockchip,grf = <&grf>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 ranges; 680 681 gpio0: gpio0@2007c000 { 682 compatible = "rockchip,gpio-bank"; 683 reg = <0x2007c000 0x100>; 684 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cru PCLK_GPIO0>; 686 gpio-controller; 687 #gpio-cells = <2>; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 692 gpio1: gpio1@20080000 { 693 compatible = "rockchip,gpio-bank"; 694 reg = <0x20080000 0x100>; 695 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cru PCLK_GPIO1>; 697 gpio-controller; 698 #gpio-cells = <2>; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 }; 702 703 gpio2: gpio2@20084000 { 704 compatible = "rockchip,gpio-bank"; 705 reg = <0x20084000 0x100>; 706 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cru PCLK_GPIO2>; 708 gpio-controller; 709 #gpio-cells = <2>; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 714 gpio3: gpio2@20088000 { 715 compatible = "rockchip,gpio-bank"; 716 reg = <0x20088000 0x100>; 717 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cru PCLK_GPIO3>; 719 gpio-controller; 720 #gpio-cells = <2>; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 725 pcfg_pull_default: pcfg_pull_default { 726 bias-pull-pin-default; 727 }; 728 729 pcfg_pull_none: pcfg-pull-none { 730 bias-disable; 731 }; 732 733 emmc { 734 emmc_clk: emmc-clk { 735 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 736 }; 737 738 emmc_cmd: emmc-cmd { 739 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 740 }; 741 742 emmc_cmd1: emmc-cmd1 { 743 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 744 }; 745 746 emmc_pwr: emmc-pwr { 747 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 748 }; 749 750 emmc_bus1: emmc-bus1 { 751 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 752 }; 753 754 emmc_bus4: emmc-bus4 { 755 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 756 <1 RK_PD1 2 &pcfg_pull_default>, 757 <1 RK_PD2 2 &pcfg_pull_default>, 758 <1 RK_PD3 2 &pcfg_pull_default>; 759 }; 760 761 emmc_bus8: emmc-bus8 { 762 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 763 <1 RK_PD1 2 &pcfg_pull_default>, 764 <1 RK_PD2 2 &pcfg_pull_default>, 765 <1 RK_PD3 2 &pcfg_pull_default>, 766 <1 RK_PD4 2 &pcfg_pull_default>, 767 <1 RK_PD5 2 &pcfg_pull_default>, 768 <1 RK_PD6 2 &pcfg_pull_default>, 769 <1 RK_PD7 2 &pcfg_pull_default>; 770 }; 771 }; 772 773 i2c0 { 774 i2c0_xfer: i2c0-xfer { 775 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 776 <0 RK_PA1 1 &pcfg_pull_none>; 777 }; 778 }; 779 780 i2c1 { 781 i2c1_xfer: i2c1-xfer { 782 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 783 <0 RK_PA3 1 &pcfg_pull_none>; 784 }; 785 }; 786 787 i2c2 { 788 i2c2_xfer: i2c2-xfer { 789 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 790 <2 RK_PC5 3 &pcfg_pull_none>; 791 }; 792 }; 793 794 i2c3 { 795 i2c3_xfer: i2c3-xfer { 796 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 797 <0 RK_PA7 1 &pcfg_pull_none>; 798 }; 799 }; 800 801 lcdc { 802 lcdc_rgb_pins: lcdc-rgb-pins { 803 rockchip,pins = 804 <2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */ 805 <2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */ 806 <2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */ 807 <2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */ 808 <2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */ 809 <2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */ 810 <2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */ 811 <2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */ 812 <2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */ 813 <2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */ 814 <2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */ 815 <2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */ 816 <2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */ 817 <2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */ 818 <2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */ 819 <2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */ 820 <2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */ 821 <2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */ 822 }; 823 824 lcdc_sleep_pins: lcdc-sleep-pins { 825 rockchip,pins = 826 <2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */ 827 <2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */ 828 <2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */ 829 <2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */ 830 <2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */ 831 <2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */ 832 <2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */ 833 <2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */ 834 <2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */ 835 <2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */ 836 <2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */ 837 <2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */ 838 <2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */ 839 <2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */ 840 <2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */ 841 <2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */ 842 <2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */ 843 <2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */ 844 }; 845 }; 846 847 uart0 { 848 uart0_xfer: uart0-xfer { 849 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 850 <2 RK_PD3 2 &pcfg_pull_none>; 851 }; 852 853 uart0_cts: uart0-cts { 854 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 855 }; 856 857 uart0_rts: uart0-rts { 858 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 859 }; 860 }; 861 862 uart1 { 863 uart1_xfer: uart1-xfer { 864 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 865 <1 RK_PB2 2 &pcfg_pull_default>; 866 }; 867 868 uart1_cts: uart1-cts { 869 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 870 }; 871 872 uart1_rts: uart1-rts { 873 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 874 }; 875 }; 876 877 uart2 { 878 uart2_xfer: uart2-xfer { 879 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 880 <1 RK_PC3 2 &pcfg_pull_none>; 881 }; 882 883 uart2_cts: uart2-cts { 884 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 885 }; 886 887 uart2_rts: uart2-rts { 888 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 889 }; 890 }; 891 892 sdmmc { 893 sdmmc_clk: sdmmc-clk { 894 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 895 }; 896 897 sdmmc_cmd: sdmmc-cmd { 898 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 899 }; 900 901 sdmmc_wp: sdmmc-wp { 902 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 903 }; 904 905 sdmmc_pwren: sdmmc-pwren { 906 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 907 }; 908 909 sdmmc_bus4: sdmmc-bus4 { 910 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 911 <1 RK_PC3 1 &pcfg_pull_default>, 912 <1 RK_PC4 1 &pcfg_pull_default>, 913 <1 RK_PC5 1 &pcfg_pull_default>; 914 }; 915 }; 916 917 sdio { 918 sdio_clk: sdio-clk { 919 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 920 }; 921 922 sdio_cmd: sdio-cmd { 923 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 924 }; 925 926 sdio_pwren: sdio-pwren { 927 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 928 }; 929 930 sdio_bus4: sdio-bus4 { 931 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 932 <1 RK_PA2 2 &pcfg_pull_default>, 933 <1 RK_PA4 2 &pcfg_pull_default>, 934 <1 RK_PA5 2 &pcfg_pull_default>; 935 }; 936 }; 937 938 hdmi { 939 hdmii2c_xfer: hdmii2c-xfer { 940 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 941 <0 RK_PA7 2 &pcfg_pull_none>; 942 }; 943 }; 944 945 i2s { 946 i2s_bus: i2s-bus { 947 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 948 <0 RK_PB1 1 &pcfg_pull_none>, 949 <0 RK_PB3 1 &pcfg_pull_none>, 950 <0 RK_PB4 1 &pcfg_pull_none>, 951 <0 RK_PB5 1 &pcfg_pull_none>, 952 <0 RK_PB6 1 &pcfg_pull_none>; 953 }; 954 955 i2s1_bus: i2s1-bus { 956 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 957 <1 RK_PA1 1 &pcfg_pull_none>, 958 <1 RK_PA2 1 &pcfg_pull_none>, 959 <1 RK_PA3 1 &pcfg_pull_none>, 960 <1 RK_PA4 1 &pcfg_pull_none>, 961 <1 RK_PA5 1 &pcfg_pull_none>; 962 }; 963 }; 964 965 pwm0 { 966 pwm0_pin: pwm0-pin { 967 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 968 }; 969 }; 970 971 pwm1 { 972 pwm1_pin: pwm1-pin { 973 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 974 }; 975 }; 976 977 pwm2 { 978 pwm2_pin: pwm2-pin { 979 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 980 }; 981 }; 982 983 pwm3 { 984 pwm3_pin: pwm3-pin { 985 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 986 }; 987 }; 988 989 gmac { 990 rgmii_pins: rgmii-pins { 991 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 992 <2 RK_PB1 3 &pcfg_pull_default>, 993 <2 RK_PB3 3 &pcfg_pull_default>, 994 <2 RK_PB4 3 &pcfg_pull_default>, 995 <2 RK_PB5 3 &pcfg_pull_default>, 996 <2 RK_PB6 3 &pcfg_pull_default>, 997 <2 RK_PC0 3 &pcfg_pull_default>, 998 <2 RK_PC1 3 &pcfg_pull_default>, 999 <2 RK_PC2 3 &pcfg_pull_default>, 1000 <2 RK_PC3 3 &pcfg_pull_default>, 1001 <2 RK_PD1 3 &pcfg_pull_default>, 1002 <2 RK_PC4 4 &pcfg_pull_default>, 1003 <2 RK_PC5 4 &pcfg_pull_default>, 1004 <2 RK_PC6 4 &pcfg_pull_default>, 1005 <2 RK_PC7 4 &pcfg_pull_default>; 1006 }; 1007 1008 rmii_pins: rmii-pins { 1009 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1010 <2 RK_PB4 3 &pcfg_pull_default>, 1011 <2 RK_PB5 3 &pcfg_pull_default>, 1012 <2 RK_PB6 3 &pcfg_pull_default>, 1013 <2 RK_PB7 3 &pcfg_pull_default>, 1014 <2 RK_PC0 3 &pcfg_pull_default>, 1015 <2 RK_PC1 3 &pcfg_pull_default>, 1016 <2 RK_PC3 3 &pcfg_pull_default>, 1017 <2 RK_PC4 3 &pcfg_pull_default>, 1018 <2 RK_PD1 3 &pcfg_pull_default>; 1019 }; 1020 }; 1021 1022 spdif { 1023 spdif_tx: spdif-tx { 1024 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1025 }; 1026 }; 1027 1028 spi { 1029 spi0_clk: spi0-clk { 1030 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1031 }; 1032 1033 spi0_cs0: spi0-cs0 { 1034 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1035 }; 1036 1037 spi0_tx: spi0-tx { 1038 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1039 }; 1040 1041 spi0_rx: spi0-rx { 1042 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1043 }; 1044 1045 spi0_cs1: spi0-cs1 { 1046 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1047 }; 1048 1049 spi1_clk: spi1-clk { 1050 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1051 }; 1052 1053 spi1_cs0: spi1-cs0 { 1054 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1055 }; 1056 1057 spi1_tx: spi1-tx { 1058 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1059 }; 1060 1061 spi1_rx: spi1-rx { 1062 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1063 }; 1064 1065 spi1_cs1: spi1-cs1 { 1066 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1067 }; 1068 1069 spi2_clk: spi2-clk { 1070 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1071 }; 1072 1073 spi2_cs0: spi2-cs0 { 1074 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1075 }; 1076 1077 spi2_tx: spi2-tx { 1078 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1079 }; 1080 1081 spi2_rx: spi2-rx { 1082 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1083 }; 1084 }; 1085 }; 1086}; 1087
