1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H 7 #define _ASM_ARCH_SDRAM_PCTL_PX30_H 8 #include <asm/arch/sdram_share.h> 9 10 struct ddr_pctl_regs { 11 u32 pctl[30][2]; 12 }; 13 14 /* ddr pctl registers define */ 15 #define DDR_PCTL2_MSTR 0x0 16 #define DDR_PCTL2_STAT 0x4 17 #define DDR_PCTL2_MSTR1 0x8 18 #define DDR_PCTL2_MRCTRL0 0x10 19 #define DDR_PCTL2_MRCTRL1 0x14 20 #define DDR_PCTL2_MRSTAT 0x18 21 #define DDR_PCTL2_MRCTRL2 0x1c 22 #define DDR_PCTL2_DERATEEN 0x20 23 #define DDR_PCTL2_DERATEINT 0x24 24 #define DDR_PCTL2_PWRCTL 0x30 25 #define DDR_PCTL2_PWRTMG 0x34 26 #define DDR_PCTL2_HWLPCTL 0x38 27 #define DDR_PCTL2_RFSHCTL0 0x50 28 #define DDR_PCTL2_RFSHCTL1 0x54 29 #define DDR_PCTL2_RFSHCTL2 0x58 30 #define DDR_PCTL2_RFSHCTL4 0x5c 31 #define DDR_PCTL2_RFSHCTL3 0x60 32 #define DDR_PCTL2_RFSHTMG 0x64 33 #define DDR_PCTL2_RFSHTMG1 0x68 34 #define DDR_PCTL2_RFSHCTL5 0x6c 35 #define DDR_PCTL2_INIT0 0xd0 36 #define DDR_PCTL2_INIT1 0xd4 37 #define DDR_PCTL2_INIT2 0xd8 38 #define DDR_PCTL2_INIT3 0xdc 39 #define DDR_PCTL2_INIT4 0xe0 40 #define DDR_PCTL2_INIT5 0xe4 41 #define DDR_PCTL2_INIT6 0xe8 42 #define DDR_PCTL2_INIT7 0xec 43 #define DDR_PCTL2_DIMMCTL 0xf0 44 #define DDR_PCTL2_RANKCTL 0xf4 45 #define DDR_PCTL2_CHCTL 0xfc 46 #define DDR_PCTL2_DRAMTMG0 0x100 47 #define DDR_PCTL2_DRAMTMG1 0x104 48 #define DDR_PCTL2_DRAMTMG2 0x108 49 #define DDR_PCTL2_DRAMTMG3 0x10c 50 #define DDR_PCTL2_DRAMTMG4 0x110 51 #define DDR_PCTL2_DRAMTMG5 0x114 52 #define DDR_PCTL2_DRAMTMG6 0x118 53 #define DDR_PCTL2_DRAMTMG7 0x11c 54 #define DDR_PCTL2_DRAMTMG8 0x120 55 #define DDR_PCTL2_DRAMTMG9 0x124 56 #define DDR_PCTL2_DRAMTMG10 0x128 57 #define DDR_PCTL2_DRAMTMG11 0x12c 58 #define DDR_PCTL2_DRAMTMG12 0x130 59 #define DDR_PCTL2_DRAMTMG13 0x134 60 #define DDR_PCTL2_DRAMTMG14 0x138 61 #define DDR_PCTL2_DRAMTMG15 0x13c 62 #define DDR_PCTL2_DRAMTMG16 0x140 63 #define DDR_PCTL2_ZQCTL0 0x180 64 #define DDR_PCTL2_ZQCTL1 0x184 65 #define DDR_PCTL2_ZQCTL2 0x188 66 #define DDR_PCTL2_ZQSTAT 0x18c 67 #define DDR_PCTL2_DFITMG0 0x190 68 #define DDR_PCTL2_DFITMG1 0x194 69 #define DDR_PCTL2_DFILPCFG0 0x198 70 #define DDR_PCTL2_DFILPCFG1 0x19c 71 #define DDR_PCTL2_DFIUPD0 0x1a0 72 #define DDR_PCTL2_DFIUPD1 0x1a4 73 #define DDR_PCTL2_DFIUPD2 0x1a8 74 #define DDR_PCTL2_DFIMISC 0x1b0 75 #define DDR_PCTL2_DFITMG2 0x1b4 76 #define DDR_PCTL2_DFITMG3 0x1b8 77 #define DDR_PCTL2_DFISTAT 0x1bc 78 #define DDR_PCTL2_DBICTL 0x1c0 79 #define DDR_PCTL2_ADDRMAP0 0x200 80 #define DDR_PCTL2_ADDRMAP1 0x204 81 #define DDR_PCTL2_ADDRMAP2 0x208 82 #define DDR_PCTL2_ADDRMAP3 0x20c 83 #define DDR_PCTL2_ADDRMAP4 0x210 84 #define DDR_PCTL2_ADDRMAP5 0x214 85 #define DDR_PCTL2_ADDRMAP6 0x218 86 #define DDR_PCTL2_ADDRMAP7 0x21c 87 #define DDR_PCTL2_ADDRMAP8 0x220 88 #define DDR_PCTL2_ADDRMAP9 0x224 89 #define DDR_PCTL2_ADDRMAP10 0x228 90 #define DDR_PCTL2_ADDRMAP11 0x22c 91 #define DDR_PCTL2_ODTCFG 0x240 92 #define DDR_PCTL2_ODTMAP 0x244 93 #define DDR_PCTL2_SCHED 0x250 94 #define DDR_PCTL2_SCHED1 0x254 95 #define DDR_PCTL2_PERFHPR1 0x25c 96 #define DDR_PCTL2_PERFLPR1 0x264 97 #define DDR_PCTL2_PERFWR1 0x26c 98 #define DDR_PCTL2_DQMAP0 0x280 99 #define DDR_PCTL2_DQMAP1 0x284 100 #define DDR_PCTL2_DQMAP2 0x288 101 #define DDR_PCTL2_DQMAP3 0x28c 102 #define DDR_PCTL2_DQMAP4 0x290 103 #define DDR_PCTL2_DQMAP5 0x294 104 #define DDR_PCTL2_DBG0 0x300 105 #define DDR_PCTL2_DBG1 0x304 106 #define DDR_PCTL2_DBGCAM 0x308 107 #define DDR_PCTL2_DBGCMD 0x30c 108 #define DDR_PCTL2_DBGSTAT 0x310 109 #define DDR_PCTL2_SWCTL 0x320 110 #define DDR_PCTL2_SWSTAT 0x324 111 #define DDR_PCTL2_POISONCFG 0x36c 112 #define DDR_PCTL2_POISONSTAT 0x370 113 #define DDR_PCTL2_ADVECCINDEX 0x374 114 #define DDR_PCTL2_ADVECCSTAT 0x378 115 #define DDR_PCTL2_PSTAT 0x3fc 116 #define DDR_PCTL2_PCCFG 0x400 117 #define DDR_PCTL2_PCFGR_n 0x404 118 #define DDR_PCTL2_PCFGW_n 0x408 119 #define DDR_PCTL2_PCTRL_n 0x490 120 121 /* PCTL2_MRSTAT */ 122 #define MR_WR_BUSY BIT(0) 123 124 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); 125 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, 126 u32 dramtype); 127 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, 128 u32 dramtype); 129 130 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base); 131 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq); 132 133 u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, 134 struct sdram_cap_info *cap_info, 135 u32 dram_type); 136 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, 137 u32 sr_idle, u32 pd_idle); 138 139 #endif 140