1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static inline void set_vop_mcu_rs(struct vop *vop, int v) 35 { 36 if (dm_gpio_is_valid(&vop->mcu_rs_gpio)) 37 dm_gpio_set_value(&vop->mcu_rs_gpio, v); 38 else 39 VOP_CTRL_SET(vop, mcu_rs, v); 40 } 41 42 static int to_vop_csc_mode(int csc_mode) 43 { 44 switch (csc_mode) { 45 case V4L2_COLORSPACE_SMPTE170M: 46 return CSC_BT601L; 47 case V4L2_COLORSPACE_REC709: 48 case V4L2_COLORSPACE_DEFAULT: 49 return CSC_BT709L; 50 case V4L2_COLORSPACE_JPEG: 51 return CSC_BT601F; 52 case V4L2_COLORSPACE_BT2020: 53 return CSC_BT2020; 54 default: 55 return CSC_BT709L; 56 } 57 } 58 59 static bool is_yuv_output(uint32_t bus_format) 60 { 61 switch (bus_format) { 62 case MEDIA_BUS_FMT_YUV8_1X24: 63 case MEDIA_BUS_FMT_YUV10_1X30: 64 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 65 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 66 case MEDIA_BUS_FMT_YUYV8_2X8: 67 case MEDIA_BUS_FMT_YVYU8_2X8: 68 case MEDIA_BUS_FMT_UYVY8_2X8: 69 case MEDIA_BUS_FMT_VYUY8_2X8: 70 case MEDIA_BUS_FMT_YUYV8_1X16: 71 case MEDIA_BUS_FMT_YVYU8_1X16: 72 case MEDIA_BUS_FMT_UYVY8_1X16: 73 case MEDIA_BUS_FMT_VYUY8_1X16: 74 return true; 75 default: 76 return false; 77 } 78 } 79 80 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 81 { 82 /* 83 * FIXME: 84 * 85 * There is no media type for YUV444 output, 86 * so when out_mode is AAAA or P888, assume output is YUV444 on 87 * yuv format. 88 * 89 * From H/W testing, YUV444 mode need a rb swap. 90 */ 91 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 92 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 93 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 94 output_mode == ROCKCHIP_OUT_MODE_P888)) 95 return true; 96 else 97 return false; 98 } 99 100 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 101 { 102 struct crtc_state *crtc_state = &state->crtc_state; 103 struct connector_state *conn_state = &state->conn_state; 104 u32 *lut = conn_state->gamma.lut; 105 fdt_size_t lut_size; 106 int i, lut_len; 107 u32 *lut_regs; 108 109 if (!conn_state->gamma.lut) 110 return 0; 111 112 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 113 if (i < 0) { 114 printf("Warning: vop not support gamma\n"); 115 return 0; 116 } 117 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 118 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 119 printf("failed to get gamma lut register\n"); 120 return 0; 121 } 122 lut_len = lut_size / 4; 123 if (lut_len != 256 && lut_len != 1024) { 124 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 125 return 0; 126 } 127 128 if (conn_state->gamma.size != lut_len) { 129 int size = conn_state->gamma.size; 130 u32 j, r, g, b, color; 131 132 for (i = 0; i < lut_len; i++) { 133 j = i * size / lut_len; 134 r = lut[j] / size / size * lut_len / size; 135 g = lut[j] / size % size * lut_len / size; 136 b = lut[j] % size * lut_len / size; 137 color = r * lut_len * lut_len + g * lut_len + b; 138 139 writel(color, lut_regs + (i << 2)); 140 } 141 } else { 142 for (i = 0; i < lut_len; i++) 143 writel(lut[i], lut_regs + (i << 2)); 144 } 145 146 VOP_CTRL_SET(vop, dsp_lut_en, 1); 147 VOP_CTRL_SET(vop, update_gamma_lut, 1); 148 149 return 0; 150 } 151 152 static void vop_post_config(struct display_state *state, struct vop *vop) 153 { 154 struct connector_state *conn_state = &state->conn_state; 155 struct drm_display_mode *mode = &conn_state->mode; 156 u16 vtotal = mode->crtc_vtotal; 157 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 158 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 159 u16 hdisplay = mode->crtc_hdisplay; 160 u16 vdisplay = mode->crtc_vdisplay; 161 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 162 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 163 u16 hact_end, vact_end; 164 u32 val; 165 166 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 167 vsize = round_down(vsize, 2); 168 169 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 170 hact_end = hact_st + hsize; 171 val = hact_st << 16; 172 val |= hact_end; 173 174 VOP_CTRL_SET(vop, hpost_st_end, val); 175 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 176 vact_end = vact_st + vsize; 177 val = vact_st << 16; 178 val |= vact_end; 179 VOP_CTRL_SET(vop, vpost_st_end, val); 180 val = scl_cal_scale2(vdisplay, vsize) << 16; 181 val |= scl_cal_scale2(hdisplay, hsize); 182 VOP_CTRL_SET(vop, post_scl_factor, val); 183 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 184 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 185 VOP_CTRL_SET(vop, post_scl_ctrl, 186 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 187 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 188 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 189 u16 vact_st_f1 = vtotal + vact_st + 1; 190 u16 vact_end_f1 = vact_st_f1 + vsize; 191 192 val = vact_st_f1 << 16 | vact_end_f1; 193 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 194 } 195 } 196 197 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 198 { 199 struct crtc_state *crtc_state = &state->crtc_state; 200 201 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 202 VOP_CTRL_SET(vop, mcu_type, 1); 203 204 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 205 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 206 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 207 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 208 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 209 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 210 } 211 212 static int rockchip_vop_preinit(struct display_state *state) 213 { 214 const struct vop_data *vop_data = state->crtc_state.crtc->data; 215 216 state->crtc_state.max_output = vop_data->max_output; 217 218 return 0; 219 } 220 221 static int rockchip_vop_init(struct display_state *state) 222 { 223 struct crtc_state *crtc_state = &state->crtc_state; 224 struct connector_state *conn_state = &state->conn_state; 225 struct drm_display_mode *mode = &conn_state->mode; 226 const struct rockchip_crtc *crtc = crtc_state->crtc; 227 const struct vop_data *vop_data = crtc->data; 228 struct vop *vop; 229 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 230 u16 hdisplay = mode->crtc_hdisplay; 231 u16 htotal = mode->crtc_htotal; 232 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 233 u16 hact_end = hact_st + hdisplay; 234 u16 vdisplay = mode->crtc_vdisplay; 235 u16 vtotal = mode->crtc_vtotal; 236 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 237 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 238 u16 vact_end = vact_st + vdisplay; 239 struct clk dclk; 240 u32 val, act_end; 241 int ret; 242 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 243 u16 post_csc_mode; 244 bool dclk_inv; 245 246 vop = malloc(sizeof(*vop)); 247 if (!vop) 248 return -ENOMEM; 249 memset(vop, 0, sizeof(*vop)); 250 251 crtc_state->private = vop; 252 vop->regs = dev_read_addr_ptr(crtc_state->dev); 253 vop->regsbak = malloc(vop_data->reg_len); 254 vop->win = vop_data->win; 255 vop->win_offset = vop_data->win_offset; 256 vop->ctrl = vop_data->ctrl; 257 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 258 if (vop->grf <= 0) 259 printf("%s: Get syscon grf failed (ret=%p)\n", 260 __func__, vop->grf); 261 262 vop->grf_ctrl = vop_data->grf_ctrl; 263 vop->line_flag = vop_data->line_flag; 264 vop->csc_table = vop_data->csc_table; 265 vop->win_csc = vop_data->win_csc; 266 vop->version = vop_data->version; 267 268 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 269 ret = clk_set_defaults(crtc_state->dev); 270 if (ret) 271 debug("%s clk_set_defaults failed %d\n", __func__, ret); 272 273 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 274 if (!ret) 275 ret = clk_set_rate(&dclk, mode->clock * 1000); 276 if (IS_ERR_VALUE(ret)) { 277 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 278 return ret; 279 } 280 281 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 282 283 rockchip_vop_init_gamma(vop, state); 284 285 ret = gpio_request_by_name(crtc_state->dev, "mcu-rs-gpios", 286 0, &vop->mcu_rs_gpio, GPIOD_IS_OUT); 287 if (ret && ret != -ENOENT) 288 printf("%s: Cannot get mcu rs GPIO: %d\n", __func__, ret); 289 290 VOP_CTRL_SET(vop, global_regdone_en, 1); 291 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 292 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 293 VOP_CTRL_SET(vop, reg_done_frm, 1); 294 VOP_CTRL_SET(vop, win_gate[0], 1); 295 VOP_CTRL_SET(vop, win_gate[1], 1); 296 VOP_CTRL_SET(vop, win_channel[0], 0x12); 297 VOP_CTRL_SET(vop, win_channel[1], 0x34); 298 VOP_CTRL_SET(vop, win_channel[2], 0x56); 299 VOP_CTRL_SET(vop, dsp_blank, 0); 300 301 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 302 /* For improving signal quality, dclk need to be inverted by default on rv1106. */ 303 if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12)) 304 dclk_inv = !dclk_inv; 305 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 306 307 val = 0x8; 308 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 309 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 310 VOP_CTRL_SET(vop, pin_pol, val); 311 312 switch (conn_state->type) { 313 case DRM_MODE_CONNECTOR_LVDS: 314 VOP_CTRL_SET(vop, rgb_en, 1); 315 VOP_CTRL_SET(vop, rgb_pin_pol, val); 316 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 317 VOP_CTRL_SET(vop, lvds_en, 1); 318 VOP_CTRL_SET(vop, lvds_pin_pol, val); 319 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 320 if (!IS_ERR_OR_NULL(vop->grf)) 321 VOP_GRF_SET(vop, grf_dclk_inv, dclk_inv); 322 break; 323 case DRM_MODE_CONNECTOR_eDP: 324 VOP_CTRL_SET(vop, edp_en, 1); 325 VOP_CTRL_SET(vop, edp_pin_pol, val); 326 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 327 break; 328 case DRM_MODE_CONNECTOR_HDMIA: 329 VOP_CTRL_SET(vop, hdmi_en, 1); 330 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 331 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 332 break; 333 case DRM_MODE_CONNECTOR_DSI: 334 VOP_CTRL_SET(vop, mipi_en, 1); 335 VOP_CTRL_SET(vop, mipi_pin_pol, val); 336 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 337 VOP_CTRL_SET(vop, mipi_dual_channel_en, 338 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)); 339 VOP_CTRL_SET(vop, data01_swap, 340 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) || 341 crtc_state->dual_channel_swap); 342 break; 343 case DRM_MODE_CONNECTOR_DisplayPort: 344 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 345 VOP_CTRL_SET(vop, dp_pin_pol, val); 346 VOP_CTRL_SET(vop, dp_en, 1); 347 break; 348 case DRM_MODE_CONNECTOR_TV: 349 if (vdisplay == CVBS_PAL_VDISPLAY) 350 VOP_CTRL_SET(vop, tve_sw_mode, 1); 351 else 352 VOP_CTRL_SET(vop, tve_sw_mode, 0); 353 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 354 VOP_CTRL_SET(vop, tve_dclk_en, 1); 355 /* use the same pol reg with hdmi */ 356 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 357 VOP_CTRL_SET(vop, sw_genlock, 1); 358 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 359 VOP_CTRL_SET(vop, dither_up, 1); 360 break; 361 default: 362 printf("unsupport connector_type[%d]\n", conn_state->type); 363 } 364 365 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 366 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 367 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 368 369 switch (conn_state->bus_format) { 370 case MEDIA_BUS_FMT_RGB565_1X16: 371 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 372 break; 373 case MEDIA_BUS_FMT_RGB666_1X18: 374 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 375 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 376 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 377 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 378 break; 379 case MEDIA_BUS_FMT_YUV8_1X24: 380 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 381 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 382 break; 383 case MEDIA_BUS_FMT_YUV10_1X30: 384 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 385 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 386 break; 387 case MEDIA_BUS_FMT_RGB888_1X24: 388 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 389 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 390 default: 391 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 392 break; 393 } 394 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 395 val |= PRE_DITHER_DOWN_EN(0); 396 else 397 val |= PRE_DITHER_DOWN_EN(1); 398 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 399 VOP_CTRL_SET(vop, dither_down, val); 400 401 VOP_CTRL_SET(vop, dclk_ddr, 402 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 403 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 404 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 405 406 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 407 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 408 else 409 VOP_CTRL_SET(vop, dsp_data_swap, 0); 410 411 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 412 413 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 414 yuv_overlay = is_yuv_output(conn_state->bus_format); 415 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 416 } 417 /* 418 * todo: r2y for win csc 419 */ 420 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 421 422 if (yuv_overlay) { 423 if (!is_yuv_output(conn_state->bus_format)) 424 post_y2r_en = true; 425 } else { 426 if (is_yuv_output(conn_state->bus_format)) 427 post_r2y_en = true; 428 } 429 430 crtc_state->yuv_overlay = yuv_overlay; 431 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 432 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 433 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 434 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 435 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 436 437 /* 438 * Background color is 10bit depth if vop version >= 3.5 439 */ 440 if (!is_yuv_output(conn_state->bus_format)) 441 val = 0; 442 else if (VOP_MAJOR(vop->version) == 3 && 443 VOP_MINOR(vop->version) >= 5) 444 val = 0x20010200; 445 else 446 val = 0x801080; 447 VOP_CTRL_SET(vop, dsp_background, val); 448 449 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 450 val = hact_st << 16; 451 val |= hact_end; 452 VOP_CTRL_SET(vop, hact_st_end, val); 453 val = vact_st << 16; 454 val |= vact_end; 455 VOP_CTRL_SET(vop, vact_st_end, val); 456 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 457 u16 vact_st_f1 = vtotal + vact_st + 1; 458 u16 vact_end_f1 = vact_st_f1 + vdisplay; 459 460 val = vact_st_f1 << 16 | vact_end_f1; 461 VOP_CTRL_SET(vop, vact_st_end_f1, val); 462 463 val = vtotal << 16 | (vtotal + vsync_len); 464 VOP_CTRL_SET(vop, vs_st_end_f1, val); 465 VOP_CTRL_SET(vop, dsp_interlace, 1); 466 VOP_CTRL_SET(vop, p2i_en, 1); 467 vtotal += vtotal + 1; 468 act_end = vact_end_f1; 469 } else { 470 VOP_CTRL_SET(vop, dsp_interlace, 0); 471 VOP_CTRL_SET(vop, p2i_en, 0); 472 act_end = vact_end; 473 } 474 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 475 vop_post_config(state, vop); 476 VOP_CTRL_SET(vop, core_dclk_div, 477 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 478 479 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 480 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 481 act_end - us_to_vertical_line(mode, 1000)); 482 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 483 vop_mcu_mode(state, vop); 484 vop_cfg_done(vop); 485 486 return 0; 487 } 488 489 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 490 uint32_t dst, bool is_horizontal, 491 int vsu_mode, int *vskiplines) 492 { 493 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 494 495 if (is_horizontal) { 496 if (mode == SCALE_UP) 497 val = GET_SCL_FT_BIC(src, dst); 498 else if (mode == SCALE_DOWN) 499 val = GET_SCL_FT_BILI_DN(src, dst); 500 } else { 501 if (mode == SCALE_UP) { 502 if (vsu_mode == SCALE_UP_BIL) 503 val = GET_SCL_FT_BILI_UP(src, dst); 504 else 505 val = GET_SCL_FT_BIC(src, dst); 506 } else if (mode == SCALE_DOWN) { 507 if (vskiplines) { 508 *vskiplines = scl_get_vskiplines(src, dst); 509 val = scl_get_bili_dn_vskip(src, dst, 510 *vskiplines); 511 } else { 512 val = GET_SCL_FT_BILI_DN(src, dst); 513 } 514 } 515 } 516 517 return val; 518 } 519 520 static void scl_vop_cal_scl_fac(struct vop *vop, 521 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 522 uint32_t dst_h, uint32_t pixel_format) 523 { 524 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 525 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 526 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 527 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 528 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 529 bool is_yuv = false; 530 uint16_t cbcr_src_w = src_w / hsub; 531 uint16_t cbcr_src_h = src_h / vsub; 532 uint16_t vsu_mode; 533 uint16_t lb_mode; 534 uint32_t val; 535 int vskiplines = 0; 536 537 if (!vop->win->scl) 538 return; 539 540 if (!vop->win->scl->ext) { 541 VOP_SCL_SET(vop, scale_yrgb_x, 542 scl_cal_scale2(src_w, dst_w)); 543 VOP_SCL_SET(vop, scale_yrgb_y, 544 scl_cal_scale2(src_h, dst_h)); 545 if (is_yuv) { 546 VOP_SCL_SET(vop, scale_cbcr_x, 547 scl_cal_scale2(src_w, dst_w)); 548 VOP_SCL_SET(vop, scale_cbcr_y, 549 scl_cal_scale2(src_h, dst_h)); 550 } 551 return; 552 } 553 554 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 555 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 556 557 if (is_yuv) { 558 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 559 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 560 if (cbcr_hor_scl_mode == SCALE_DOWN) 561 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 562 else 563 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 564 } else { 565 if (yrgb_hor_scl_mode == SCALE_DOWN) 566 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 567 else 568 lb_mode = scl_vop_cal_lb_mode(src_w, false); 569 } 570 571 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 572 if (lb_mode == LB_RGB_3840X2) { 573 if (yrgb_ver_scl_mode != SCALE_NONE) { 574 printf("ERROR : not allow yrgb ver scale\n"); 575 return; 576 } 577 if (cbcr_ver_scl_mode != SCALE_NONE) { 578 printf("ERROR : not allow cbcr ver scale\n"); 579 return; 580 } 581 vsu_mode = SCALE_UP_BIL; 582 } else if (lb_mode == LB_RGB_2560X4) { 583 vsu_mode = SCALE_UP_BIL; 584 } else { 585 vsu_mode = SCALE_UP_BIC; 586 } 587 588 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 589 true, 0, NULL); 590 VOP_SCL_SET(vop, scale_yrgb_x, val); 591 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 592 false, vsu_mode, &vskiplines); 593 VOP_SCL_SET(vop, scale_yrgb_y, val); 594 595 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 596 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 597 598 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 599 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 600 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 601 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 602 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 603 if (is_yuv) { 604 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 605 dst_w, true, 0, NULL); 606 VOP_SCL_SET(vop, scale_cbcr_x, val); 607 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 608 dst_h, false, vsu_mode, &vskiplines); 609 VOP_SCL_SET(vop, scale_cbcr_y, val); 610 611 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 612 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 613 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 614 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 615 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 616 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 617 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 618 } 619 } 620 621 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 622 { 623 int i; 624 625 /* 626 * so far the csc offset is not 0 and in the feature the csc offset 627 * impossible be 0, so when the offset is 0, should return here. 628 */ 629 if (!table || offset == 0) 630 return; 631 632 for (i = 0; i < 8; i++) 633 vop_writel(vop, offset + i * 4, table[i]); 634 } 635 636 static int rockchip_vop_setup_csc_table(struct display_state *state) 637 { 638 struct crtc_state *crtc_state = &state->crtc_state; 639 struct connector_state *conn_state = &state->conn_state; 640 struct vop *vop = crtc_state->private; 641 const uint32_t *csc_table = NULL; 642 643 if (!vop->csc_table || !crtc_state->yuv_overlay) 644 return 0; 645 /* todo: only implement r2y*/ 646 switch (conn_state->color_space) { 647 case V4L2_COLORSPACE_SMPTE170M: 648 csc_table = vop->csc_table->r2y_bt601_12_235; 649 break; 650 case V4L2_COLORSPACE_REC709: 651 case V4L2_COLORSPACE_DEFAULT: 652 case V4L2_COLORSPACE_JPEG: 653 csc_table = vop->csc_table->r2y_bt709; 654 break; 655 case V4L2_COLORSPACE_BT2020: 656 csc_table = vop->csc_table->r2y_bt2020; 657 break; 658 default: 659 csc_table = vop->csc_table->r2y_bt601; 660 break; 661 } 662 663 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 664 VOP_WIN_CSC_SET(vop, r2y_en, 1); 665 666 return 0; 667 } 668 669 static int rockchip_vop_set_plane(struct display_state *state) 670 { 671 struct crtc_state *crtc_state = &state->crtc_state; 672 const struct rockchip_crtc *crtc = crtc_state->crtc; 673 const struct vop_data *vop_data = crtc->data; 674 struct connector_state *conn_state = &state->conn_state; 675 struct drm_display_mode *mode = &conn_state->mode; 676 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 677 struct vop *vop = crtc_state->private; 678 int src_w = crtc_state->src_rect.w; 679 int src_h = crtc_state->src_rect.h; 680 int crtc_x = crtc_state->crtc_rect.x; 681 int crtc_y = crtc_state->crtc_rect.y; 682 int crtc_w = crtc_state->crtc_rect.w; 683 int crtc_h = crtc_state->crtc_rect.h; 684 int xvir = crtc_state->xvir; 685 int x_mirror = 0, y_mirror = 0; 686 687 if (crtc_w > crtc_state->max_output.width) { 688 printf("ERROR: output w[%d] exceeded max width[%d]\n", 689 crtc_w, crtc_state->max_output.width); 690 return -EINVAL; 691 } 692 693 act_info = (src_h - 1) << 16; 694 act_info |= (src_w - 1) & 0xffff; 695 696 dsp_info = (crtc_h - 1) << 16; 697 dsp_info |= (crtc_w - 1) & 0xffff; 698 699 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 700 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 701 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 702 /* 703 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround 704 */ 705 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3) 706 crtc_state->rb_swap = !crtc_state->rb_swap; 707 708 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 709 y_mirror = 1; 710 else 711 y_mirror = 0; 712 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 713 x_mirror = 1; 714 else 715 x_mirror = 0; 716 if (crtc_state->ymirror ^ y_mirror) 717 y_mirror = 1; 718 else 719 y_mirror = 0; 720 if (y_mirror) { 721 if (VOP_CTRL_SUPPORT(vop, ymirror)) 722 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 723 else 724 y_mirror = 0; 725 } 726 VOP_CTRL_SET(vop, ymirror, y_mirror); 727 VOP_CTRL_SET(vop, xmirror, x_mirror); 728 729 VOP_WIN_SET(vop, format, crtc_state->format); 730 VOP_WIN_SET(vop, yrgb_vir, xvir); 731 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 732 733 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 734 crtc_state->format); 735 736 VOP_WIN_SET(vop, act_info, act_info); 737 VOP_WIN_SET(vop, dsp_info, dsp_info); 738 VOP_WIN_SET(vop, dsp_st, dsp_st); 739 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 740 741 VOP_WIN_SET(vop, src_alpha_ctl, 0); 742 743 rockchip_vop_setup_csc_table(state); 744 VOP_WIN_SET(vop, enable, 1); 745 VOP_WIN_SET(vop, gate, 1); 746 vop_cfg_done(vop); 747 748 return 0; 749 } 750 751 static int rockchip_vop_prepare(struct display_state *state) 752 { 753 return 0; 754 } 755 756 static int rockchip_vop_enable(struct display_state *state) 757 { 758 struct crtc_state *crtc_state = &state->crtc_state; 759 struct vop *vop = crtc_state->private; 760 761 VOP_CTRL_SET(vop, standby, 0); 762 vop_cfg_done(vop); 763 if (crtc_state->mcu_timing.mcu_pix_total > 0) 764 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 765 766 return 0; 767 } 768 769 static int rockchip_vop_disable(struct display_state *state) 770 { 771 struct crtc_state *crtc_state = &state->crtc_state; 772 struct vop *vop = crtc_state->private; 773 774 VOP_CTRL_SET(vop, standby, 1); 775 vop_cfg_done(vop); 776 return 0; 777 } 778 779 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 780 { 781 #if 0 782 struct crtc_state *crtc_state = &state->crtc_state; 783 struct panel_state *pstate = &state->panel_state; 784 uint32_t phandle; 785 char path[100]; 786 int ret, dsp_lut_node; 787 788 if (!ofnode_valid(pstate->dsp_lut_node)) 789 return 0; 790 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 791 if (ret < 0) { 792 printf("failed to get dsp_lut path[%s], ret=%d\n", 793 path, ret); 794 return ret; 795 } 796 797 dsp_lut_node = fdt_path_offset(blob, path); 798 phandle = fdt_get_phandle(blob, dsp_lut_node); 799 if (!phandle) { 800 phandle = fdt_alloc_phandle(blob); 801 if (!phandle) { 802 printf("failed to alloc phandle\n"); 803 return -ENOMEM; 804 } 805 806 fdt_set_phandle(blob, dsp_lut_node, phandle); 807 } 808 809 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 810 if (ret < 0) { 811 printf("failed to get route path[%s], ret=%d\n", 812 path, ret); 813 return ret; 814 } 815 816 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 817 #endif 818 return 0; 819 } 820 821 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 822 u32 type, u32 value) 823 { 824 struct crtc_state *crtc_state = &state->crtc_state; 825 struct vop *vop = crtc_state->private; 826 827 if (vop) { 828 switch (type) { 829 case MCU_WRCMD: 830 set_vop_mcu_rs(vop, 0); 831 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 832 set_vop_mcu_rs(vop, 1); 833 break; 834 case MCU_WRDATA: 835 set_vop_mcu_rs(vop, 1); 836 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 837 break; 838 case MCU_SETBYPASS: 839 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 840 break; 841 default: 842 break; 843 } 844 } 845 846 return 0; 847 } 848 849 static int rockchip_vop_mode_valid(struct display_state *state) 850 { 851 struct connector_state *conn_state = &state->conn_state; 852 struct drm_display_mode *mode = &conn_state->mode; 853 struct videomode vm; 854 855 drm_display_mode_to_videomode(mode, &vm); 856 857 if (vm.hactive < 32 || vm.vactive < 32 || 858 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 859 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 860 printf("ERROR: unsupported display timing\n"); 861 return -EINVAL; 862 } 863 864 return 0; 865 } 866 867 static int rockchip_vop_plane_check(struct display_state *state) 868 { 869 struct crtc_state *crtc_state = &state->crtc_state; 870 const struct rockchip_crtc *crtc = crtc_state->crtc; 871 const struct vop_data *vop_data = crtc->data; 872 const struct vop_win *win = vop_data->win; 873 struct display_rect *src = &crtc_state->src_rect; 874 struct display_rect *dst = &crtc_state->crtc_rect; 875 int min_scale, max_scale; 876 int hscale, vscale; 877 878 min_scale = win->scl ? FRAC_16_16(1, 8) : VOP_PLANE_NO_SCALING; 879 max_scale = win->scl ? FRAC_16_16(8, 1) : VOP_PLANE_NO_SCALING; 880 881 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 882 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 883 if (hscale < 0 || vscale < 0) { 884 printf("ERROR: scale factor is out of range\n"); 885 return -ERANGE; 886 } 887 888 return 0; 889 } 890 891 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 892 .preinit = rockchip_vop_preinit, 893 .init = rockchip_vop_init, 894 .set_plane = rockchip_vop_set_plane, 895 .prepare = rockchip_vop_prepare, 896 .enable = rockchip_vop_enable, 897 .disable = rockchip_vop_disable, 898 .fixup_dts = rockchip_vop_fixup_dts, 899 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 900 .mode_valid = rockchip_vop_mode_valid, 901 .plane_check = rockchip_vop_plane_check, 902 }; 903