1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16 }; 17 18 secure-otp@ffcd0000 { 19 compatible = "rockchip,rk3528-secure-otp"; 20 reg = <0x0 0xffcd0000 0x0 0x4000>; 21 secure_conf = <0xff4500c0>; 22 mask_addr = <0x0>; 23 cru_rst_addr = <0xff4a8080>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27 28}; 29 30&grf { 31 u-boot,dm-spl; 32 status = "okay"; 33}; 34 35&ioc_grf { 36 u-boot,dm-spl; 37 status = "okay"; 38}; 39 40&cru { 41 u-boot,dm-spl; 42 status = "okay"; 43}; 44 45&crypto { 46 clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; 47 clock-names = "sclk", "pka"; 48 clock-frequency = <200000000>, <300000000>; 49 u-boot,dm-spl; 50 status = "okay"; 51}; 52 53&rng { 54 u-boot,dm-pre-reloc; 55 status = "okay"; 56}; 57 58&psci { 59 u-boot,dm-pre-reloc; 60 status = "okay"; 61}; 62 63&uart2 { 64 clock-frequency = <24000000>; 65 u-boot,dm-spl; 66 status = "okay"; 67}; 68 69&sfc { 70 u-boot,dm-spl; 71 /delete-property/ pinctrl-names; 72 /delete-property/ pinctrl-0; 73 /delete-property/ assigned-clocks; 74 /delete-property/ assigned-clock-rates; 75 status = "okay"; 76 77 #address-cells = <1>; 78 #size-cells = <0>; 79 spi_nand: flash@0 { 80 u-boot,dm-spl; 81 compatible = "spi-nand"; 82 reg = <0>; 83 spi-tx-bus-width = <1>; 84 spi-rx-bus-width = <4>; 85 spi-max-frequency = <75000000>; 86 }; 87 88 spi_nor: flash@1 { 89 u-boot,dm-spl; 90 compatible = "jedec,spi-nor"; 91 label = "sfc_nor"; 92 reg = <0>; 93 spi-tx-bus-width = <1>; 94 spi-rx-bus-width = <4>; 95 spi-max-frequency = <100000000>; 96 }; 97}; 98 99&sdhci { 100 bus-width = <8>; 101 u-boot,dm-spl; 102 /delete-property/ pinctrl-names; 103 /delete-property/ pinctrl-0; 104 mmc-hs400-1_8v; 105 mmc-hs400-enhanced-strobe; 106 fixed-emmc-driver-type = <1>; 107 status = "okay"; 108}; 109 110&sdmmc { 111 u-boot,dm-spl; 112 status = "okay"; 113}; 114 115&saradc { 116 u-boot,dm-pre-reloc; 117 status = "okay"; 118}; 119 120&u2phy_otg { 121 u-boot,dm-pre-reloc; 122 status = "okay"; 123}; 124 125&usb2phy { 126 u-boot,dm-pre-reloc; 127 status = "okay"; 128}; 129 130&firmware { 131 u-boot,dm-spl; 132}; 133 134&scmi { 135 u-boot,dm-spl; 136}; 137 138&scmi_clk { 139 u-boot,dm-spl; 140}; 141 142&scmi_shmem { 143 u-boot,dm-spl; 144}; 145 146&pinctrl { 147 u-boot,dm-spl; 148 status = "okay"; 149}; 150 151&gpio0 { 152 u-boot,dm-spl; 153}; 154 155&gpio1 { 156 u-boot,dm-spl; 157}; 158 159&gpio2 { 160 u-boot,dm-spl; 161}; 162 163&pcfg_pull_none_drv_level_1 { 164 u-boot,dm-spl; 165}; 166 167&pcfg_pull_none_drv_level_2 { 168 u-boot,dm-spl; 169}; 170 171&pcfg_pull_up_drv_level_1 { 172 u-boot,dm-spl; 173}; 174 175&pcfg_pull_up_drv_level_2 { 176 u-boot,dm-spl; 177}; 178 179&pcfg_pull_up { 180 u-boot,dm-spl; 181}; 182 183&pcfg_pull_none { 184 u-boot,dm-spl; 185}; 186 187&sdmmc_pins { 188 u-boot,dm-spl; 189}; 190 191&sdmmc_bus4 { 192 u-boot,dm-spl; 193}; 194 195&sdmmc_clk { 196 u-boot,dm-spl; 197}; 198 199&sdmmc_cmd { 200 u-boot,dm-spl; 201}; 202 203&sdmmc_det { 204 u-boot,dm-spl; 205}; 206