| 4ec4e545 | 06-Sep-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(sctlr2): add support for FEAT_SCTLR2
Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the
feat(sctlr2): add support for FEAT_SCTLR2
Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 781e1a44 | 20-May-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(cm): enhance the cpu_context memory report
Currently, as part of the context_memory report, we explicitly
list the EL3, EL1 and EL2 registers and memory usage per CPU
for each world. The remain
feat(cm): enhance the cpu_context memory report
Currently, as part of the context_memory report, we explicitly
list the EL3, EL1 and EL2 registers and memory usage per CPU
for each world. The remaining bits in the cpu_context_t structure
are grouped and listed as other section.
This patch enhances this part, by individually listing all the
remaining bits (GPREGS, PAUTH_REGS) separately providing
a much detailed overview of the context memory consumption
amongst the registers.
The patch has been tested on the CI with the following patch
and the results are summarised precisely.
[https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/28849]
Change-Id: I16f210b605ddd7900600519520accf1ccd057bc7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| a0674ab0 | 07-May-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1
* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure,
refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1
* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.
* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.
* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.
* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.
Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.
Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| a0d9a973 | 30-Jul-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr
chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.
Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 188f8c4b | 18-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
feat(cm): handle asymmetry for SPE feature
With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. SPE is one of the features which can be asymmetric
across cores.
feat(cm): handle asymmetry for SPE feature
With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. SPE is one of the features which can be asymmetric
across cores.
Add a function to handle this asymmetry by re-visting the feature
presence on running core.
There are two possible cases:
- If the primary has the feature and secondary does not have it then,
the feature needs to be disabled.
- If the primary does not have the feature and secondary has it then,
the feature need to be enabled
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibb2b88b5ef63b3efcb80801898ae8d8967e5c271
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| 2f41c9a7 | 12-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
feat(cm): support for asymmetric feature among cores
TF-A assumes that all the cores in a platform has architecture feature
parity, this is evident by the fact that primary sets up the
Non-secure co
feat(cm): support for asymmetric feature among cores
TF-A assumes that all the cores in a platform has architecture feature
parity, this is evident by the fact that primary sets up the
Non-secure context of secondary cores.
With changing landscape of platforms (e.g. big/little/mid cores), we are
seeing more and more platforms which has feature asymmetry among cores.
There is also a scenario where certain CPU erratum only applies to one
type of cores and requires a feature to be disabled even it supports
the feature.
To handle these scenarios, introduce a hook in warmboot path which would
be called on the running CPU to override any feature disparity in the
NS context stashed up by primary. Note that, re-checking of feature for
Secure/Realm context is not required as the context is created on
running core itself.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I5a01dbda528fa8481a00fdd098b58a7463ed0e22
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| 42e35d2f | 11-Apr-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
refactor(cm): convert el1-ctx assembly offset entries to c structure
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca
refactor(cm): convert el1-ctx assembly offset entries to c structure
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.
Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.
Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 59b7c0a0 | 05-Jun-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.
* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.
* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.
* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".
* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.
Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 0aa3284a | 17-Jul-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(context-mgmt): keep actlr_el2 value in the init context
The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
fix(context-mgmt): keep actlr_el2 value in the init context
The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
actlr_el2 is set in the platform reset handler to enable the write
access to DSU PMU registers from EL1. However, as EL2 context gets
restored without saving it beforehand during jump to SPM and next NS
image, therefore, the initialized value of actlr_el2 is not retained.
To fix this issue, keep track of actlr_el2 value during the EL2 context
initialization. This applies for both secure and non-secure security
state.
Change-Id: I1bd7b984216c042c056ad20c6724bedce5a6a3e2
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
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