1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL1_H 8 #define CONTEXT_EL1_H 9 10 #ifndef __ASSEMBLER__ 11 12 /******************************************************************************* 13 * EL1 Registers: 14 * AArch64 EL1 system register context structure for preserving the 15 * architectural state during world switches. 16 ******************************************************************************/ 17 18 typedef struct el1_common_regs { 19 uint64_t spsr_el1; 20 uint64_t elr_el1; 21 22 #if (!ERRATA_SPECULATIVE_AT) 23 uint64_t sctlr_el1; 24 uint64_t tcr_el1; 25 #endif /* ERRATA_SPECULATIVE_AT=0 */ 26 27 uint64_t cpacr_el1; 28 uint64_t csselr_el1; 29 uint64_t sp_el1; 30 uint64_t esr_el1; 31 uint64_t ttbr0_el1; 32 uint64_t ttbr1_el1; 33 uint64_t mair_el1; 34 uint64_t amair_el1; 35 uint64_t actlr_el1; 36 uint64_t tpidr_el1; 37 uint64_t tpidr_el0; 38 uint64_t tpidrro_el0; 39 uint64_t par_el1; 40 uint64_t far_el1; 41 uint64_t afsr0_el1; 42 uint64_t afsr1_el1; 43 uint64_t contextidr_el1; 44 uint64_t vbar_el1; 45 uint64_t mdccint_el1; 46 uint64_t mdscr_el1; 47 } el1_common_regs_t; 48 49 typedef struct el1_aarch32_regs { 50 uint64_t spsr_abt; 51 uint64_t spsr_und; 52 uint64_t spsr_irq; 53 uint64_t spsr_fiq; 54 uint64_t dacr32_el2; 55 uint64_t ifsr32_el2; 56 } el1_aarch32_regs_t; 57 58 typedef struct el1_arch_timer_regs { 59 uint64_t cntp_ctl_el0; 60 uint64_t cntp_cval_el0; 61 uint64_t cntv_ctl_el0; 62 uint64_t cntv_cval_el0; 63 uint64_t cntkctl_el1; 64 } el1_arch_timer_regs_t; 65 66 typedef struct el1_mte2_regs { 67 uint64_t tfsre0_el1; 68 uint64_t tfsr_el1; 69 uint64_t rgsr_el1; 70 uint64_t gcr_el1; 71 } el1_mte2_regs_t; 72 73 typedef struct el1_ras_regs { 74 uint64_t disr_el1; 75 } el1_ras_regs_t; 76 77 typedef struct el1_s1pie_regs { 78 uint64_t pire0_el1; 79 uint64_t pir_el1; 80 } el1_s1pie_regs_t; 81 82 typedef struct el1_s1poe_regs { 83 uint64_t por_el1; 84 } el1_s1poe_regs_t; 85 86 typedef struct el1_s2poe_regs { 87 uint64_t s2por_el1; 88 } el1_s2poe_regs_t; 89 90 typedef struct el1_tcr2_regs { 91 uint64_t tcr2_el1; 92 } el1_tcr2_regs_t; 93 94 typedef struct el1_trf_regs { 95 uint64_t trfcr_el1; 96 } el1_trf_regs_t; 97 98 typedef struct el1_csv2_2_regs { 99 uint64_t scxtnum_el0; 100 uint64_t scxtnum_el1; 101 } el1_csv2_2_regs_t; 102 103 typedef struct el1_gcs_regs { 104 uint64_t gcscr_el1; 105 uint64_t gcscre0_el1; 106 uint64_t gcspr_el1; 107 uint64_t gcspr_el0; 108 } el1_gcs_regs_t; 109 110 typedef struct el1_the_regs { 111 uint64_t rcwmask_el1; 112 uint64_t rcwsmask_el1; 113 } el1_the_regs_t; 114 115 typedef struct el1_sysregs { 116 117 el1_common_regs_t common; 118 119 #if CTX_INCLUDE_AARCH32_REGS 120 el1_aarch32_regs_t el1_aarch32; 121 #endif 122 123 #if NS_TIMER_SWITCH 124 el1_arch_timer_regs_t arch_timer; 125 #endif 126 127 #if ENABLE_FEAT_MTE2 128 el1_mte2_regs_t mte2; 129 #endif 130 131 #if ENABLE_FEAT_RAS 132 el1_ras_regs_t ras; 133 #endif 134 135 #if ENABLE_FEAT_S1PIE 136 el1_s1pie_regs_t s1pie; 137 #endif 138 139 #if ENABLE_FEAT_S1POE 140 el1_s1poe_regs_t s1poe; 141 #endif 142 143 #if ENABLE_FEAT_S2POE 144 el1_s2poe_regs_t s2poe; 145 #endif 146 147 #if ENABLE_FEAT_TCR2 148 el1_tcr2_regs_t tcr2; 149 #endif 150 151 #if ENABLE_TRF_FOR_NS 152 el1_trf_regs_t trf; 153 #endif 154 155 #if ENABLE_FEAT_CSV2_2 156 el1_csv2_2_regs_t csv2_2; 157 #endif 158 159 #if ENABLE_FEAT_GCS 160 el1_gcs_regs_t gcs; 161 #endif 162 163 #if ENABLE_FEAT_THE 164 el1_the_regs_t the; 165 #endif 166 167 } el1_sysregs_t; 168 169 170 /* 171 * Macros to access members related to individual features of the el1_sysregs_t 172 * structures. 173 */ 174 175 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) 176 177 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 178 = (uint64_t) (val)) 179 180 #if NS_TIMER_SWITCH 181 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) 182 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ 183 = (uint64_t) (val)) 184 #else 185 #define read_el1_ctx_arch_timer(ctx, reg) ULL(0) 186 #define write_el1_ctx_arch_timer(ctx, reg, val) 187 #endif /* NS_TIMER_SWITCH */ 188 189 #if CTX_INCLUDE_AARCH32_REGS 190 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) 191 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ 192 = (uint64_t) (val)) 193 #else 194 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) 195 #define write_el1_ctx_aarch32(ctx, reg, val) 196 #endif /* CTX_INCLUDE_AARCH32_REGS */ 197 198 #if ENABLE_FEAT_MTE2 199 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 200 #define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 201 = (uint64_t) (val)) 202 #else 203 #define read_el1_ctx_mte2(ctx, reg) ULL(0) 204 #define write_el1_ctx_mte2(ctx, reg, val) 205 #endif /* ENABLE_FEAT_MTE2 */ 206 207 #if ENABLE_FEAT_RAS 208 #define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg) 209 #define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 210 = (uint64_t) (val)) 211 #else 212 #define read_el1_ctx_ras(ctx, reg) ULL(0) 213 #define write_el1_ctx_ras(ctx, reg, val) 214 #endif /* ENABLE_FEAT_RAS */ 215 216 #if ENABLE_FEAT_S1PIE 217 #define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg) 218 #define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \ 219 = (uint64_t) (val)) 220 #else 221 #define read_el1_ctx_s1pie(ctx, reg) ULL(0) 222 #define write_el1_ctx_s1pie(ctx, reg, val) 223 #endif /* ENABLE_FEAT_S1PIE */ 224 225 #if ENABLE_FEAT_S1POE 226 #define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg) 227 #define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \ 228 = (uint64_t) (val)) 229 #else 230 #define read_el1_ctx_s1poe(ctx, reg) ULL(0) 231 #define write_el1_ctx_s1poe(ctx, reg, val) 232 #endif /* ENABLE_FEAT_S1POE */ 233 234 #if ENABLE_FEAT_S2POE 235 #define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg) 236 #define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \ 237 = (uint64_t) (val)) 238 #else 239 #define read_el1_ctx_s2poe(ctx, reg) ULL(0) 240 #define write_el1_ctx_s2poe(ctx, reg, val) 241 #endif /* ENABLE_FEAT_S2POE */ 242 243 #if ENABLE_FEAT_TCR2 244 #define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 245 #define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 246 = (uint64_t) (val)) 247 #else 248 #define read_el1_ctx_tcr2(ctx, reg) ULL(0) 249 #define write_el1_ctx_tcr2(ctx, reg, val) 250 #endif /* ENABLE_FEAT_TCR2 */ 251 252 #if ENABLE_TRF_FOR_NS 253 #define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg) 254 #define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 255 = (uint64_t) (val)) 256 #else 257 #define read_el1_ctx_trf(ctx, reg) ULL(0) 258 #define write_el1_ctx_trf(ctx, reg, val) 259 #endif /* ENABLE_TRF_FOR_NS */ 260 261 #if ENABLE_FEAT_CSV2_2 262 #define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg) 263 #define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \ 264 = (uint64_t) (val)) 265 #else 266 #define read_el1_ctx_csv2_2(ctx, reg) ULL(0) 267 #define write_el1_ctx_csv2_2(ctx, reg, val) 268 #endif /* ENABLE_FEAT_CSV2_2 */ 269 270 #if ENABLE_FEAT_GCS 271 #define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 272 #define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 273 = (uint64_t) (val)) 274 #else 275 #define read_el1_ctx_gcs(ctx, reg) ULL(0) 276 #define write_el1_ctx_gcs(ctx, reg, val) 277 #endif /* ENABLE_FEAT_GCS */ 278 279 #if ENABLE_FEAT_THE 280 #define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg) 281 #define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \ 282 = (uint64_t) (val)) 283 #else 284 #define read_el1_ctx_the(ctx, reg) ULL(0) 285 #define write_el1_ctx_the(ctx, reg, val) 286 #endif /* ENABLE_FEAT_THE */ 287 288 /******************************************************************************/ 289 #endif /* __ASSEMBLER__ */ 290 291 #endif /* CONTEXT_EL1_H */ 292