1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 184 Memory System Resource Partitioning and Monitoring (MPAM) 185 registers to be included when saving and restoring the CPU context. 186 Default is '0'. 187 188- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 189 registers to be saved/restored when entering/exiting an EL2 execution 190 context. This flag can take values 0 to 2, to align with the 191 ``ENABLE_FEAT`` mechanism. Default value is 0. 192 193- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 194 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 195 to be included when saving and restoring the CPU context as part of world 196 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 197 mechanism. Default value is 0. 198 199 Note that Pointer Authentication is enabled for Non-secure world irrespective 200 of the value of this flag if the CPU supports it. 201 202- ``DEBUG``: Chooses between a debug and release build. It can take either 0 203 (release) or 1 (debug) as values. 0 is the default. 204 205- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 206 authenticated decryption algorithm to be used to decrypt firmware/s during 207 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 208 this flag is ``none`` to disable firmware decryption which is an optional 209 feature as per TBBR. 210 211- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 212 of the binary image. If set to 1, then only the ELF image is built. 213 0 is the default. 214 215- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 216 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 217 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 218 mechanism. Default is ``0``. 219 220- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 221 Board Boot authentication at runtime. This option is meant to be enabled only 222 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 223 flag has to be enabled. 0 is the default. 224 225- ``E``: Boolean option to make warnings into errors. Default is 1. 226 227 When specifying higher warnings levels (``W=1`` and higher), this option 228 defaults to 0. This is done to encourage contributors to use them, as they 229 are expected to produce warnings that would otherwise fail the build. New 230 contributions are still expected to build with ``W=0`` and ``E=1`` (the 231 default). 232 233- ``EARLY_CONSOLE``: This option is used to enable early traces before default 234 console is properly setup. It introduces EARLY_* traces macros, that will 235 use the non-EARLY traces macros if the flag is enabled, or do nothing 236 otherwise. To use this feature, platforms will have to create the function 237 plat_setup_early_console(). 238 Default is 0 (disabled) 239 240- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 241 the normal boot flow. It must specify the entry point address of the EL3 242 payload. Please refer to the "Booting an EL3 payload" section for more 243 details. 244 245- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 246 (also known as group 1 counters). These are implementation-defined counters, 247 and as such require additional platform configuration. Default is 0. 248 249- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 250 allows platforms with auxiliary counters to describe them via the 251 ``HW_CONFIG`` device tree blob. Default is 0. 252 253- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 254 are compiled out. For debug builds, this option defaults to 1, and calls to 255 ``assert()`` are left in place. For release builds, this option defaults to 0 256 and calls to ``assert()`` function are compiled out. This option can be set 257 independently of ``DEBUG``. It can also be used to hide any auxiliary code 258 that is only required for the assertion and does not fit in the assertion 259 itself. 260 261- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 262 dumps or not. It is supported in both AArch64 and AArch32. However, in 263 AArch32 the format of the frame records are not defined in the AAPCS and they 264 are defined by the implementation. This implementation of backtrace only 265 supports the format used by GCC when T32 interworking is disabled. For this 266 reason enabling this option in AArch32 will force the compiler to only 267 generate A32 code. This option is enabled by default only in AArch64 debug 268 builds, but this behaviour can be overridden in each platform's Makefile or 269 in the build command line. 270 271- ``ENABLE_FEAT`` 272 The Arm architecture defines several architecture extension features, 273 named FEAT_xxx in the architecure manual. Some of those features require 274 setup code in higher exception levels, other features might be used by TF-A 275 code itself. 276 Most of the feature flags defined in the TF-A build system permit to take 277 the values 0, 1 or 2, with the following meaning: 278 279 :: 280 281 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 282 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 283 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 284 285 When setting the flag to 0, the feature is disabled during compilation, 286 and the compiler's optimisation stage and the linker will try to remove 287 as much of this code as possible. 288 If it is defined to 1, the code will use the feature unconditionally, so the 289 CPU is expected to support that feature. The FEATURE_DETECTION debug 290 feature, if enabled, will verify this. 291 If the feature flag is set to 2, support for the feature will be compiled 292 in, but its existence will be checked at runtime, so it works on CPUs with 293 or without the feature. This is mostly useful for platforms which either 294 support multiple different CPUs, or where the CPU is configured at runtime, 295 like in emulators. 296 297- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 298 extensions. This flag can take the values 0 to 2, to align with the 299 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 300 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 301 and this option can be used to enable this feature on those systems as well. 302 This flag can take the values 0 to 2, the default is 0. 303 304- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 305 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 306 onwards. This flag can take the values 0 to 2, to align with the 307 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 308 309- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 310 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 311 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 312 optional feature available on Arm v8.0 onwards. This flag can take values 313 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 314 Default value is ``0``. 315 316- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 317 extension. This feature is supported in AArch64 state only and is an optional 318 feature available in Arm v8.0 implementations. 319 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 320 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 321 mechanism. Default value is ``0``. 322 323- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 324 extension which allows the ability to implement more than 16 breakpoints 325 and/or watchpoints. This feature is mandatory from v8.9 and is optional 326 from v8.8. This flag can take the values of 0 to 2, to align with the 327 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 328 329- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 330 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 331 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 332 and upwards. This flag can take the values 0 to 2, to align with the 333 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 334 335- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 336 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 337 Physical Offset register) during EL2 to EL3 context save/restore operations. 338 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 339 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 340 mechanism. Default value is ``0``. 341 342- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 343 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 344 Read Trap Register) during EL2 to EL3 context save/restore operations. 345 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 346 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 347 mechanism. Default value is ``0``. 348 349- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 350 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 351 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 352 mandatory architectural feature and is enabled from v8.7 and upwards. This 353 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 354 mechanism. Default value is ``0``. 355 356- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 357 if the platform wants to use this feature and MTE2 is enabled at ELX. 358 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 359 mechanism. Default value is ``0``. 360 361- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 362 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 363 permission fault for any privileged data access from EL1/EL2 to virtual 364 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 365 mandatory architectural feature and is enabled from v8.1 and upwards. This 366 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 367 mechanism. Default value is ``0``. 368 369- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 370 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 371 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 372 mechanism. Default value is ``0``. 373 374- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 375 extension. This feature is only supported in AArch64 state. This flag can 376 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 377 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 378 Armv8.5 onwards. 379 380- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 381 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 382 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 383 later CPUs. It is enabled from v8.5 and upwards and if needed can be 384 overidden from platforms explicitly. 385 386- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 387 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 388 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 389 mechanism. Default is ``0``. 390 391- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 392 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 393 available on Arm v8.6. This flag can take values 0 to 2, to align with the 394 ``ENABLE_FEAT`` mechanism. Default is ``0``. 395 396 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 397 delayed by the amount of value in ``TWED_DELAY``. 398 399- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 400 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 401 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 402 architectural feature and is enabled from v8.1 and upwards. It can take 403 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 404 Default value is ``0``. 405 406- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 407 allow access to TCR2_EL2 (extended translation control) from EL2 as 408 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 409 mandatory architectural feature and is enabled from v8.9 and upwards. This 410 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 411 mechanism. Default value is ``0``. 412 413- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 414 at EL2 and below, and context switch relevant registers. This flag 415 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 416 mechanism. Default value is ``0``. 417 418- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 419 at EL2 and below, and context switch relevant registers. This flag 420 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 421 mechanism. Default value is ``0``. 422 423- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 424 at EL2 and below, and context switch relevant registers. This flag 425 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 426 mechanism. Default value is ``0``. 427 428- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 429 at EL2 and below, and context switch relevant registers. This flag 430 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 431 mechanism. Default value is ``0``. 432 433- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 434 allow use of Guarded Control Stack from EL2 as well as adding the GCS 435 registers to the EL2 context save/restore operations. This flag can take 436 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 437 Default value is ``0``. 438 439- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 440 support in GCC for TF-A. This option is currently only supported for 441 AArch64. Default is 0. 442 443- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 444 feature. MPAM is an optional Armv8.4 extension that enables various memory 445 system components and resources to define partitions; software running at 446 various ELs can assign themselves to desired partition to control their 447 performance aspects. 448 449 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 450 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 451 access their own MPAM registers without trapping into EL3. This option 452 doesn't make use of partitioning in EL3, however. Platform initialisation 453 code should configure and use partitions in EL3 as required. This option 454 defaults to ``2`` since MPAM is enabled by default for NS world only. 455 The flag is automatically disabled when the target 456 architecture is AArch32. 457 458- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 459 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 460 firmware to detect and limit high activity events to assist in SoC processor 461 power domain dynamic power budgeting and limit the triggering of whole-rail 462 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 463 464- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 465 allows platforms with cores supporting MPMM to describe them via the 466 ``HW_CONFIG`` device tree blob. Default is 0. 467 468- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 469 support within generic code in TF-A. This option is currently only supported 470 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 471 in BL32 (SP_min) for AARCH32. Default is 0. 472 473- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 474 Measurement Framework(PMF). Default is 0. 475 476- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 477 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 478 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 479 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 480 software. 481 482- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 483 instrumentation which injects timestamp collection points into TF-A to 484 allow runtime performance to be measured. Currently, only PSCI is 485 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 486 as well. Default is 0. 487 488- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 489 extensions. This is an optional architectural feature for AArch64. 490 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 491 mechanism. The default is 2 but is automatically disabled when the target 492 architecture is AArch32. 493 494- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 495 (SVE) for the Non-secure world only. SVE is an optional architectural feature 496 for AArch64. Note that when SVE is enabled for the Non-secure world, access 497 to SIMD and floating-point functionality from the Secure world is disabled by 498 default and controlled with ENABLE_SVE_FOR_SWD. 499 This is to avoid corruption of the Non-secure world data in the Z-registers 500 which are aliased by the SIMD and FP registers. The build option is not 501 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 502 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 503 enabled. This flag can take the values 0 to 2, to align with the 504 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 505 used on systems that have SPM_MM enabled. The default is 1. 506 507- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 508 SVE is an optional architectural feature for AArch64. Note that this option 509 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 510 automatically disabled when the target architecture is AArch32. 511 512- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 513 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 514 default value is set to "none". "strong" is the recommended stack protection 515 level if this feature is desired. "none" disables the stack protection. For 516 all values other than "none", the ``plat_get_stack_protector_canary()`` 517 platform hook needs to be implemented. The value is passed as the last 518 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 519 520- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 521 flag depends on ``DECRYPTION_SUPPORT`` build flag. 522 523- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 524 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 525 526- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 527 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 528 on ``DECRYPTION_SUPPORT`` build flag. 529 530- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 531 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 532 build flag. 533 534- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 535 deprecated platform APIs, helper functions or drivers within Trusted 536 Firmware as error. It can take the value 1 (flag the use of deprecated 537 APIs as error) or 0. The default is 0. 538 539- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 540 configure an Arm® Ethos™-N NPU. To use this service the target platform's 541 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 542 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 543 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 544 545- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 546 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 547 ``TRUSTED_BOARD_BOOT`` to be enabled. 548 549- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 550 (```ethosn.bin```). This firmware image will be included in the FIP and 551 loaded at runtime. 552 553- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 554 targeted at EL3. When set ``0`` (default), no exceptions are expected or 555 handled at EL3, and a panic will result. The exception to this rule is when 556 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 557 occuring during normal world execution, are trapped to EL3. Any exception 558 trapped during secure world execution are trapped to the SPMC. This is 559 supported only for AArch64 builds. 560 561- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 562 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 563 Default value is 40 (LOG_LEVEL_INFO). 564 565- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 566 injection from lower ELs, and this build option enables lower ELs to use 567 Error Records accessed via System Registers to inject faults. This is 568 applicable only to AArch64 builds. 569 570 This feature is intended for testing purposes only, and is advisable to keep 571 disabled for production images. 572 573- ``FIP_NAME``: This is an optional build option which specifies the FIP 574 filename for the ``fip`` target. Default is ``fip.bin``. 575 576- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 577 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 578 579- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 580 581 :: 582 583 0: Encryption is done with Secret Symmetric Key (SSK) which is common 584 for a class of devices. 585 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 586 unique per device. 587 588 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 589 590- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 591 tool to create certificates as per the Chain of Trust described in 592 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 593 include the certificates in the FIP and FWU_FIP. Default value is '0'. 594 595 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 596 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 597 the corresponding certificates, and to include those certificates in the 598 FIP and FWU_FIP. 599 600 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 601 images will not include support for Trusted Board Boot. The FIP will still 602 include the corresponding certificates. This FIP can be used to verify the 603 Chain of Trust on the host machine through other mechanisms. 604 605 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 606 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 607 will not include the corresponding certificates, causing a boot failure. 608 609- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 610 inherent support for specific EL3 type interrupts. Setting this build option 611 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 612 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 613 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 614 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 615 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 616 the Secure Payload interrupts needs to be synchronously handed over to Secure 617 EL1 for handling. The default value of this option is ``0``, which means the 618 Group 0 interrupts are assumed to be handled by Secure EL1. 619 620- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 621 Interrupts, resulting from errors in NS world, will be always trapped in 622 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 623 will be trapped in the current exception level (or in EL1 if the current 624 exception level is EL0). 625 626- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 627 software operations are required for CPUs to enter and exit coherency. 628 However, newer systems exist where CPUs' entry to and exit from coherency 629 is managed in hardware. Such systems require software to only initiate these 630 operations, and the rest is managed in hardware, minimizing active software 631 management. In such systems, this boolean option enables TF-A to carry out 632 build and run-time optimizations during boot and power management operations. 633 This option defaults to 0 and if it is enabled, then it implies 634 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 635 636 If this flag is disabled while the platform which TF-A is compiled for 637 includes cores that manage coherency in hardware, then a compilation error is 638 generated. This is based on the fact that a system cannot have, at the same 639 time, cores that manage coherency in hardware and cores that don't. In other 640 words, a platform cannot have, at the same time, cores that require 641 ``HW_ASSISTED_COHERENCY=1`` and cores that require 642 ``HW_ASSISTED_COHERENCY=0``. 643 644 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 645 translation library (xlat tables v2) must be used; version 1 of translation 646 library is not supported. 647 648- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 649 implementation defined system register accesses from lower ELs. Default 650 value is ``0``. 651 652- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 653 bottom, higher addresses at the top. This build flag can be set to '1' to 654 invert this behavior. Lower addresses will be printed at the top and higher 655 addresses at the bottom. 656 657- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 658 used for generating the PKCS keys and subsequent signing of the certificate. 659 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 660 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 661 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 662 compatibility. The default value of this flag is ``rsa`` which is the TBBR 663 compliant PKCS#1 RSA 2.1 scheme. 664 665- ``KEY_SIZE``: This build flag enables the user to select the key size for 666 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 667 depend on the chosen algorithm and the cryptographic module. 668 669 +---------------------------+------------------------------------+ 670 | KEY_ALG | Possible key sizes | 671 +===========================+====================================+ 672 | rsa | 1024 , 2048 (default), 3072, 4096 | 673 +---------------------------+------------------------------------+ 674 | ecdsa | 256 (default), 384 | 675 +---------------------------+------------------------------------+ 676 | ecdsa-brainpool-regular | unavailable | 677 +---------------------------+------------------------------------+ 678 | ecdsa-brainpool-twisted | unavailable | 679 +---------------------------+------------------------------------+ 680 681- ``HASH_ALG``: This build flag enables the user to select the secure hash 682 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 683 The default value of this flag is ``sha256``. 684 685- ``LDFLAGS``: Extra user options appended to the linkers' command line in 686 addition to the one set by the build system. 687 688- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 689 output compiled into the build. This should be one of the following: 690 691 :: 692 693 0 (LOG_LEVEL_NONE) 694 10 (LOG_LEVEL_ERROR) 695 20 (LOG_LEVEL_NOTICE) 696 30 (LOG_LEVEL_WARNING) 697 40 (LOG_LEVEL_INFO) 698 50 (LOG_LEVEL_VERBOSE) 699 700 All log output up to and including the selected log level is compiled into 701 the build. The default value is 40 in debug builds and 20 in release builds. 702 703- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 704 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 705 provide trust that the code taking the measurements and recording them has 706 not been tampered with. 707 708 This option defaults to 0. 709 710- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 711 options to the compiler. An example usage: 712 713 .. code:: make 714 715 MARCH_DIRECTIVE := -march=armv8.5-a 716 717- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 718 options to the compiler currently supporting only of the options. 719 GCC documentation: 720 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 721 722 An example usage: 723 724 .. code:: make 725 726 HARDEN_SLS := 1 727 728 This option defaults to 0. 729 730- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 731 specifies a file that contains the Non-Trusted World private key in PEM 732 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 733 will be used to save the key. 734 735- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 736 optional. It is only needed if the platform makefile specifies that it 737 is required in order to build the ``fwu_fip`` target. 738 739- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 740 contents upon world switch. It can take either 0 (don't save and restore) or 741 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 742 wants the timer registers to be saved and restored. 743 744- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 745 for the BL image. It can be either 0 (include) or 1 (remove). The default 746 value is 0. 747 748- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 749 the underlying hardware is not a full PL011 UART but a minimally compliant 750 generic UART, which is a subset of the PL011. The driver will not access 751 any register that is not part of the SBSA generic UART specification. 752 Default value is 0 (a full PL011 compliant UART is present). 753 754- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 755 must be subdirectory of any depth under ``plat/``, and must contain a 756 platform makefile named ``platform.mk``. For example, to build TF-A for the 757 Arm Juno board, select PLAT=juno. 758 759- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 760 each core as well as the global context. The data includes the memory used 761 by each world and each privileged exception level. This build option is 762 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 763 764- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 765 instead of the normal boot flow. When defined, it must specify the entry 766 point address for the preloaded BL33 image. This option is incompatible with 767 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 768 over ``PRELOADED_BL33_BASE``. 769 770- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 771 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 772 registers when the cluster goes through a power cycle. This is disabled by 773 default and platforms that require this feature have to enable them. 774 775- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 776 vector address can be programmed or is fixed on the platform. It can take 777 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 778 programmable reset address, it is expected that a CPU will start executing 779 code directly at the right address, both on a cold and warm reset. In this 780 case, there is no need to identify the entrypoint on boot and the boot path 781 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 782 does not need to be implemented in this case. 783 784- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 785 possible for the PSCI power-state parameter: original and extended State-ID 786 formats. This flag if set to 1, configures the generic PSCI layer to use the 787 extended format. The default value of this flag is 0, which means by default 788 the original power-state format is used by the PSCI implementation. This flag 789 should be specified by the platform makefile and it governs the return value 790 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 791 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 792 set to 1 as well. 793 794- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 795 OS-initiated mode. This option defaults to 0. 796 797- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 798 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 799 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 800 NOTE: This flag enables use of IESB capability to reduce entry latency into 801 EL3 even when RAS error handling is not performed on the platform. Hence this 802 flag is recommended to be turned on Armv8.2 and later CPUs. 803 804- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 805 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 806 entrypoint) or 1 (CPU reset to BL31 entrypoint). 807 The default value is 0. 808 809- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 810 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 811 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 812 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 813 814- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 815- blocks) covered by a single bit of the bitlock structure during RME GPT 816- operations. The lower the block size, the better opportunity for 817- parallelising GPT operations but at the cost of more bits being needed 818- for the bitlock structure. This numeric parameter can take the values 819- from 0 to 512 and must be a power of 2. The value of 0 is special and 820- and it chooses a single spinlock for all GPT L1 table entries. Default 821- value is 1 which corresponds to block size of 512MB per bit of bitlock 822- structure. 823 824- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 825 supported contiguous blocks in GPT Library. This parameter can take the 826 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 827 descriptors. Default value is 2. 828 829- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 830 file that contains the ROT private key in PEM format or a PKCS11 URI and 831 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 832 accepted and it will be used to save the key. 833 834- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 835 certificate generation tool to save the keys used to establish the Chain of 836 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 837 838- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 839 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 840 target. 841 842- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 843 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 844 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 845 846- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 847 optional. It is only needed if the platform makefile specifies that it 848 is required in order to build the ``fwu_fip`` target. 849 850- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 851 Delegated Exception Interface to BL31 image. This defaults to ``0``. 852 853 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 854 set to ``1``. 855 856- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 857 isolated on separate memory pages. This is a trade-off between security and 858 memory usage. See "Isolating code and read-only data on separate memory 859 pages" section in :ref:`Firmware Design`. This flag is disabled by default 860 and affects all BL images. 861 862- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 863 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 864 allocated in RAM discontiguous from the loaded firmware image. When set, the 865 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 866 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 867 sections are placed in RAM immediately following the loaded firmware image. 868 869- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 870 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 871 discontiguous from loaded firmware images. When set, the platform need to 872 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 873 flag is disabled by default and NOLOAD sections are placed in RAM immediately 874 following the loaded firmware image. 875 876- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 877 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 878 UEFI+ACPI this can provide a certain amount of OS forward compatibility 879 with newer platforms that aren't ECAM compliant. 880 881- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 882 This build option is only valid if ``ARCH=aarch64``. The value should be 883 the path to the directory containing the SPD source, relative to 884 ``services/spd/``; the directory is expected to contain a makefile called 885 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 886 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 887 cannot be enabled when the ``SPM_MM`` option is enabled. 888 889- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 890 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 891 execution in BL1 just before handing over to BL31. At this point, all 892 firmware images have been loaded in memory, and the MMU and caches are 893 turned off. Refer to the "Debugging options" section for more details. 894 895- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 896 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 897 component runs at the EL3 exception level. The default value is ``0`` ( 898 disabled). This configuration supports pre-Armv8.4 platforms (aka not 899 implementing the ``FEAT_SEL2`` extension). 900 901- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 902 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 903 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 904 905- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 906 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 907 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 908 mechanism should be used. 909 910- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 911 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 912 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 913 extension. This is the default when enabling the SPM Dispatcher. When 914 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 915 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 916 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 917 extension). 918 919- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 920 Partition Manager (SPM) implementation. The default value is ``0`` 921 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 922 enabled (``SPD=spmd``). 923 924- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 925 description of secure partitions. The build system will parse this file and 926 package all secure partition blobs into the FIP. This file is not 927 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 928 929- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 930 secure interrupts (caught through the FIQ line). Platforms can enable 931 this directive if they need to handle such interruption. When enabled, 932 the FIQ are handled in monitor mode and non secure world is not allowed 933 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 934 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 935 936- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 937 Platforms can configure this if they need to lower the hardware 938 limit, for example due to asymmetric configuration or limitations of 939 software run at lower ELs. The default is the architectural maximum 940 of 2048 which should be suitable for most configurations, the 941 hardware will limit the effective VL to the maximum physically supported 942 VL. 943 944- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 945 Random Number Generator Interface to BL31 image. This defaults to ``0``. 946 947- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 948 Boot feature. When set to '1', BL1 and BL2 images include support to load 949 and verify the certificates and images in a FIP, and BL1 includes support 950 for the Firmware Update. The default value is '0'. Generation and inclusion 951 of certificates in the FIP and FWU_FIP depends upon the value of the 952 ``GENERATE_COT`` option. 953 954 .. warning:: 955 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 956 already exist in disk, they will be overwritten without further notice. 957 958- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 959 specifies a file that contains the Trusted World private key in PEM 960 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 961 it will be used to save the key. 962 963- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 964 synchronous, (see "Initializing a BL32 Image" section in 965 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 966 synchronous method) or 1 (BL32 is initialized using asynchronous method). 967 Default is 0. 968 969- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 970 routing model which routes non-secure interrupts asynchronously from TSP 971 to EL3 causing immediate preemption of TSP. The EL3 is responsible 972 for saving and restoring the TSP context in this routing model. The 973 default routing model (when the value is 0) is to route non-secure 974 interrupts to TSP allowing it to save its context and hand over 975 synchronously to EL3 via an SMC. 976 977 .. note:: 978 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 979 must also be set to ``1``. 980 981- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 982 internal-trusted-storage) as SP in tb_fw_config device tree. 983 984- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 985 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 986 this delay. It can take values in the range (0-15). Default value is ``0`` 987 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 988 Platforms need to explicitly update this value based on their requirements. 989 990- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 991 linker. When the ``LINKER`` build variable points to the armlink linker, 992 this flag is enabled automatically. To enable support for armlink, platforms 993 will have to provide a scatter file for the BL image. Currently, Tegra 994 platforms use the armlink support to compile BL3-1 images. 995 996- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 997 memory region in the BL memory map or not (see "Use of Coherent memory in 998 TF-A" section in :ref:`Firmware Design`). It can take the value 1 999 (Coherent memory region is included) or 0 (Coherent memory region is 1000 excluded). Default is 1. 1001 1002- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1003 firmware configuration framework. This will move the io_policies into a 1004 configuration device tree, instead of static structure in the code base. 1005 1006- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1007 at runtime using fconf. If this flag is enabled, COT descriptors are 1008 statically captured in tb_fw_config file in the form of device tree nodes 1009 and properties. Currently, COT descriptors used by BL2 are moved to the 1010 device tree and COT descriptors used by BL1 are retained in the code 1011 base statically. 1012 1013- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1014 runtime using firmware configuration framework. The platform specific SDEI 1015 shared and private events configuration is retrieved from device tree rather 1016 than static C structures at compile time. This is only supported if 1017 SDEI_SUPPORT build flag is enabled. 1018 1019- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1020 and Group1 secure interrupts using the firmware configuration framework. The 1021 platform specific secure interrupt property descriptor is retrieved from 1022 device tree in runtime rather than depending on static C structure at compile 1023 time. 1024 1025- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1026 This feature creates a library of functions to be placed in ROM and thus 1027 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1028 is 0. 1029 1030- ``V``: Verbose build. If assigned anything other than 0, the build commands 1031 are printed. Default is 0. 1032 1033- ``VERSION_STRING``: String used in the log output for each TF-A image. 1034 Defaults to a string formed by concatenating the version number, build type 1035 and build string. 1036 1037- ``W``: Warning level. Some compiler warning options of interest have been 1038 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1039 each level enabling more warning options. Default is 0. 1040 1041 This option is closely related to the ``E`` option, which enables 1042 ``-Werror``. 1043 1044 - ``W=0`` (default) 1045 1046 Enables a wide assortment of warnings, most notably ``-Wall`` and 1047 ``-Wextra``, as well as various bad practices and things that are likely to 1048 result in errors. Includes some compiler specific flags. No warnings are 1049 expected at this level for any build. 1050 1051 - ``W=1`` 1052 1053 Enables warnings we want the generic build to include but are too time 1054 consuming to fix at the moment. It re-enables warnings taken out for 1055 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1056 to eventually be merged into ``W=0``. Some warnings are expected on some 1057 builds, but new contributions should not introduce new ones. 1058 1059 - ``W=2`` (recommended) 1060 1061 Enables warnings we want the generic build to include but cannot be enabled 1062 due to external libraries. This level is expected to eventually be merged 1063 into ``W=0``. Lots of warnings are expected, primarily from external 1064 libraries like zlib and compiler-rt, but new controbutions should not 1065 introduce new ones. 1066 1067 - ``W=3`` 1068 1069 Enables warnings that are informative but not necessary and generally too 1070 verbose and frequently ignored. A very large number of warnings are 1071 expected. 1072 1073 The exact set of warning flags depends on the compiler and TF-A warning 1074 level, however they are all succinctly set in the top-level Makefile. Please 1075 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1076 individual flags. 1077 1078- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1079 the CPU after warm boot. This is applicable for platforms which do not 1080 require interconnect programming to enable cache coherency (eg: single 1081 cluster platforms). If this option is enabled, then warm boot path 1082 enables D-caches immediately after enabling MMU. This option defaults to 0. 1083 1084- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1085 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1086 default value of this flag is ``no``. Note this option must be enabled only 1087 for ARM architecture greater than Armv8.5-A. 1088 1089- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1090 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1091 The default value of this flag is ``0``. 1092 1093 ``AT`` speculative errata workaround disables stage1 page table walk for 1094 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1095 produces either the correct result or failure without TLB allocation. 1096 1097 This boolean option enables errata for all below CPUs. 1098 1099 +---------+--------------+-------------------------+ 1100 | Errata | CPU | Workaround Define | 1101 +=========+==============+=========================+ 1102 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1103 +---------+--------------+-------------------------+ 1104 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1105 +---------+--------------+-------------------------+ 1106 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1107 +---------+--------------+-------------------------+ 1108 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1109 +---------+--------------+-------------------------+ 1110 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1111 +---------+--------------+-------------------------+ 1112 1113 .. note:: 1114 This option is enabled by build only if platform sets any of above defines 1115 mentioned in ’Workaround Define' column in the table. 1116 If this option is enabled for the EL3 software then EL2 software also must 1117 implement this workaround due to the behaviour of the errata mentioned 1118 in new SDEN document which will get published soon. 1119 1120- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1121 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1122 This flag is disabled by default. 1123 1124- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1125 host machine where a custom installation of OpenSSL is located, which is used 1126 to build the certificate generation, firmware encryption and FIP tools. If 1127 this option is not set, the default OS installation will be used. 1128 1129- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1130 functions that wait for an arbitrary time length (udelay and mdelay). The 1131 default value is 0. 1132 1133- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1134 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1135 optional architectural feature for AArch64. This flag can take the values 1136 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1137 and it is automatically disabled when the target architecture is AArch32. 1138 1139- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1140 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1141 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1142 feature for AArch64. This flag can take the values 0 to 2, to align with the 1143 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1144 disabled when the target architecture is AArch32. 1145 1146- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1147 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1148 but unused). This feature is available if trace unit such as ETMv4.x, and 1149 ETE(extending ETM feature) is implemented. This flag can take the values 1150 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1151 1152- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1153 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1154 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1155 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1156 1157- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1158 ``plat_can_cmo`` which will return zero if cache management operations should 1159 be skipped and non-zero otherwise. By default, this option is disabled which 1160 means platform hook won't be checked and CMOs will always be performed when 1161 related functions are called. 1162 1163- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1164 firmware interface for the BL31 image. By default its disabled (``0``). 1165 1166- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1167 errata mitigation for platforms with a non-arm interconnect using the errata 1168 ABI. By default its disabled (``0``). 1169 1170- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1171 driver(s). By default it is disabled (``0``) because it constitutes an attack 1172 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1173 This option should only be enabled on a need basis if there is a use case for 1174 reading characters from the console. 1175 1176GICv3 driver options 1177-------------------- 1178 1179GICv3 driver files are included using directive: 1180 1181``include drivers/arm/gic/v3/gicv3.mk`` 1182 1183The driver can be configured with the following options set in the platform 1184makefile: 1185 1186- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1187 Enabling this option will add runtime detection support for the 1188 GIC-600, so is safe to select even for a GIC500 implementation. 1189 This option defaults to 0. 1190 1191- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1192 for GIC-600 AE. Enabling this option will introduce support to initialize 1193 the FMU. Platforms should call the init function during boot to enable the 1194 FMU and its safety mechanisms. This option defaults to 0. 1195 1196- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1197 functionality. This option defaults to 0 1198 1199- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1200 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1201 functions. This is required for FVP platform which need to simulate GIC save 1202 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1203 1204- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1205 This option defaults to 0. 1206 1207- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1208 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1209 1210Debugging options 1211----------------- 1212 1213To compile a debug version and make the build more verbose use 1214 1215.. code:: shell 1216 1217 make PLAT=<platform> DEBUG=1 V=1 all 1218 1219AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1220(for example Arm-DS) might not support this and may need an older version of 1221DWARF symbols to be emitted by GCC. This can be achieved by using the 1222``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1223the version to 4 is recommended for Arm-DS. 1224 1225When debugging logic problems it might also be useful to disable all compiler 1226optimizations by using ``-O0``. 1227 1228.. warning:: 1229 Using ``-O0`` could cause output images to be larger and base addresses 1230 might need to be recalculated (see the **Memory layout on Arm development 1231 platforms** section in the :ref:`Firmware Design`). 1232 1233Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1234``LDFLAGS``: 1235 1236.. code:: shell 1237 1238 CFLAGS='-O0 -gdwarf-2' \ 1239 make PLAT=<platform> DEBUG=1 V=1 all 1240 1241Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1242ignored as the linker is called directly. 1243 1244It is also possible to introduce an infinite loop to help in debugging the 1245post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1246``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1247section. In this case, the developer may take control of the target using a 1248debugger when indicated by the console output. When using Arm-DS, the following 1249commands can be used: 1250 1251:: 1252 1253 # Stop target execution 1254 interrupt 1255 1256 # 1257 # Prepare your debugging environment, e.g. set breakpoints 1258 # 1259 1260 # Jump over the debug loop 1261 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1262 1263 # Resume execution 1264 continue 1265 1266.. _build_options_experimental: 1267 1268Experimental build options 1269--------------------------- 1270 1271Common build options 1272~~~~~~~~~~~~~~~~~~~~ 1273 1274- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1275 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1276 set to ``1`` then measurements and additional metadata collected during the 1277 measured boot process are sent to the DICE Protection Environment for storage 1278 and processing. A certificate chain, which represents the boot state of the 1279 device, can be queried from the DPE. 1280 1281- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1282 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1283 the measurements and recording them as per `PSA DRTM specification`_. For 1284 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1285 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1286 should have mechanism to authenticate BL31. This option defaults to 0. 1287 1288- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1289 Management Extension. This flag can take the values 0 to 2, to align with 1290 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1291 1292- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1293 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1294 registers so are enabled together. Using this option without 1295 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1296 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1297 superset of SVE. SME is an optional architectural feature for AArch64. 1298 At this time, this build option cannot be used on systems that have 1299 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1300 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1301 mechanism. Default is 0. 1302 1303- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1304 version 2 (SME2) for the non-secure world only. SME2 is an optional 1305 architectural feature for AArch64. 1306 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1307 accesses will still be trapped. This flag can take the values 0 to 2, to 1308 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1309 1310- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1311 Extension for secure world. Used along with SVE and FPU/SIMD. 1312 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1313 Default is 0. 1314 1315- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1316 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1317 for logical partitions in EL3, managed by the SPMD as defined in the 1318 FF-A v1.2 specification. This flag is disabled by default. This flag 1319 must not be used if ``SPMC_AT_EL3`` is enabled. 1320 1321- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1322 verification mechanism. This is a debug feature that compares the 1323 architectural features enabled through the feature specific build flags 1324 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1325 and reports any discrepancies. 1326 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1327 1328 It is expected that this feature is only used for flexible platforms like 1329 software emulators, or for hardware platforms at bringup time, to verify 1330 that the configured feature set matches the CPU. 1331 The ``FEATURE_DETECTION`` macro is disabled by default. 1332 1333- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1334 The platform will use PSA compliant Crypto APIs during authentication and 1335 image measurement process by enabling this option. It uses APIs defined as 1336 per the `PSA Crypto API specification`_. This feature is only supported if 1337 using MbedTLS 3.x version. It is disabled (``0``) by default. 1338 1339- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1340 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1341 This defaults to ``0``. Current implementation follows the Firmware Handoff 1342 specification v0.9. 1343 1344- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1345 interface through BL31 as a SiP SMC function. 1346 Default is disabled (0). 1347 1348Firmware update options 1349~~~~~~~~~~~~~~~~~~~~~~~ 1350 1351- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1352 `PSA FW update specification`_. The default value is 0. 1353 PSA firmware update implementation has few limitations, such as: 1354 1355 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1356 be updated, then it should be done through another platform-defined 1357 mechanism. 1358 1359 - It assumes the platform's hardware supports CRC32 instructions. 1360 1361- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1362 in defining the firmware update metadata structure. This flag is by default 1363 set to '2'. 1364 1365- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1366 firmware bank. Each firmware bank must have the same number of images as per 1367 the `PSA FW update specification`_. 1368 This flag is used in defining the firmware update metadata structure. This 1369 flag is by default set to '1'. 1370 1371- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1372 metadata contains image description. The default value is 1. 1373 1374 The version 2 of the FWU metadata allows for an opaque metadata 1375 structure where a platform can choose to not include the firmware 1376 store description in the metadata structure. This option indicates 1377 if the firmware store description, which provides information on 1378 the updatable images is part of the structure. 1379 1380-------------- 1381 1382*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1383 1384.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1385.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1386.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1387.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1388.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1389.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1390.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1391