1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 184 Memory System Resource Partitioning and Monitoring (MPAM) 185 registers to be included when saving and restoring the CPU context. 186 Default is '0'. 187 188- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 189 registers to be saved/restored when entering/exiting an EL2 execution 190 context. This flag can take values 0 to 2, to align with the 191 ``ENABLE_FEAT`` mechanism. Default value is 0. 192 193- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 194 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 195 to be included when saving and restoring the CPU context as part of world 196 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 197 mechanism. Default value is 0. 198 199 Note that Pointer Authentication is enabled for Non-secure world irrespective 200 of the value of this flag if the CPU supports it. 201 202- ``DEBUG``: Chooses between a debug and release build. It can take either 0 203 (release) or 1 (debug) as values. 0 is the default. 204 205- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 206 authenticated decryption algorithm to be used to decrypt firmware/s during 207 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 208 this flag is ``none`` to disable firmware decryption which is an optional 209 feature as per TBBR. 210 211- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 212 of the binary image. If set to 1, then only the ELF image is built. 213 0 is the default. 214 215- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 216 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 217 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 218 mechanism. Default is ``0``. 219 220- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 221 Board Boot authentication at runtime. This option is meant to be enabled only 222 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 223 flag has to be enabled. 0 is the default. 224 225- ``E``: Boolean option to make warnings into errors. Default is 1. 226 227 When specifying higher warnings levels (``W=1`` and higher), this option 228 defaults to 0. This is done to encourage contributors to use them, as they 229 are expected to produce warnings that would otherwise fail the build. New 230 contributions are still expected to build with ``W=0`` and ``E=1`` (the 231 default). 232 233- ``EARLY_CONSOLE``: This option is used to enable early traces before default 234 console is properly setup. It introduces EARLY_* traces macros, that will 235 use the non-EARLY traces macros if the flag is enabled, or do nothing 236 otherwise. To use this feature, platforms will have to create the function 237 plat_setup_early_console(). 238 Default is 0 (disabled) 239 240- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 241 the normal boot flow. It must specify the entry point address of the EL3 242 payload. Please refer to the "Booting an EL3 payload" section for more 243 details. 244 245- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 246 (also known as group 1 counters). These are implementation-defined counters, 247 and as such require additional platform configuration. Default is 0. 248 249- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 250 allows platforms with auxiliary counters to describe them via the 251 ``HW_CONFIG`` device tree blob. Default is 0. 252 253- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 254 are compiled out. For debug builds, this option defaults to 1, and calls to 255 ``assert()`` are left in place. For release builds, this option defaults to 0 256 and calls to ``assert()`` function are compiled out. This option can be set 257 independently of ``DEBUG``. It can also be used to hide any auxiliary code 258 that is only required for the assertion and does not fit in the assertion 259 itself. 260 261- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 262 dumps or not. It is supported in both AArch64 and AArch32. However, in 263 AArch32 the format of the frame records are not defined in the AAPCS and they 264 are defined by the implementation. This implementation of backtrace only 265 supports the format used by GCC when T32 interworking is disabled. For this 266 reason enabling this option in AArch32 will force the compiler to only 267 generate A32 code. This option is enabled by default only in AArch64 debug 268 builds, but this behaviour can be overridden in each platform's Makefile or 269 in the build command line. 270 271- ``ENABLE_FEAT`` 272 The Arm architecture defines several architecture extension features, 273 named FEAT_xxx in the architecure manual. Some of those features require 274 setup code in higher exception levels, other features might be used by TF-A 275 code itself. 276 Most of the feature flags defined in the TF-A build system permit to take 277 the values 0, 1 or 2, with the following meaning: 278 279 :: 280 281 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 282 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 283 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 284 285 When setting the flag to 0, the feature is disabled during compilation, 286 and the compiler's optimisation stage and the linker will try to remove 287 as much of this code as possible. 288 If it is defined to 1, the code will use the feature unconditionally, so the 289 CPU is expected to support that feature. The FEATURE_DETECTION debug 290 feature, if enabled, will verify this. 291 If the feature flag is set to 2, support for the feature will be compiled 292 in, but its existence will be checked at runtime, so it works on CPUs with 293 or without the feature. This is mostly useful for platforms which either 294 support multiple different CPUs, or where the CPU is configured at runtime, 295 like in emulators. 296 297- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 298 extensions. This flag can take the values 0 to 2, to align with the 299 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 300 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 301 and this option can be used to enable this feature on those systems as well. 302 This flag can take the values 0 to 2, the default is 0. 303 304- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 305 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 306 onwards. This flag can take the values 0 to 2, to align with the 307 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 308 309- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 310 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 311 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 312 optional feature available on Arm v8.0 onwards. This flag can take values 313 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 314 Default value is ``0``. 315 316- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 317 extension. This feature is supported in AArch64 state only and is an optional 318 feature available in Arm v8.0 implementations. 319 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 320 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 321 mechanism. Default value is ``0``. 322 323- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 324 extension which allows the ability to implement more than 16 breakpoints 325 and/or watchpoints. This feature is mandatory from v8.9 and is optional 326 from v8.8. This flag can take the values of 0 to 2, to align with the 327 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 328 329- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 330 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 331 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 332 and upwards. This flag can take the values 0 to 2, to align with the 333 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 334 335- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 336 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 337 Physical Offset register) during EL2 to EL3 context save/restore operations. 338 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 339 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 340 mechanism. Default value is ``0``. 341 342- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 343 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 344 Read Trap Register) during EL2 to EL3 context save/restore operations. 345 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 346 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 347 mechanism. Default value is ``0``. 348 349- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 350 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 351 during EL2 to EL3 context save/restore operations. 352 Its an optional architectural feature and is available from v8.8 and upwards. 353 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 354 mechanism. Default value is ``0``. 355 356- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 357 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 358 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 359 mandatory architectural feature and is enabled from v8.7 and upwards. This 360 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 361 mechanism. Default value is ``0``. 362 363- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 364 if the platform wants to use this feature and MTE2 is enabled at ELX. 365 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 366 mechanism. Default value is ``0``. 367 368- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 369 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 370 permission fault for any privileged data access from EL1/EL2 to virtual 371 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 372 mandatory architectural feature and is enabled from v8.1 and upwards. This 373 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 374 mechanism. Default value is ``0``. 375 376- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 377 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 378 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 379 mechanism. Default value is ``0``. 380 381- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 382 extension. This feature is only supported in AArch64 state. This flag can 383 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 384 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 385 Armv8.5 onwards. 386 387- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 388 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 389 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 390 later CPUs. It is enabled from v8.5 and upwards and if needed can be 391 overidden from platforms explicitly. 392 393- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 394 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 395 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 396 mechanism. Default is ``0``. 397 398- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 399 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 400 available on Arm v8.6. This flag can take values 0 to 2, to align with the 401 ``ENABLE_FEAT`` mechanism. Default is ``0``. 402 403 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 404 delayed by the amount of value in ``TWED_DELAY``. 405 406- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 407 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 408 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 409 architectural feature and is enabled from v8.1 and upwards. It can take 410 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 411 Default value is ``0``. 412 413- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 414 allow access to TCR2_EL2 (extended translation control) from EL2 as 415 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 416 mandatory architectural feature and is enabled from v8.9 and upwards. This 417 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 418 mechanism. Default value is ``0``. 419 420- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 421 at EL2 and below, and context switch relevant registers. This flag 422 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 423 mechanism. Default value is ``0``. 424 425- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 426 at EL2 and below, and context switch relevant registers. This flag 427 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 428 mechanism. Default value is ``0``. 429 430- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 431 at EL2 and below, and context switch relevant registers. This flag 432 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 433 mechanism. Default value is ``0``. 434 435- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 436 at EL2 and below, and context switch relevant registers. This flag 437 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 438 mechanism. Default value is ``0``. 439 440- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 441 allow use of Guarded Control Stack from EL2 as well as adding the GCS 442 registers to the EL2 context save/restore operations. This flag can take 443 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 444 Default value is ``0``. 445 446- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 447 support in GCC for TF-A. This option is currently only supported for 448 AArch64. Default is 0. 449 450- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 451 feature. MPAM is an optional Armv8.4 extension that enables various memory 452 system components and resources to define partitions; software running at 453 various ELs can assign themselves to desired partition to control their 454 performance aspects. 455 456 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 457 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 458 access their own MPAM registers without trapping into EL3. This option 459 doesn't make use of partitioning in EL3, however. Platform initialisation 460 code should configure and use partitions in EL3 as required. This option 461 defaults to ``2`` since MPAM is enabled by default for NS world only. 462 The flag is automatically disabled when the target 463 architecture is AArch32. 464 465- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 466 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 467 firmware to detect and limit high activity events to assist in SoC processor 468 power domain dynamic power budgeting and limit the triggering of whole-rail 469 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 470 471- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 472 allows platforms with cores supporting MPMM to describe them via the 473 ``HW_CONFIG`` device tree blob. Default is 0. 474 475- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 476 support within generic code in TF-A. This option is currently only supported 477 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 478 in BL32 (SP_min) for AARCH32. Default is 0. 479 480- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 481 Measurement Framework(PMF). Default is 0. 482 483- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 484 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 485 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 486 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 487 software. 488 489- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 490 instrumentation which injects timestamp collection points into TF-A to 491 allow runtime performance to be measured. Currently, only PSCI is 492 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 493 as well. Default is 0. 494 495- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 496 extensions. This is an optional architectural feature for AArch64. 497 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 498 mechanism. The default is 2 but is automatically disabled when the target 499 architecture is AArch32. 500 501- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 502 (SVE) for the Non-secure world only. SVE is an optional architectural feature 503 for AArch64. Note that when SVE is enabled for the Non-secure world, access 504 to SIMD and floating-point functionality from the Secure world is disabled by 505 default and controlled with ENABLE_SVE_FOR_SWD. 506 This is to avoid corruption of the Non-secure world data in the Z-registers 507 which are aliased by the SIMD and FP registers. The build option is not 508 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 509 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 510 enabled. This flag can take the values 0 to 2, to align with the 511 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 512 used on systems that have SPM_MM enabled. The default is 1. 513 514- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 515 SVE is an optional architectural feature for AArch64. Note that this option 516 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 517 automatically disabled when the target architecture is AArch32. 518 519- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 520 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 521 default value is set to "none". "strong" is the recommended stack protection 522 level if this feature is desired. "none" disables the stack protection. For 523 all values other than "none", the ``plat_get_stack_protector_canary()`` 524 platform hook needs to be implemented. The value is passed as the last 525 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 526 527- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 528 flag depends on ``DECRYPTION_SUPPORT`` build flag. 529 530- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 531 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 532 533- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 534 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 535 on ``DECRYPTION_SUPPORT`` build flag. 536 537- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 538 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 539 build flag. 540 541- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 542 deprecated platform APIs, helper functions or drivers within Trusted 543 Firmware as error. It can take the value 1 (flag the use of deprecated 544 APIs as error) or 0. The default is 0. 545 546- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 547 configure an Arm® Ethos™-N NPU. To use this service the target platform's 548 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 549 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 550 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 551 552- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 553 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 554 ``TRUSTED_BOARD_BOOT`` to be enabled. 555 556- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 557 (```ethosn.bin```). This firmware image will be included in the FIP and 558 loaded at runtime. 559 560- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 561 targeted at EL3. When set ``0`` (default), no exceptions are expected or 562 handled at EL3, and a panic will result. The exception to this rule is when 563 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 564 occuring during normal world execution, are trapped to EL3. Any exception 565 trapped during secure world execution are trapped to the SPMC. This is 566 supported only for AArch64 builds. 567 568- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 569 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 570 Default value is 40 (LOG_LEVEL_INFO). 571 572- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 573 injection from lower ELs, and this build option enables lower ELs to use 574 Error Records accessed via System Registers to inject faults. This is 575 applicable only to AArch64 builds. 576 577 This feature is intended for testing purposes only, and is advisable to keep 578 disabled for production images. 579 580- ``FIP_NAME``: This is an optional build option which specifies the FIP 581 filename for the ``fip`` target. Default is ``fip.bin``. 582 583- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 584 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 585 586- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 587 588 :: 589 590 0: Encryption is done with Secret Symmetric Key (SSK) which is common 591 for a class of devices. 592 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 593 unique per device. 594 595 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 596 597- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 598 tool to create certificates as per the Chain of Trust described in 599 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 600 include the certificates in the FIP and FWU_FIP. Default value is '0'. 601 602 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 603 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 604 the corresponding certificates, and to include those certificates in the 605 FIP and FWU_FIP. 606 607 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 608 images will not include support for Trusted Board Boot. The FIP will still 609 include the corresponding certificates. This FIP can be used to verify the 610 Chain of Trust on the host machine through other mechanisms. 611 612 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 613 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 614 will not include the corresponding certificates, causing a boot failure. 615 616- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 617 inherent support for specific EL3 type interrupts. Setting this build option 618 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 619 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 620 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 621 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 622 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 623 the Secure Payload interrupts needs to be synchronously handed over to Secure 624 EL1 for handling. The default value of this option is ``0``, which means the 625 Group 0 interrupts are assumed to be handled by Secure EL1. 626 627- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 628 Interrupts, resulting from errors in NS world, will be always trapped in 629 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 630 will be trapped in the current exception level (or in EL1 if the current 631 exception level is EL0). 632 633- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 634 software operations are required for CPUs to enter and exit coherency. 635 However, newer systems exist where CPUs' entry to and exit from coherency 636 is managed in hardware. Such systems require software to only initiate these 637 operations, and the rest is managed in hardware, minimizing active software 638 management. In such systems, this boolean option enables TF-A to carry out 639 build and run-time optimizations during boot and power management operations. 640 This option defaults to 0 and if it is enabled, then it implies 641 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 642 643 If this flag is disabled while the platform which TF-A is compiled for 644 includes cores that manage coherency in hardware, then a compilation error is 645 generated. This is based on the fact that a system cannot have, at the same 646 time, cores that manage coherency in hardware and cores that don't. In other 647 words, a platform cannot have, at the same time, cores that require 648 ``HW_ASSISTED_COHERENCY=1`` and cores that require 649 ``HW_ASSISTED_COHERENCY=0``. 650 651 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 652 translation library (xlat tables v2) must be used; version 1 of translation 653 library is not supported. 654 655- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 656 implementation defined system register accesses from lower ELs. Default 657 value is ``0``. 658 659- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 660 bottom, higher addresses at the top. This build flag can be set to '1' to 661 invert this behavior. Lower addresses will be printed at the top and higher 662 addresses at the bottom. 663 664- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 665 used for generating the PKCS keys and subsequent signing of the certificate. 666 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 667 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 668 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 669 compatibility. The default value of this flag is ``rsa`` which is the TBBR 670 compliant PKCS#1 RSA 2.1 scheme. 671 672- ``KEY_SIZE``: This build flag enables the user to select the key size for 673 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 674 depend on the chosen algorithm and the cryptographic module. 675 676 +---------------------------+------------------------------------+ 677 | KEY_ALG | Possible key sizes | 678 +===========================+====================================+ 679 | rsa | 1024 , 2048 (default), 3072, 4096 | 680 +---------------------------+------------------------------------+ 681 | ecdsa | 256 (default), 384 | 682 +---------------------------+------------------------------------+ 683 | ecdsa-brainpool-regular | unavailable | 684 +---------------------------+------------------------------------+ 685 | ecdsa-brainpool-twisted | unavailable | 686 +---------------------------+------------------------------------+ 687 688- ``HASH_ALG``: This build flag enables the user to select the secure hash 689 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 690 The default value of this flag is ``sha256``. 691 692- ``LDFLAGS``: Extra user options appended to the linkers' command line in 693 addition to the one set by the build system. 694 695- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 696 output compiled into the build. This should be one of the following: 697 698 :: 699 700 0 (LOG_LEVEL_NONE) 701 10 (LOG_LEVEL_ERROR) 702 20 (LOG_LEVEL_NOTICE) 703 30 (LOG_LEVEL_WARNING) 704 40 (LOG_LEVEL_INFO) 705 50 (LOG_LEVEL_VERBOSE) 706 707 All log output up to and including the selected log level is compiled into 708 the build. The default value is 40 in debug builds and 20 in release builds. 709 710- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 711 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 712 provide trust that the code taking the measurements and recording them has 713 not been tampered with. 714 715 This option defaults to 0. 716 717- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 718 options to the compiler. An example usage: 719 720 .. code:: make 721 722 MARCH_DIRECTIVE := -march=armv8.5-a 723 724- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 725 options to the compiler currently supporting only of the options. 726 GCC documentation: 727 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 728 729 An example usage: 730 731 .. code:: make 732 733 HARDEN_SLS := 1 734 735 This option defaults to 0. 736 737- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 738 specifies a file that contains the Non-Trusted World private key in PEM 739 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 740 will be used to save the key. 741 742- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 743 optional. It is only needed if the platform makefile specifies that it 744 is required in order to build the ``fwu_fip`` target. 745 746- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 747 contents upon world switch. It can take either 0 (don't save and restore) or 748 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 749 wants the timer registers to be saved and restored. 750 751- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 752 for the BL image. It can be either 0 (include) or 1 (remove). The default 753 value is 0. 754 755- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 756 the underlying hardware is not a full PL011 UART but a minimally compliant 757 generic UART, which is a subset of the PL011. The driver will not access 758 any register that is not part of the SBSA generic UART specification. 759 Default value is 0 (a full PL011 compliant UART is present). 760 761- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 762 must be subdirectory of any depth under ``plat/``, and must contain a 763 platform makefile named ``platform.mk``. For example, to build TF-A for the 764 Arm Juno board, select PLAT=juno. 765 766- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 767 each core as well as the global context. The data includes the memory used 768 by each world and each privileged exception level. This build option is 769 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 770 771- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 772 instead of the normal boot flow. When defined, it must specify the entry 773 point address for the preloaded BL33 image. This option is incompatible with 774 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 775 over ``PRELOADED_BL33_BASE``. 776 777- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 778 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 779 registers when the cluster goes through a power cycle. This is disabled by 780 default and platforms that require this feature have to enable them. 781 782- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 783 vector address can be programmed or is fixed on the platform. It can take 784 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 785 programmable reset address, it is expected that a CPU will start executing 786 code directly at the right address, both on a cold and warm reset. In this 787 case, there is no need to identify the entrypoint on boot and the boot path 788 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 789 does not need to be implemented in this case. 790 791- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 792 possible for the PSCI power-state parameter: original and extended State-ID 793 formats. This flag if set to 1, configures the generic PSCI layer to use the 794 extended format. The default value of this flag is 0, which means by default 795 the original power-state format is used by the PSCI implementation. This flag 796 should be specified by the platform makefile and it governs the return value 797 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 798 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 799 set to 1 as well. 800 801- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 802 OS-initiated mode. This option defaults to 0. 803 804- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 805 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 806 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 807 NOTE: This flag enables use of IESB capability to reduce entry latency into 808 EL3 even when RAS error handling is not performed on the platform. Hence this 809 flag is recommended to be turned on Armv8.2 and later CPUs. 810 811- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 812 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 813 entrypoint) or 1 (CPU reset to BL31 entrypoint). 814 The default value is 0. 815 816- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 817 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 818 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 819 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 820 821- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 822- blocks) covered by a single bit of the bitlock structure during RME GPT 823- operations. The lower the block size, the better opportunity for 824- parallelising GPT operations but at the cost of more bits being needed 825- for the bitlock structure. This numeric parameter can take the values 826- from 0 to 512 and must be a power of 2. The value of 0 is special and 827- and it chooses a single spinlock for all GPT L1 table entries. Default 828- value is 1 which corresponds to block size of 512MB per bit of bitlock 829- structure. 830 831- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 832 supported contiguous blocks in GPT Library. This parameter can take the 833 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 834 descriptors. Default value is 2. 835 836- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 837 file that contains the ROT private key in PEM format or a PKCS11 URI and 838 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 839 accepted and it will be used to save the key. 840 841- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 842 certificate generation tool to save the keys used to establish the Chain of 843 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 844 845- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 846 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 847 target. 848 849- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 850 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 851 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 852 853- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 854 optional. It is only needed if the platform makefile specifies that it 855 is required in order to build the ``fwu_fip`` target. 856 857- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 858 Delegated Exception Interface to BL31 image. This defaults to ``0``. 859 860 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 861 set to ``1``. 862 863- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 864 isolated on separate memory pages. This is a trade-off between security and 865 memory usage. See "Isolating code and read-only data on separate memory 866 pages" section in :ref:`Firmware Design`. This flag is disabled by default 867 and affects all BL images. 868 869- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 870 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 871 allocated in RAM discontiguous from the loaded firmware image. When set, the 872 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 873 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 874 sections are placed in RAM immediately following the loaded firmware image. 875 876- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 877 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 878 discontiguous from loaded firmware images. When set, the platform need to 879 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 880 flag is disabled by default and NOLOAD sections are placed in RAM immediately 881 following the loaded firmware image. 882 883- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 884 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 885 UEFI+ACPI this can provide a certain amount of OS forward compatibility 886 with newer platforms that aren't ECAM compliant. 887 888- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 889 This build option is only valid if ``ARCH=aarch64``. The value should be 890 the path to the directory containing the SPD source, relative to 891 ``services/spd/``; the directory is expected to contain a makefile called 892 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 893 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 894 cannot be enabled when the ``SPM_MM`` option is enabled. 895 896- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 897 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 898 execution in BL1 just before handing over to BL31. At this point, all 899 firmware images have been loaded in memory, and the MMU and caches are 900 turned off. Refer to the "Debugging options" section for more details. 901 902- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 903 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 904 component runs at the EL3 exception level. The default value is ``0`` ( 905 disabled). This configuration supports pre-Armv8.4 platforms (aka not 906 implementing the ``FEAT_SEL2`` extension). 907 908- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 909 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 910 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 911 912- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 913 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 914 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 915 mechanism should be used. 916 917- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 918 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 919 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 920 extension. This is the default when enabling the SPM Dispatcher. When 921 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 922 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 923 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 924 extension). 925 926- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 927 Partition Manager (SPM) implementation. The default value is ``0`` 928 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 929 enabled (``SPD=spmd``). 930 931- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 932 description of secure partitions. The build system will parse this file and 933 package all secure partition blobs into the FIP. This file is not 934 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 935 936- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 937 secure interrupts (caught through the FIQ line). Platforms can enable 938 this directive if they need to handle such interruption. When enabled, 939 the FIQ are handled in monitor mode and non secure world is not allowed 940 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 941 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 942 943- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 944 Platforms can configure this if they need to lower the hardware 945 limit, for example due to asymmetric configuration or limitations of 946 software run at lower ELs. The default is the architectural maximum 947 of 2048 which should be suitable for most configurations, the 948 hardware will limit the effective VL to the maximum physically supported 949 VL. 950 951- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 952 Random Number Generator Interface to BL31 image. This defaults to ``0``. 953 954- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 955 Boot feature. When set to '1', BL1 and BL2 images include support to load 956 and verify the certificates and images in a FIP, and BL1 includes support 957 for the Firmware Update. The default value is '0'. Generation and inclusion 958 of certificates in the FIP and FWU_FIP depends upon the value of the 959 ``GENERATE_COT`` option. 960 961 .. warning:: 962 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 963 already exist in disk, they will be overwritten without further notice. 964 965- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 966 specifies a file that contains the Trusted World private key in PEM 967 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 968 it will be used to save the key. 969 970- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 971 synchronous, (see "Initializing a BL32 Image" section in 972 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 973 synchronous method) or 1 (BL32 is initialized using asynchronous method). 974 Default is 0. 975 976- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 977 routing model which routes non-secure interrupts asynchronously from TSP 978 to EL3 causing immediate preemption of TSP. The EL3 is responsible 979 for saving and restoring the TSP context in this routing model. The 980 default routing model (when the value is 0) is to route non-secure 981 interrupts to TSP allowing it to save its context and hand over 982 synchronously to EL3 via an SMC. 983 984 .. note:: 985 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 986 must also be set to ``1``. 987 988- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 989 internal-trusted-storage) as SP in tb_fw_config device tree. 990 991- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 992 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 993 this delay. It can take values in the range (0-15). Default value is ``0`` 994 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 995 Platforms need to explicitly update this value based on their requirements. 996 997- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 998 linker. When the ``LINKER`` build variable points to the armlink linker, 999 this flag is enabled automatically. To enable support for armlink, platforms 1000 will have to provide a scatter file for the BL image. Currently, Tegra 1001 platforms use the armlink support to compile BL3-1 images. 1002 1003- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1004 memory region in the BL memory map or not (see "Use of Coherent memory in 1005 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1006 (Coherent memory region is included) or 0 (Coherent memory region is 1007 excluded). Default is 1. 1008 1009- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1010 firmware configuration framework. This will move the io_policies into a 1011 configuration device tree, instead of static structure in the code base. 1012 1013- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1014 at runtime using fconf. If this flag is enabled, COT descriptors are 1015 statically captured in tb_fw_config file in the form of device tree nodes 1016 and properties. Currently, COT descriptors used by BL2 are moved to the 1017 device tree and COT descriptors used by BL1 are retained in the code 1018 base statically. 1019 1020- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1021 runtime using firmware configuration framework. The platform specific SDEI 1022 shared and private events configuration is retrieved from device tree rather 1023 than static C structures at compile time. This is only supported if 1024 SDEI_SUPPORT build flag is enabled. 1025 1026- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1027 and Group1 secure interrupts using the firmware configuration framework. The 1028 platform specific secure interrupt property descriptor is retrieved from 1029 device tree in runtime rather than depending on static C structure at compile 1030 time. 1031 1032- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1033 This feature creates a library of functions to be placed in ROM and thus 1034 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1035 is 0. 1036 1037- ``V``: Verbose build. If assigned anything other than 0, the build commands 1038 are printed. Default is 0. 1039 1040- ``VERSION_STRING``: String used in the log output for each TF-A image. 1041 Defaults to a string formed by concatenating the version number, build type 1042 and build string. 1043 1044- ``W``: Warning level. Some compiler warning options of interest have been 1045 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1046 each level enabling more warning options. Default is 0. 1047 1048 This option is closely related to the ``E`` option, which enables 1049 ``-Werror``. 1050 1051 - ``W=0`` (default) 1052 1053 Enables a wide assortment of warnings, most notably ``-Wall`` and 1054 ``-Wextra``, as well as various bad practices and things that are likely to 1055 result in errors. Includes some compiler specific flags. No warnings are 1056 expected at this level for any build. 1057 1058 - ``W=1`` 1059 1060 Enables warnings we want the generic build to include but are too time 1061 consuming to fix at the moment. It re-enables warnings taken out for 1062 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1063 to eventually be merged into ``W=0``. Some warnings are expected on some 1064 builds, but new contributions should not introduce new ones. 1065 1066 - ``W=2`` (recommended) 1067 1068 Enables warnings we want the generic build to include but cannot be enabled 1069 due to external libraries. This level is expected to eventually be merged 1070 into ``W=0``. Lots of warnings are expected, primarily from external 1071 libraries like zlib and compiler-rt, but new controbutions should not 1072 introduce new ones. 1073 1074 - ``W=3`` 1075 1076 Enables warnings that are informative but not necessary and generally too 1077 verbose and frequently ignored. A very large number of warnings are 1078 expected. 1079 1080 The exact set of warning flags depends on the compiler and TF-A warning 1081 level, however they are all succinctly set in the top-level Makefile. Please 1082 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1083 individual flags. 1084 1085- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1086 the CPU after warm boot. This is applicable for platforms which do not 1087 require interconnect programming to enable cache coherency (eg: single 1088 cluster platforms). If this option is enabled, then warm boot path 1089 enables D-caches immediately after enabling MMU. This option defaults to 0. 1090 1091- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1092 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1093 default value of this flag is ``no``. Note this option must be enabled only 1094 for ARM architecture greater than Armv8.5-A. 1095 1096- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1097 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1098 The default value of this flag is ``0``. 1099 1100 ``AT`` speculative errata workaround disables stage1 page table walk for 1101 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1102 produces either the correct result or failure without TLB allocation. 1103 1104 This boolean option enables errata for all below CPUs. 1105 1106 +---------+--------------+-------------------------+ 1107 | Errata | CPU | Workaround Define | 1108 +=========+==============+=========================+ 1109 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1110 +---------+--------------+-------------------------+ 1111 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1112 +---------+--------------+-------------------------+ 1113 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1114 +---------+--------------+-------------------------+ 1115 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1116 +---------+--------------+-------------------------+ 1117 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1118 +---------+--------------+-------------------------+ 1119 1120 .. note:: 1121 This option is enabled by build only if platform sets any of above defines 1122 mentioned in ’Workaround Define' column in the table. 1123 If this option is enabled for the EL3 software then EL2 software also must 1124 implement this workaround due to the behaviour of the errata mentioned 1125 in new SDEN document which will get published soon. 1126 1127- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1128 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1129 This flag is disabled by default. 1130 1131- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1132 host machine where a custom installation of OpenSSL is located, which is used 1133 to build the certificate generation, firmware encryption and FIP tools. If 1134 this option is not set, the default OS installation will be used. 1135 1136- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1137 functions that wait for an arbitrary time length (udelay and mdelay). The 1138 default value is 0. 1139 1140- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1141 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1142 optional architectural feature for AArch64. This flag can take the values 1143 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1144 and it is automatically disabled when the target architecture is AArch32. 1145 1146- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1147 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1148 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1149 feature for AArch64. This flag can take the values 0 to 2, to align with the 1150 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1151 disabled when the target architecture is AArch32. 1152 1153- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1154 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1155 but unused). This feature is available if trace unit such as ETMv4.x, and 1156 ETE(extending ETM feature) is implemented. This flag can take the values 1157 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1158 1159- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1160 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1161 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1162 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1163 1164- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1165 ``plat_can_cmo`` which will return zero if cache management operations should 1166 be skipped and non-zero otherwise. By default, this option is disabled which 1167 means platform hook won't be checked and CMOs will always be performed when 1168 related functions are called. 1169 1170- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1171 firmware interface for the BL31 image. By default its disabled (``0``). 1172 1173- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1174 errata mitigation for platforms with a non-arm interconnect using the errata 1175 ABI. By default its disabled (``0``). 1176 1177- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1178 driver(s). By default it is disabled (``0``) because it constitutes an attack 1179 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1180 This option should only be enabled on a need basis if there is a use case for 1181 reading characters from the console. 1182 1183GICv3 driver options 1184-------------------- 1185 1186GICv3 driver files are included using directive: 1187 1188``include drivers/arm/gic/v3/gicv3.mk`` 1189 1190The driver can be configured with the following options set in the platform 1191makefile: 1192 1193- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1194 Enabling this option will add runtime detection support for the 1195 GIC-600, so is safe to select even for a GIC500 implementation. 1196 This option defaults to 0. 1197 1198- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1199 for GIC-600 AE. Enabling this option will introduce support to initialize 1200 the FMU. Platforms should call the init function during boot to enable the 1201 FMU and its safety mechanisms. This option defaults to 0. 1202 1203- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1204 functionality. This option defaults to 0 1205 1206- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1207 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1208 functions. This is required for FVP platform which need to simulate GIC save 1209 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1210 1211- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1212 This option defaults to 0. 1213 1214- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1215 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1216 1217Debugging options 1218----------------- 1219 1220To compile a debug version and make the build more verbose use 1221 1222.. code:: shell 1223 1224 make PLAT=<platform> DEBUG=1 V=1 all 1225 1226AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1227(for example Arm-DS) might not support this and may need an older version of 1228DWARF symbols to be emitted by GCC. This can be achieved by using the 1229``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1230the version to 4 is recommended for Arm-DS. 1231 1232When debugging logic problems it might also be useful to disable all compiler 1233optimizations by using ``-O0``. 1234 1235.. warning:: 1236 Using ``-O0`` could cause output images to be larger and base addresses 1237 might need to be recalculated (see the **Memory layout on Arm development 1238 platforms** section in the :ref:`Firmware Design`). 1239 1240Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1241``LDFLAGS``: 1242 1243.. code:: shell 1244 1245 CFLAGS='-O0 -gdwarf-2' \ 1246 make PLAT=<platform> DEBUG=1 V=1 all 1247 1248Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1249ignored as the linker is called directly. 1250 1251It is also possible to introduce an infinite loop to help in debugging the 1252post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1253``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1254section. In this case, the developer may take control of the target using a 1255debugger when indicated by the console output. When using Arm-DS, the following 1256commands can be used: 1257 1258:: 1259 1260 # Stop target execution 1261 interrupt 1262 1263 # 1264 # Prepare your debugging environment, e.g. set breakpoints 1265 # 1266 1267 # Jump over the debug loop 1268 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1269 1270 # Resume execution 1271 continue 1272 1273.. _build_options_experimental: 1274 1275Experimental build options 1276--------------------------- 1277 1278Common build options 1279~~~~~~~~~~~~~~~~~~~~ 1280 1281- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1282 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1283 set to ``1`` then measurements and additional metadata collected during the 1284 measured boot process are sent to the DICE Protection Environment for storage 1285 and processing. A certificate chain, which represents the boot state of the 1286 device, can be queried from the DPE. 1287 1288- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1289 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1290 the measurements and recording them as per `PSA DRTM specification`_. For 1291 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1292 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1293 should have mechanism to authenticate BL31. This option defaults to 0. 1294 1295- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1296 Management Extension. This flag can take the values 0 to 2, to align with 1297 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1298 1299- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1300 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1301 registers so are enabled together. Using this option without 1302 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1303 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1304 superset of SVE. SME is an optional architectural feature for AArch64. 1305 At this time, this build option cannot be used on systems that have 1306 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1307 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1308 mechanism. Default is 0. 1309 1310- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1311 version 2 (SME2) for the non-secure world only. SME2 is an optional 1312 architectural feature for AArch64. 1313 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1314 accesses will still be trapped. This flag can take the values 0 to 2, to 1315 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1316 1317- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1318 Extension for secure world. Used along with SVE and FPU/SIMD. 1319 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1320 Default is 0. 1321 1322- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1323 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1324 for logical partitions in EL3, managed by the SPMD as defined in the 1325 FF-A v1.2 specification. This flag is disabled by default. This flag 1326 must not be used if ``SPMC_AT_EL3`` is enabled. 1327 1328- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1329 verification mechanism. This is a debug feature that compares the 1330 architectural features enabled through the feature specific build flags 1331 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1332 and reports any discrepancies. 1333 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1334 1335 It is expected that this feature is only used for flexible platforms like 1336 software emulators, or for hardware platforms at bringup time, to verify 1337 that the configured feature set matches the CPU. 1338 The ``FEATURE_DETECTION`` macro is disabled by default. 1339 1340- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1341 The platform will use PSA compliant Crypto APIs during authentication and 1342 image measurement process by enabling this option. It uses APIs defined as 1343 per the `PSA Crypto API specification`_. This feature is only supported if 1344 using MbedTLS 3.x version. It is disabled (``0``) by default. 1345 1346- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1347 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1348 This defaults to ``0``. Current implementation follows the Firmware Handoff 1349 specification v0.9. 1350 1351- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1352 interface through BL31 as a SiP SMC function. 1353 Default is disabled (0). 1354 1355Firmware update options 1356~~~~~~~~~~~~~~~~~~~~~~~ 1357 1358- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1359 `PSA FW update specification`_. The default value is 0. 1360 PSA firmware update implementation has few limitations, such as: 1361 1362 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1363 be updated, then it should be done through another platform-defined 1364 mechanism. 1365 1366 - It assumes the platform's hardware supports CRC32 instructions. 1367 1368- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1369 in defining the firmware update metadata structure. This flag is by default 1370 set to '2'. 1371 1372- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1373 firmware bank. Each firmware bank must have the same number of images as per 1374 the `PSA FW update specification`_. 1375 This flag is used in defining the firmware update metadata structure. This 1376 flag is by default set to '1'. 1377 1378- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1379 metadata contains image description. The default value is 1. 1380 1381 The version 2 of the FWU metadata allows for an opaque metadata 1382 structure where a platform can choose to not include the firmware 1383 store description in the metadata structure. This option indicates 1384 if the firmware store description, which provides information on 1385 the updatable images is part of the structure. 1386 1387-------------- 1388 1389*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1390 1391.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1392.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1393.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1394.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1395.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1396.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1397.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1398