1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/amd/versal2 8 9# A78 Erratum for SoC 10ERRATA_A78_AE_1941500 := 1 11ERRATA_A78_AE_1951502 := 1 12ERRATA_A78_AE_2376748 := 1 13ERRATA_A78_AE_2395408 := 1 14ERRATA_ABI_SUPPORT := 1 15 16# Platform Supports Armv8.2 extensions 17ARM_ARCH_MAJOR := 8 18ARM_ARCH_MINOR := 2 19 20override PROGRAMMABLE_RESET_ADDRESS := 1 21PSCI_EXTENDED_STATE_ID := 1 22SEPARATE_CODE_AND_RODATA := 1 23override RESET_TO_BL31 := 1 24PL011_GENERIC_UART := 1 25IPI_CRC_CHECK := 0 26GIC_ENABLE_V4_EXTN := 0 27GICV3_SUPPORT_GIC600 := 1 28 29override CTX_INCLUDE_AARCH32_REGS := 0 30 31ifdef MEM_BASE 32 $(eval $(call add_define,MEM_BASE)) 33 34 ifndef MEM_SIZE 35 $(error "MEM_BASE defined without MEM_SIZE") 36 endif 37 $(eval $(call add_define,MEM_SIZE)) 38 39 ifdef MEM_PROGBITS_SIZE 40 $(eval $(call add_define,MEM_PROGBITS_SIZE)) 41 endif 42endif 43 44ifdef BL32_MEM_BASE 45 $(eval $(call add_define,BL32_MEM_BASE)) 46 47 ifndef BL32_MEM_SIZE 48 $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 49 endif 50 $(eval $(call add_define,BL32_MEM_SIZE)) 51endif 52 53ifdef IPI_CRC_CHECK 54 $(eval $(call add_define,IPI_CRC_CHECK)) 55endif 56 57USE_COHERENT_MEM := 0 58HW_ASSISTED_COHERENCY := 1 59 60CONSOLE ?= pl011 61ifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc)) 62else 63 $(error Please define CONSOLE) 64endif 65 66$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE})) 67 68ifdef XILINX_OF_BOARD_DTB_ADDR 69$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 70endif 71 72PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 73 -Iplat/xilinx/common/include/ \ 74 -Iplat/xilinx/common/ipi_mailbox_service/ \ 75 -I${PLAT_PATH}/include/ \ 76 -Iplat/xilinx/versal/pm_service/ 77 78# Include GICv3 driver files 79include drivers/arm/gic/v3/gicv3.mk 80include lib/xlat_tables_v2/xlat_tables.mk 81include lib/libfdt/libfdt.mk 82 83PLAT_BL_COMMON_SOURCES := \ 84 drivers/arm/dcc/dcc_console.c \ 85 drivers/delay_timer/delay_timer.c \ 86 drivers/delay_timer/generic_delay_timer.c \ 87 ${GICV3_SOURCES} \ 88 drivers/arm/pl011/aarch64/pl011_console.S \ 89 plat/common/aarch64/crash_console_helpers.S \ 90 plat/arm/common/arm_common.c \ 91 plat/common/plat_gicv3.c \ 92 ${PLAT_PATH}/aarch64/helpers.S \ 93 ${PLAT_PATH}/aarch64/common.c \ 94 ${PLAT_PATH}/plat_topology.c \ 95 ${XLAT_TABLES_LIB_SRCS} 96 97BL31_SOURCES += drivers/arm/cci/cci.c \ 98 lib/cpus/aarch64/cortex_a78_ae.S \ 99 lib/cpus/aarch64/cortex_a78.S \ 100 plat/common/plat_psci_common.c \ 101 drivers/scmi-msg/base.c \ 102 drivers/scmi-msg/entry.c \ 103 drivers/scmi-msg/smt.c \ 104 drivers/scmi-msg/clock.c \ 105 drivers/scmi-msg/power_domain.c \ 106 drivers/scmi-msg/reset_domain.c \ 107 ${PLAT_PATH}/scmi.c 108 109BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 110 111BL31_SOURCES += plat/xilinx/common/plat_fdt.c \ 112 plat/xilinx/common/plat_startup.c \ 113 plat/xilinx/common/ipi.c \ 114 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 115 ${PLAT_PATH}/soc_ipi.c \ 116 plat/xilinx/common/versal.c \ 117 ${PLAT_PATH}/bl31_setup.c \ 118 common/fdt_fixup.c \ 119 common/fdt_wrappers.c \ 120 ${LIBFDT_SRCS} \ 121 ${PLAT_PATH}/sip_svc_setup.c \ 122 ${PLAT_PATH}/gicv3.c 123 124ifeq (${ERRATA_ABI_SUPPORT}, 1) 125# enable the cpu macros for errata abi interface 126CORTEX_A78_AE_H_INC := 1 127$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 128endif 129