1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sys_reg_trace.h> 37 #include <lib/extensions/tcr2.h> 38 #include <lib/extensions/trbe.h> 39 #include <lib/extensions/trf.h> 40 #include <lib/utils.h> 41 42 #if ENABLE_FEAT_TWED 43 /* Make sure delay value fits within the range(0-15) */ 44 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 45 #endif /* ENABLE_FEAT_TWED */ 46 47 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 48 static bool has_secure_perworld_init; 49 50 static void manage_extensions_common(cpu_context_t *ctx); 51 static void manage_extensions_nonsecure(cpu_context_t *ctx); 52 static void manage_extensions_secure(cpu_context_t *ctx); 53 static void manage_extensions_secure_per_world(void); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 152 /** 153 * manage_extensions_secure_per_world api has to be executed once, 154 * as the registers getting initialised, maintain constant value across 155 * all the cpus for the secure world. 156 * Henceforth, this check ensures that the registers are initialised once 157 * and avoids re-initialization from multiple cores. 158 */ 159 if (!has_secure_perworld_init) { 160 manage_extensions_secure_per_world(); 161 } 162 } 163 164 #if ENABLE_RME 165 /****************************************************************************** 166 * This function performs initializations that are specific to REALM state 167 * and updates the cpu context specified by 'ctx'. 168 *****************************************************************************/ 169 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 170 { 171 u_register_t scr_el3; 172 el3_state_t *state; 173 174 state = get_el3state_ctx(ctx); 175 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 176 177 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 178 179 /* CSV2 version 2 and above */ 180 if (is_feat_csv2_2_supported()) { 181 /* Enable access to the SCXTNUM_ELx registers. */ 182 scr_el3 |= SCR_EnSCXT_BIT; 183 } 184 185 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 186 } 187 #endif /* ENABLE_RME */ 188 189 /****************************************************************************** 190 * This function performs initializations that are specific to NON-SECURE state 191 * and updates the cpu context specified by 'ctx'. 192 *****************************************************************************/ 193 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 194 { 195 u_register_t scr_el3; 196 el3_state_t *state; 197 198 state = get_el3state_ctx(ctx); 199 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 200 201 /* SCR_NS: Set the NS bit */ 202 scr_el3 |= SCR_NS_BIT; 203 204 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 205 if (is_feat_mte2_supported()) { 206 scr_el3 |= SCR_ATA_BIT; 207 } 208 209 #if !CTX_INCLUDE_PAUTH_REGS 210 /* 211 * Pointer Authentication feature, if present, is always enabled by default 212 * for Non secure lower exception levels. We do not have an explicit 213 * flag to set it. 214 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 215 * exception levels of secure and realm worlds. 216 * 217 * To prevent the leakage between the worlds during world switch, 218 * we enable it only for the non-secure world. 219 * 220 * If the Secure/realm world wants to use pointer authentication, 221 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 222 * it will be enabled globally for all the contexts. 223 * 224 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 225 * other than EL3 226 * 227 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 228 * than EL3 229 */ 230 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 231 232 #endif /* CTX_INCLUDE_PAUTH_REGS */ 233 234 #if HANDLE_EA_EL3_FIRST_NS 235 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 236 scr_el3 |= SCR_EA_BIT; 237 #endif 238 239 #if RAS_TRAP_NS_ERR_REC_ACCESS 240 /* 241 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 242 * and RAS ERX registers from EL1 and EL2(from any security state) 243 * are trapped to EL3. 244 * Set here to trap only for NS EL1/EL2 245 * 246 */ 247 scr_el3 |= SCR_TERR_BIT; 248 #endif 249 250 /* CSV2 version 2 and above */ 251 if (is_feat_csv2_2_supported()) { 252 /* Enable access to the SCXTNUM_ELx registers. */ 253 scr_el3 |= SCR_EnSCXT_BIT; 254 } 255 256 #ifdef IMAGE_BL31 257 /* 258 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 259 * indicated by the interrupt routing model for BL31. 260 */ 261 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 262 #endif 263 264 if (is_feat_the_supported()) { 265 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 266 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 267 */ 268 scr_el3 |= SCR_RCWMASKEn_BIT; 269 } 270 271 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 272 273 /* Initialize EL2 context registers */ 274 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 275 276 /* 277 * Initialize SCTLR_EL2 context register with reset value. 278 */ 279 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 280 281 if (is_feat_hcx_supported()) { 282 /* 283 * Initialize register HCRX_EL2 with its init value. 284 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 285 * chance that this can lead to unexpected behavior in lower 286 * ELs that have not been updated since the introduction of 287 * this feature if not properly initialized, especially when 288 * it comes to those bits that enable/disable traps. 289 */ 290 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 291 HCRX_EL2_INIT_VAL); 292 } 293 294 if (is_feat_fgt_supported()) { 295 /* 296 * Initialize HFG*_EL2 registers with a default value so legacy 297 * systems unaware of FEAT_FGT do not get trapped due to their lack 298 * of initialization for this feature. 299 */ 300 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 301 HFGITR_EL2_INIT_VAL); 302 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 303 HFGRTR_EL2_INIT_VAL); 304 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 305 HFGWTR_EL2_INIT_VAL); 306 } 307 #else 308 /* Initialize EL1 context registers */ 309 setup_el1_context(ctx, ep); 310 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 311 312 manage_extensions_nonsecure(ctx); 313 } 314 315 /******************************************************************************* 316 * The following function performs initialization of the cpu_context 'ctx' 317 * for first use that is common to all security states, and sets the 318 * initial entrypoint state as specified by the entry_point_info structure. 319 * 320 * The EE and ST attributes are used to configure the endianness and secure 321 * timer availability for the new execution context. 322 ******************************************************************************/ 323 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 324 { 325 u_register_t scr_el3; 326 u_register_t mdcr_el3; 327 el3_state_t *state; 328 gp_regs_t *gp_regs; 329 330 state = get_el3state_ctx(ctx); 331 332 /* Clear any residual register values from the context */ 333 zeromem(ctx, sizeof(*ctx)); 334 335 /* 336 * The lower-EL context is zeroed so that no stale values leak to a world. 337 * It is assumed that an all-zero lower-EL context is good enough for it 338 * to boot correctly. However, there are very few registers where this 339 * is not true and some values need to be recreated. 340 */ 341 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 342 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 343 344 /* 345 * These bits are set in the gicv3 driver. Losing them (especially the 346 * SRE bit) is problematic for all worlds. Henceforth recreate them. 347 */ 348 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 349 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 350 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 351 352 /* 353 * The actlr_el2 register can be initialized in platform's reset handler 354 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 355 */ 356 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 357 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 358 359 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 360 scr_el3 = SCR_RESET_VAL; 361 362 /* 363 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 364 * EL2, EL1 and EL0 are not trapped to EL3. 365 * 366 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 367 * EL2, EL1 and EL0 are not trapped to EL3. 368 * 369 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 370 * both Security states and both Execution states. 371 * 372 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 373 * Non-secure memory. 374 */ 375 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 376 377 scr_el3 |= SCR_SIF_BIT; 378 379 /* 380 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 381 * Exception level as specified by SPSR. 382 */ 383 if (GET_RW(ep->spsr) == MODE_RW_64) { 384 scr_el3 |= SCR_RW_BIT; 385 } 386 387 /* 388 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 389 * Secure timer registers to EL3, from AArch64 state only, if specified 390 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 391 * bit always behaves as 1 (i.e. secure physical timer register access 392 * is not trapped) 393 */ 394 if (EP_GET_ST(ep->h.attr) != 0U) { 395 scr_el3 |= SCR_ST_BIT; 396 } 397 398 /* 399 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 400 * SCR_EL3.HXEn. 401 */ 402 if (is_feat_hcx_supported()) { 403 scr_el3 |= SCR_HXEn_BIT; 404 } 405 406 /* 407 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 408 * registers are trapped to EL3. 409 */ 410 #if ENABLE_FEAT_RNG_TRAP 411 scr_el3 |= SCR_TRNDR_BIT; 412 #endif 413 414 #if FAULT_INJECTION_SUPPORT 415 /* Enable fault injection from lower ELs */ 416 scr_el3 |= SCR_FIEN_BIT; 417 #endif 418 419 #if CTX_INCLUDE_PAUTH_REGS 420 /* 421 * Enable Pointer Authentication globally for all the worlds. 422 * 423 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 424 * other than EL3 425 * 426 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 427 * than EL3 428 */ 429 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 430 #endif /* CTX_INCLUDE_PAUTH_REGS */ 431 432 /* 433 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 434 */ 435 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 436 scr_el3 |= SCR_TCR2EN_BIT; 437 } 438 439 /* 440 * SCR_EL3.PIEN: Enable permission indirection and overlay 441 * registers for AArch64 if present. 442 */ 443 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 444 scr_el3 |= SCR_PIEN_BIT; 445 } 446 447 /* 448 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 449 */ 450 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 451 scr_el3 |= SCR_GCSEn_BIT; 452 } 453 454 /* 455 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 456 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 457 * next mode is Hyp. 458 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 459 * same conditions as HVC instructions and when the processor supports 460 * ARMv8.6-FGT. 461 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 462 * CNTPOFF_EL2 register under the same conditions as HVC instructions 463 * and when the processor supports ECV. 464 */ 465 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 466 || ((GET_RW(ep->spsr) != MODE_RW_64) 467 && (GET_M32(ep->spsr) == MODE32_hyp))) { 468 scr_el3 |= SCR_HCE_BIT; 469 470 if (is_feat_fgt_supported()) { 471 scr_el3 |= SCR_FGTEN_BIT; 472 } 473 474 if (is_feat_ecv_supported()) { 475 scr_el3 |= SCR_ECVEN_BIT; 476 } 477 } 478 479 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 480 if (is_feat_twed_supported()) { 481 /* Set delay in SCR_EL3 */ 482 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 483 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 484 << SCR_TWEDEL_SHIFT); 485 486 /* Enable WFE delay */ 487 scr_el3 |= SCR_TWEDEn_BIT; 488 } 489 490 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 491 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 492 if (is_feat_sel2_supported()) { 493 scr_el3 |= SCR_EEL2_BIT; 494 } 495 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 496 497 /* 498 * Populate EL3 state so that we've the right context 499 * before doing ERET 500 */ 501 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 502 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 503 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 504 505 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 506 mdcr_el3 = MDCR_EL3_RESET_VAL; 507 508 /* --------------------------------------------------------------------- 509 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 510 * Some fields are architecturally UNKNOWN on reset. 511 * 512 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 513 * Debug exceptions, other than Breakpoint Instruction exceptions, are 514 * disabled from all ELs in Secure state. 515 * 516 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 517 * privileged debug from S-EL1. 518 * 519 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 520 * access to the powerdown debug registers do not trap to EL3. 521 * 522 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 523 * debug registers, other than those registers that are controlled by 524 * MDCR_EL3.TDOSA. 525 */ 526 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 527 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 528 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 529 530 /* 531 * Configure MDCR_EL3 register as applicable for each world 532 * (NS/Secure/Realm) context. 533 */ 534 manage_extensions_common(ctx); 535 536 /* 537 * Store the X0-X7 value from the entrypoint into the context 538 * Use memcpy as we are in control of the layout of the structures 539 */ 540 gp_regs = get_gpregs_ctx(ctx); 541 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 542 } 543 544 /******************************************************************************* 545 * Context management library initialization routine. This library is used by 546 * runtime services to share pointers to 'cpu_context' structures for secure 547 * non-secure and realm states. Management of the structures and their associated 548 * memory is not done by the context management library e.g. the PSCI service 549 * manages the cpu context used for entry from and exit to the non-secure state. 550 * The Secure payload dispatcher service manages the context(s) corresponding to 551 * the secure state. It also uses this library to get access to the non-secure 552 * state cpu context pointers. 553 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 554 * which will be used for programming an entry into a lower EL. The same context 555 * will be used to save state upon exception entry from that EL. 556 ******************************************************************************/ 557 void __init cm_init(void) 558 { 559 /* 560 * The context management library has only global data to initialize, but 561 * that will be done when the BSS is zeroed out. 562 */ 563 } 564 565 /******************************************************************************* 566 * This is the high-level function used to initialize the cpu_context 'ctx' for 567 * first use. It performs initializations that are common to all security states 568 * and initializations specific to the security state specified in 'ep' 569 ******************************************************************************/ 570 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 571 { 572 unsigned int security_state; 573 574 assert(ctx != NULL); 575 576 /* 577 * Perform initializations that are common 578 * to all security states 579 */ 580 setup_context_common(ctx, ep); 581 582 security_state = GET_SECURITY_STATE(ep->h.attr); 583 584 /* Perform security state specific initializations */ 585 switch (security_state) { 586 case SECURE: 587 setup_secure_context(ctx, ep); 588 break; 589 #if ENABLE_RME 590 case REALM: 591 setup_realm_context(ctx, ep); 592 break; 593 #endif 594 case NON_SECURE: 595 setup_ns_context(ctx, ep); 596 break; 597 default: 598 ERROR("Invalid security state\n"); 599 panic(); 600 break; 601 } 602 } 603 604 /******************************************************************************* 605 * Enable architecture extensions for EL3 execution. This function only updates 606 * registers in-place which are expected to either never change or be 607 * overwritten by el3_exit. 608 ******************************************************************************/ 609 #if IMAGE_BL31 610 void cm_manage_extensions_el3(void) 611 { 612 if (is_feat_amu_supported()) { 613 amu_init_el3(); 614 } 615 616 if (is_feat_sme_supported()) { 617 sme_init_el3(); 618 } 619 620 pmuv3_init_el3(); 621 } 622 #endif /* IMAGE_BL31 */ 623 624 /****************************************************************************** 625 * Function to initialise the registers with the RESET values in the context 626 * memory, which are maintained per world. 627 ******************************************************************************/ 628 #if IMAGE_BL31 629 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 630 { 631 /* 632 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 633 * 634 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 635 * by Advanced SIMD, floating-point or SVE instructions (if 636 * implemented) do not trap to EL3. 637 * 638 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 639 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 640 */ 641 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 642 643 per_world_ctx->ctx_cptr_el3 = cptr_el3; 644 645 /* 646 * Initialize MPAM3_EL3 to its default reset value 647 * 648 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 649 * all lower ELn MPAM3_EL3 register access to, trap to EL3 650 */ 651 652 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 653 } 654 #endif /* IMAGE_BL31 */ 655 656 /******************************************************************************* 657 * Initialise per_world_context for Non-Secure world. 658 * This function enables the architecture extensions, which have same value 659 * across the cores for the non-secure world. 660 ******************************************************************************/ 661 #if IMAGE_BL31 662 void manage_extensions_nonsecure_per_world(void) 663 { 664 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 665 666 if (is_feat_sme_supported()) { 667 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 668 } 669 670 if (is_feat_sve_supported()) { 671 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 672 } 673 674 if (is_feat_amu_supported()) { 675 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 676 } 677 678 if (is_feat_sys_reg_trace_supported()) { 679 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 680 } 681 682 if (is_feat_mpam_supported()) { 683 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 684 } 685 } 686 #endif /* IMAGE_BL31 */ 687 688 /******************************************************************************* 689 * Initialise per_world_context for Secure world. 690 * This function enables the architecture extensions, which have same value 691 * across the cores for the secure world. 692 ******************************************************************************/ 693 static void manage_extensions_secure_per_world(void) 694 { 695 #if IMAGE_BL31 696 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 697 698 if (is_feat_sme_supported()) { 699 700 if (ENABLE_SME_FOR_SWD) { 701 /* 702 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 703 * SME, SVE, and FPU/SIMD context properly managed. 704 */ 705 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 706 } else { 707 /* 708 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 709 * world can safely use the associated registers. 710 */ 711 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 712 } 713 } 714 if (is_feat_sve_supported()) { 715 if (ENABLE_SVE_FOR_SWD) { 716 /* 717 * Enable SVE and FPU in secure context, SPM must ensure 718 * that the SVE and FPU register contexts are properly managed. 719 */ 720 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 721 } else { 722 /* 723 * Disable SVE and FPU in secure context so non-secure world 724 * can safely use them. 725 */ 726 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 727 } 728 } 729 730 /* NS can access this but Secure shouldn't */ 731 if (is_feat_sys_reg_trace_supported()) { 732 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 733 } 734 735 has_secure_perworld_init = true; 736 #endif /* IMAGE_BL31 */ 737 } 738 739 /******************************************************************************* 740 * Enable architecture extensions on first entry to Non-secure world only 741 * and disable for secure world. 742 * 743 * NOTE: Arch features which have been provided with the capability of getting 744 * enabled only for non-secure world and being disabled for secure world are 745 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 746 ******************************************************************************/ 747 static void manage_extensions_common(cpu_context_t *ctx) 748 { 749 #if IMAGE_BL31 750 if (is_feat_spe_supported()) { 751 /* 752 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 753 */ 754 spe_enable(ctx); 755 } 756 757 if (is_feat_trbe_supported()) { 758 /* 759 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 760 * Realm state. 761 */ 762 trbe_enable(ctx); 763 } 764 765 if (is_feat_trf_supported()) { 766 /* 767 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 768 */ 769 trf_enable(ctx); 770 } 771 772 if (is_feat_brbe_supported()) { 773 /* 774 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 775 */ 776 brbe_enable(ctx); 777 } 778 #endif /* IMAGE_BL31 */ 779 } 780 781 /******************************************************************************* 782 * Enable architecture extensions on first entry to Non-secure world. 783 ******************************************************************************/ 784 static void manage_extensions_nonsecure(cpu_context_t *ctx) 785 { 786 #if IMAGE_BL31 787 if (is_feat_amu_supported()) { 788 amu_enable(ctx); 789 } 790 791 if (is_feat_sme_supported()) { 792 sme_enable(ctx); 793 } 794 795 if (is_feat_fgt2_supported()) { 796 fgt2_enable(ctx); 797 } 798 799 if (is_feat_debugv8p9_supported()) { 800 debugv8p9_extended_bp_wp_enable(ctx); 801 } 802 803 pmuv3_enable(ctx); 804 #endif /* IMAGE_BL31 */ 805 } 806 807 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 808 static __unused void enable_pauth_el2(void) 809 { 810 u_register_t hcr_el2 = read_hcr_el2(); 811 /* 812 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 813 * accessing key registers or using pointer authentication instructions 814 * from lower ELs. 815 */ 816 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 817 818 write_hcr_el2(hcr_el2); 819 } 820 821 #if INIT_UNUSED_NS_EL2 822 /******************************************************************************* 823 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 824 * world when EL2 is empty and unused. 825 ******************************************************************************/ 826 static void manage_extensions_nonsecure_el2_unused(void) 827 { 828 #if IMAGE_BL31 829 if (is_feat_spe_supported()) { 830 spe_init_el2_unused(); 831 } 832 833 if (is_feat_amu_supported()) { 834 amu_init_el2_unused(); 835 } 836 837 if (is_feat_mpam_supported()) { 838 mpam_init_el2_unused(); 839 } 840 841 if (is_feat_trbe_supported()) { 842 trbe_init_el2_unused(); 843 } 844 845 if (is_feat_sys_reg_trace_supported()) { 846 sys_reg_trace_init_el2_unused(); 847 } 848 849 if (is_feat_trf_supported()) { 850 trf_init_el2_unused(); 851 } 852 853 pmuv3_init_el2_unused(); 854 855 if (is_feat_sve_supported()) { 856 sve_init_el2_unused(); 857 } 858 859 if (is_feat_sme_supported()) { 860 sme_init_el2_unused(); 861 } 862 863 #if ENABLE_PAUTH 864 enable_pauth_el2(); 865 #endif /* ENABLE_PAUTH */ 866 #endif /* IMAGE_BL31 */ 867 } 868 #endif /* INIT_UNUSED_NS_EL2 */ 869 870 /******************************************************************************* 871 * Enable architecture extensions on first entry to Secure world. 872 ******************************************************************************/ 873 static void manage_extensions_secure(cpu_context_t *ctx) 874 { 875 #if IMAGE_BL31 876 if (is_feat_sme_supported()) { 877 if (ENABLE_SME_FOR_SWD) { 878 /* 879 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 880 * must ensure SME, SVE, and FPU/SIMD context properly managed. 881 */ 882 sme_init_el3(); 883 sme_enable(ctx); 884 } else { 885 /* 886 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 887 * world can safely use the associated registers. 888 */ 889 sme_disable(ctx); 890 } 891 } 892 #endif /* IMAGE_BL31 */ 893 } 894 895 #if !IMAGE_BL1 896 /******************************************************************************* 897 * The following function initializes the cpu_context for a CPU specified by 898 * its `cpu_idx` for first use, and sets the initial entrypoint state as 899 * specified by the entry_point_info structure. 900 ******************************************************************************/ 901 void cm_init_context_by_index(unsigned int cpu_idx, 902 const entry_point_info_t *ep) 903 { 904 cpu_context_t *ctx; 905 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 906 cm_setup_context(ctx, ep); 907 } 908 #endif /* !IMAGE_BL1 */ 909 910 /******************************************************************************* 911 * The following function initializes the cpu_context for the current CPU 912 * for first use, and sets the initial entrypoint state as specified by the 913 * entry_point_info structure. 914 ******************************************************************************/ 915 void cm_init_my_context(const entry_point_info_t *ep) 916 { 917 cpu_context_t *ctx; 918 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 919 cm_setup_context(ctx, ep); 920 } 921 922 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 923 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 924 { 925 #if INIT_UNUSED_NS_EL2 926 u_register_t hcr_el2 = HCR_RESET_VAL; 927 u_register_t mdcr_el2; 928 u_register_t scr_el3; 929 930 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 931 932 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 933 if ((scr_el3 & SCR_RW_BIT) != 0U) { 934 hcr_el2 |= HCR_RW_BIT; 935 } 936 937 write_hcr_el2(hcr_el2); 938 939 /* 940 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 941 * All fields have architecturally UNKNOWN reset values. 942 */ 943 write_cptr_el2(CPTR_EL2_RESET_VAL); 944 945 /* 946 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 947 * reset and are set to zero except for field(s) listed below. 948 * 949 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 950 * Non-secure EL0 and EL1 accesses to the physical timer registers. 951 * 952 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 953 * Non-secure EL0 and EL1 accesses to the physical counter registers. 954 */ 955 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 956 957 /* 958 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 959 * UNKNOWN value. 960 */ 961 write_cntvoff_el2(0); 962 963 /* 964 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 965 * respectively. 966 */ 967 write_vpidr_el2(read_midr_el1()); 968 write_vmpidr_el2(read_mpidr_el1()); 969 970 /* 971 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 972 * 973 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 974 * translation is disabled, cache maintenance operations depend on the 975 * VMID. 976 * 977 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 978 * disabled. 979 */ 980 write_vttbr_el2(VTTBR_RESET_VAL & 981 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 982 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 983 984 /* 985 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 986 * Some fields are architecturally UNKNOWN on reset. 987 * 988 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 989 * register accesses to the Debug ROM registers are not trapped to EL2. 990 * 991 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 992 * accesses to the powerdown debug registers are not trapped to EL2. 993 * 994 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 995 * debug registers do not trap to EL2. 996 * 997 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 998 * EL2. 999 */ 1000 mdcr_el2 = MDCR_EL2_RESET_VAL & 1001 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1002 MDCR_EL2_TDE_BIT); 1003 1004 write_mdcr_el2(mdcr_el2); 1005 1006 /* 1007 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1008 * 1009 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1010 * EL1 accesses to System registers do not trap to EL2. 1011 */ 1012 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1013 1014 /* 1015 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1016 * reset. 1017 * 1018 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1019 * and prevent timer interrupts. 1020 */ 1021 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1022 1023 manage_extensions_nonsecure_el2_unused(); 1024 #endif /* INIT_UNUSED_NS_EL2 */ 1025 } 1026 1027 /******************************************************************************* 1028 * Prepare the CPU system registers for first entry into realm, secure, or 1029 * normal world. 1030 * 1031 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1032 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1033 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1034 * For all entries, the EL1 registers are initialized from the cpu_context 1035 ******************************************************************************/ 1036 void cm_prepare_el3_exit(uint32_t security_state) 1037 { 1038 u_register_t sctlr_el2, scr_el3; 1039 cpu_context_t *ctx = cm_get_context(security_state); 1040 1041 assert(ctx != NULL); 1042 1043 if (security_state == NON_SECURE) { 1044 uint64_t el2_implemented = el_implemented(2); 1045 1046 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1047 CTX_SCR_EL3); 1048 1049 if (el2_implemented != EL_IMPL_NONE) { 1050 1051 /* 1052 * If context is not being used for EL2, initialize 1053 * HCRX_EL2 with its init value here. 1054 */ 1055 if (is_feat_hcx_supported()) { 1056 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1057 } 1058 1059 /* 1060 * Initialize Fine-grained trap registers introduced 1061 * by FEAT_FGT so all traps are initially disabled when 1062 * switching to EL2 or a lower EL, preventing undesired 1063 * behavior. 1064 */ 1065 if (is_feat_fgt_supported()) { 1066 /* 1067 * Initialize HFG*_EL2 registers with a default 1068 * value so legacy systems unaware of FEAT_FGT 1069 * do not get trapped due to their lack of 1070 * initialization for this feature. 1071 */ 1072 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1073 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1074 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1075 } 1076 1077 /* Condition to ensure EL2 is being used. */ 1078 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1079 /* Initialize SCTLR_EL2 register with reset value. */ 1080 sctlr_el2 = SCTLR_EL2_RES1; 1081 1082 /* 1083 * If workaround of errata 764081 for Cortex-A75 1084 * is used then set SCTLR_EL2.IESB to enable 1085 * Implicit Error Synchronization Barrier. 1086 */ 1087 if (errata_a75_764081_applies()) { 1088 sctlr_el2 |= SCTLR_IESB_BIT; 1089 } 1090 1091 write_sctlr_el2(sctlr_el2); 1092 } else { 1093 /* 1094 * (scr_el3 & SCR_HCE_BIT==0) 1095 * EL2 implemented but unused. 1096 */ 1097 init_nonsecure_el2_unused(ctx); 1098 } 1099 } 1100 } 1101 #if (!CTX_INCLUDE_EL2_REGS) 1102 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1103 cm_el1_sysregs_context_restore(security_state); 1104 #endif 1105 cm_set_next_eret_context(security_state); 1106 } 1107 1108 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1109 1110 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1111 { 1112 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1113 if (is_feat_amu_supported()) { 1114 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1115 } 1116 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1117 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1118 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1119 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1120 } 1121 1122 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1123 { 1124 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1125 if (is_feat_amu_supported()) { 1126 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1127 } 1128 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1129 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1130 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1131 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1132 } 1133 1134 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1135 { 1136 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1137 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1138 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1139 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1140 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1141 } 1142 1143 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1144 { 1145 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1146 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1147 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1148 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1149 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1150 } 1151 1152 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1153 { 1154 u_register_t mpam_idr = read_mpamidr_el1(); 1155 1156 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1157 1158 /* 1159 * The context registers that we intend to save would be part of the 1160 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1161 */ 1162 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1163 return; 1164 } 1165 1166 /* 1167 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1168 * MPAMIDR_HAS_HCR_BIT == 1. 1169 */ 1170 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1171 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1172 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1173 1174 /* 1175 * The number of MPAMVPM registers is implementation defined, their 1176 * number is stored in the MPAMIDR_EL1 register. 1177 */ 1178 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1179 case 7: 1180 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1181 __fallthrough; 1182 case 6: 1183 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1184 __fallthrough; 1185 case 5: 1186 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1187 __fallthrough; 1188 case 4: 1189 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1190 __fallthrough; 1191 case 3: 1192 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1193 __fallthrough; 1194 case 2: 1195 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1196 __fallthrough; 1197 case 1: 1198 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1199 break; 1200 } 1201 } 1202 1203 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1204 { 1205 u_register_t mpam_idr = read_mpamidr_el1(); 1206 1207 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1208 1209 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1210 return; 1211 } 1212 1213 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1214 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1215 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1216 1217 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1218 case 7: 1219 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1220 __fallthrough; 1221 case 6: 1222 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1223 __fallthrough; 1224 case 5: 1225 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1226 __fallthrough; 1227 case 4: 1228 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1229 __fallthrough; 1230 case 3: 1231 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1232 __fallthrough; 1233 case 2: 1234 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1235 __fallthrough; 1236 case 1: 1237 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1238 break; 1239 } 1240 } 1241 1242 /* --------------------------------------------------------------------------- 1243 * The following registers are not added: 1244 * ICH_AP0R<n>_EL2 1245 * ICH_AP1R<n>_EL2 1246 * ICH_LR<n>_EL2 1247 * 1248 * NOTE: For a system with S-EL2 present but not enabled, accessing 1249 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1250 * SCR_EL3.NS = 1 before accessing this register. 1251 * --------------------------------------------------------------------------- 1252 */ 1253 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1254 { 1255 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1256 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1257 #else 1258 u_register_t scr_el3 = read_scr_el3(); 1259 write_scr_el3(scr_el3 | SCR_NS_BIT); 1260 isb(); 1261 1262 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1263 1264 write_scr_el3(scr_el3); 1265 isb(); 1266 #endif 1267 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1268 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1269 } 1270 1271 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1272 { 1273 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1274 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1275 #else 1276 u_register_t scr_el3 = read_scr_el3(); 1277 write_scr_el3(scr_el3 | SCR_NS_BIT); 1278 isb(); 1279 1280 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1281 1282 write_scr_el3(scr_el3); 1283 isb(); 1284 #endif 1285 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1286 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1287 } 1288 1289 /* ----------------------------------------------------- 1290 * The following registers are not added: 1291 * AMEVCNTVOFF0<n>_EL2 1292 * AMEVCNTVOFF1<n>_EL2 1293 * ----------------------------------------------------- 1294 */ 1295 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1296 { 1297 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1298 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1299 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1300 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1301 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1302 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1303 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1304 if (CTX_INCLUDE_AARCH32_REGS) { 1305 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1306 } 1307 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1308 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1309 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1310 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1311 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1312 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1313 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1314 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1315 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1316 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1317 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1318 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1319 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1320 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1321 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1322 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1323 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1324 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1325 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1326 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1327 } 1328 1329 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1330 { 1331 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1332 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1333 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1334 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1335 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1336 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1337 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1338 if (CTX_INCLUDE_AARCH32_REGS) { 1339 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1340 } 1341 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1342 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1343 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1344 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1345 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1346 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1347 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1348 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1349 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1350 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1351 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1352 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1353 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1354 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1355 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1356 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1357 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1358 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1359 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1360 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1361 } 1362 1363 /******************************************************************************* 1364 * Save EL2 sysreg context 1365 ******************************************************************************/ 1366 void cm_el2_sysregs_context_save(uint32_t security_state) 1367 { 1368 cpu_context_t *ctx; 1369 el2_sysregs_t *el2_sysregs_ctx; 1370 1371 ctx = cm_get_context(security_state); 1372 assert(ctx != NULL); 1373 1374 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1375 1376 el2_sysregs_context_save_common(el2_sysregs_ctx); 1377 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1378 1379 if (is_feat_mte2_supported()) { 1380 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1381 } 1382 1383 if (is_feat_mpam_supported()) { 1384 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1385 } 1386 1387 if (is_feat_fgt_supported()) { 1388 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1389 } 1390 1391 if (is_feat_fgt2_supported()) { 1392 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1393 } 1394 1395 if (is_feat_ecv_v2_supported()) { 1396 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1397 } 1398 1399 if (is_feat_vhe_supported()) { 1400 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1401 read_contextidr_el2()); 1402 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1403 } 1404 1405 if (is_feat_ras_supported()) { 1406 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1407 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1408 } 1409 1410 if (is_feat_nv2_supported()) { 1411 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1412 } 1413 1414 if (is_feat_trf_supported()) { 1415 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1416 } 1417 1418 if (is_feat_csv2_2_supported()) { 1419 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1420 read_scxtnum_el2()); 1421 } 1422 1423 if (is_feat_hcx_supported()) { 1424 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1425 } 1426 1427 if (is_feat_tcr2_supported()) { 1428 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1429 } 1430 1431 if (is_feat_sxpie_supported()) { 1432 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1433 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1434 } 1435 1436 if (is_feat_sxpoe_supported()) { 1437 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1438 } 1439 1440 if (is_feat_s2pie_supported()) { 1441 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1442 } 1443 1444 if (is_feat_gcs_supported()) { 1445 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1446 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1447 } 1448 } 1449 1450 /******************************************************************************* 1451 * Restore EL2 sysreg context 1452 ******************************************************************************/ 1453 void cm_el2_sysregs_context_restore(uint32_t security_state) 1454 { 1455 cpu_context_t *ctx; 1456 el2_sysregs_t *el2_sysregs_ctx; 1457 1458 ctx = cm_get_context(security_state); 1459 assert(ctx != NULL); 1460 1461 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1462 1463 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1464 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1465 1466 if (is_feat_mte2_supported()) { 1467 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1468 } 1469 1470 if (is_feat_mpam_supported()) { 1471 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1472 } 1473 1474 if (is_feat_fgt_supported()) { 1475 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1476 } 1477 1478 if (is_feat_fgt2_supported()) { 1479 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1480 } 1481 1482 if (is_feat_ecv_v2_supported()) { 1483 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1484 } 1485 1486 if (is_feat_vhe_supported()) { 1487 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1488 contextidr_el2)); 1489 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1490 } 1491 1492 if (is_feat_ras_supported()) { 1493 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1494 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1495 } 1496 1497 if (is_feat_nv2_supported()) { 1498 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1499 } 1500 1501 if (is_feat_trf_supported()) { 1502 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1503 } 1504 1505 if (is_feat_csv2_2_supported()) { 1506 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1507 scxtnum_el2)); 1508 } 1509 1510 if (is_feat_hcx_supported()) { 1511 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1512 } 1513 1514 if (is_feat_tcr2_supported()) { 1515 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1516 } 1517 1518 if (is_feat_sxpie_supported()) { 1519 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1520 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1521 } 1522 1523 if (is_feat_sxpoe_supported()) { 1524 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1525 } 1526 1527 if (is_feat_s2pie_supported()) { 1528 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1529 } 1530 1531 if (is_feat_gcs_supported()) { 1532 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1533 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1534 } 1535 } 1536 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1537 1538 #if IMAGE_BL31 1539 /********************************************************************************* 1540 * This function allows Architecture features asymmetry among cores. 1541 * TF-A assumes that all the cores in the platform has architecture feature parity 1542 * and hence the context is setup on different core (e.g. primary sets up the 1543 * context for secondary cores).This assumption may not be true for systems where 1544 * cores are not conforming to same Arch version or there is CPU Erratum which 1545 * requires certain feature to be be disabled only on a given core. 1546 * 1547 * This function is called on secondary cores to override any disparity in context 1548 * setup by primary, this would be called during warmboot path. 1549 *********************************************************************************/ 1550 void cm_handle_asymmetric_features(void) 1551 { 1552 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1553 1554 assert(ctx != NULL); 1555 1556 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1557 if (is_feat_spe_supported()) { 1558 spe_enable(ctx); 1559 } else { 1560 spe_disable(ctx); 1561 } 1562 #endif 1563 1564 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1565 if (check_if_affected_core() == ERRATA_APPLIES) { 1566 if (is_feat_trbe_supported()) { 1567 trbe_disable(ctx); 1568 } 1569 } 1570 #endif 1571 1572 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1573 el3_state_t *el3_state = get_el3state_ctx(ctx); 1574 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1575 1576 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1577 tcr2_enable(ctx); 1578 } else { 1579 tcr2_disable(ctx); 1580 } 1581 #endif 1582 1583 } 1584 #endif 1585 1586 /******************************************************************************* 1587 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1588 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1589 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1590 * cm_prepare_el3_exit function. 1591 ******************************************************************************/ 1592 void cm_prepare_el3_exit_ns(void) 1593 { 1594 #if IMAGE_BL31 1595 /* 1596 * Check and handle Architecture feature asymmetry among cores. 1597 * 1598 * In warmboot path secondary cores context is initialized on core which 1599 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1600 * it in this function call. 1601 * For Symmetric cores this is an empty function. 1602 */ 1603 cm_handle_asymmetric_features(); 1604 #endif 1605 1606 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1607 #if ENABLE_ASSERTIONS 1608 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1609 assert(ctx != NULL); 1610 1611 /* Assert that EL2 is used. */ 1612 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1613 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1614 (el_implemented(2U) != EL_IMPL_NONE)); 1615 #endif /* ENABLE_ASSERTIONS */ 1616 1617 /* Restore EL2 sysreg contexts */ 1618 cm_el2_sysregs_context_restore(NON_SECURE); 1619 cm_set_next_eret_context(NON_SECURE); 1620 #else 1621 cm_prepare_el3_exit(NON_SECURE); 1622 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1623 } 1624 1625 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1626 /******************************************************************************* 1627 * The next set of six functions are used by runtime services to save and restore 1628 * EL1 context on the 'cpu_context' structure for the specified security state. 1629 ******************************************************************************/ 1630 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1631 { 1632 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1633 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1634 1635 #if (!ERRATA_SPECULATIVE_AT) 1636 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1637 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1638 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1639 1640 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1641 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1642 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1643 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1644 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1645 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1646 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1647 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1648 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1649 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1650 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1651 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1652 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1653 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1654 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1655 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1656 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1657 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1658 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1659 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1660 1661 if (CTX_INCLUDE_AARCH32_REGS) { 1662 /* Save Aarch32 registers */ 1663 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1664 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1665 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1666 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1667 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1668 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1669 } 1670 1671 if (NS_TIMER_SWITCH) { 1672 /* Save NS Timer registers */ 1673 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1674 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1675 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1676 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1677 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1678 } 1679 1680 if (is_feat_mte2_supported()) { 1681 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1682 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1683 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1684 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1685 } 1686 1687 if (is_feat_ras_supported()) { 1688 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1689 } 1690 1691 if (is_feat_s1pie_supported()) { 1692 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1693 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1694 } 1695 1696 if (is_feat_s1poe_supported()) { 1697 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1698 } 1699 1700 if (is_feat_s2poe_supported()) { 1701 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1702 } 1703 1704 if (is_feat_tcr2_supported()) { 1705 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1706 } 1707 1708 if (is_feat_trf_supported()) { 1709 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1710 } 1711 1712 if (is_feat_csv2_2_supported()) { 1713 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1714 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1715 } 1716 1717 if (is_feat_gcs_supported()) { 1718 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1719 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1720 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1721 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1722 } 1723 1724 if (is_feat_the_supported()) { 1725 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1726 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1727 } 1728 1729 } 1730 1731 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1732 { 1733 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1734 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1735 1736 #if (!ERRATA_SPECULATIVE_AT) 1737 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1738 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1739 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1740 1741 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1742 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1743 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1744 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1745 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1746 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1747 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1748 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1749 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1750 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1751 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1752 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1753 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1754 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1755 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1756 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1757 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1758 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1759 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1760 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1761 1762 if (CTX_INCLUDE_AARCH32_REGS) { 1763 /* Restore Aarch32 registers */ 1764 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1765 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1766 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1767 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1768 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1769 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1770 } 1771 1772 if (NS_TIMER_SWITCH) { 1773 /* Restore NS Timer registers */ 1774 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1775 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1776 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1777 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1778 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1779 } 1780 1781 if (is_feat_mte2_supported()) { 1782 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1783 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1784 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1785 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1786 } 1787 1788 if (is_feat_ras_supported()) { 1789 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1790 } 1791 1792 if (is_feat_s1pie_supported()) { 1793 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1794 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1795 } 1796 1797 if (is_feat_s1poe_supported()) { 1798 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1799 } 1800 1801 if (is_feat_s2poe_supported()) { 1802 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1803 } 1804 1805 if (is_feat_tcr2_supported()) { 1806 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1807 } 1808 1809 if (is_feat_trf_supported()) { 1810 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1811 } 1812 1813 if (is_feat_csv2_2_supported()) { 1814 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1815 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1816 } 1817 1818 if (is_feat_gcs_supported()) { 1819 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1820 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1821 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1822 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1823 } 1824 1825 if (is_feat_the_supported()) { 1826 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1827 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1828 } 1829 } 1830 1831 /******************************************************************************* 1832 * The next couple of functions are used by runtime services to save and restore 1833 * EL1 context on the 'cpu_context' structure for the specified security state. 1834 ******************************************************************************/ 1835 void cm_el1_sysregs_context_save(uint32_t security_state) 1836 { 1837 cpu_context_t *ctx; 1838 1839 ctx = cm_get_context(security_state); 1840 assert(ctx != NULL); 1841 1842 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1843 1844 #if IMAGE_BL31 1845 if (security_state == SECURE) 1846 PUBLISH_EVENT(cm_exited_secure_world); 1847 else 1848 PUBLISH_EVENT(cm_exited_normal_world); 1849 #endif 1850 } 1851 1852 void cm_el1_sysregs_context_restore(uint32_t security_state) 1853 { 1854 cpu_context_t *ctx; 1855 1856 ctx = cm_get_context(security_state); 1857 assert(ctx != NULL); 1858 1859 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1860 1861 #if IMAGE_BL31 1862 if (security_state == SECURE) 1863 PUBLISH_EVENT(cm_entering_secure_world); 1864 else 1865 PUBLISH_EVENT(cm_entering_normal_world); 1866 #endif 1867 } 1868 1869 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1870 1871 /******************************************************************************* 1872 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1873 * given security state with the given entrypoint 1874 ******************************************************************************/ 1875 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1876 { 1877 cpu_context_t *ctx; 1878 el3_state_t *state; 1879 1880 ctx = cm_get_context(security_state); 1881 assert(ctx != NULL); 1882 1883 /* Populate EL3 state so that ERET jumps to the correct entry */ 1884 state = get_el3state_ctx(ctx); 1885 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1886 } 1887 1888 /******************************************************************************* 1889 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1890 * pertaining to the given security state 1891 ******************************************************************************/ 1892 void cm_set_elr_spsr_el3(uint32_t security_state, 1893 uintptr_t entrypoint, uint32_t spsr) 1894 { 1895 cpu_context_t *ctx; 1896 el3_state_t *state; 1897 1898 ctx = cm_get_context(security_state); 1899 assert(ctx != NULL); 1900 1901 /* Populate EL3 state so that ERET jumps to the correct entry */ 1902 state = get_el3state_ctx(ctx); 1903 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1904 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1905 } 1906 1907 /******************************************************************************* 1908 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1909 * pertaining to the given security state using the value and bit position 1910 * specified in the parameters. It preserves all other bits. 1911 ******************************************************************************/ 1912 void cm_write_scr_el3_bit(uint32_t security_state, 1913 uint32_t bit_pos, 1914 uint32_t value) 1915 { 1916 cpu_context_t *ctx; 1917 el3_state_t *state; 1918 u_register_t scr_el3; 1919 1920 ctx = cm_get_context(security_state); 1921 assert(ctx != NULL); 1922 1923 /* Ensure that the bit position is a valid one */ 1924 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1925 1926 /* Ensure that the 'value' is only a bit wide */ 1927 assert(value <= 1U); 1928 1929 /* 1930 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1931 * and set it to its new value. 1932 */ 1933 state = get_el3state_ctx(ctx); 1934 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1935 scr_el3 &= ~(1UL << bit_pos); 1936 scr_el3 |= (u_register_t)value << bit_pos; 1937 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1938 } 1939 1940 /******************************************************************************* 1941 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1942 * given security state. 1943 ******************************************************************************/ 1944 u_register_t cm_get_scr_el3(uint32_t security_state) 1945 { 1946 cpu_context_t *ctx; 1947 el3_state_t *state; 1948 1949 ctx = cm_get_context(security_state); 1950 assert(ctx != NULL); 1951 1952 /* Populate EL3 state so that ERET jumps to the correct entry */ 1953 state = get_el3state_ctx(ctx); 1954 return read_ctx_reg(state, CTX_SCR_EL3); 1955 } 1956 1957 /******************************************************************************* 1958 * This function is used to program the context that's used for exception 1959 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1960 * the required security state 1961 ******************************************************************************/ 1962 void cm_set_next_eret_context(uint32_t security_state) 1963 { 1964 cpu_context_t *ctx; 1965 1966 ctx = cm_get_context(security_state); 1967 assert(ctx != NULL); 1968 1969 cm_set_next_context(ctx); 1970 } 1971