1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. Selects the branch protection features to use: 117- 0: Default value turns off all types of branch protection 118- 1: Enables all types of branch protection features 119- 2: Return address signing to its standard level 120- 3: Extend the signing to include leaf functions 121- 4: Turn on branch target identification mechanism 122 123 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 124 and resulting PAuth/BTI features. 125 126 +-------+--------------+-------+-----+ 127 | Value | GCC option | PAuth | BTI | 128 +=======+==============+=======+=====+ 129 | 0 | none | N | N | 130 +-------+--------------+-------+-----+ 131 | 1 | standard | Y | Y | 132 +-------+--------------+-------+-----+ 133 | 2 | pac-ret | Y | N | 134 +-------+--------------+-------+-----+ 135 | 3 | pac-ret+leaf | Y | N | 136 +-------+--------------+-------+-----+ 137 | 4 | bti | N | Y | 138 +-------+--------------+-------+-----+ 139 140 This option defaults to 0. 141 Note that Pointer Authentication is enabled for Non-secure world 142 irrespective of the value of this option if the CPU supports it. 143 144- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 145 compilation of each build. It must be set to a C string (including quotes 146 where applicable). Defaults to a string that contains the time and date of 147 the compilation. 148 149- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 150 build to be uniquely identified. Defaults to the current git commit id. 151 152- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 153 154- ``CFLAGS``: Extra user options appended on the compiler's command line in 155 addition to the options set by the build system. 156 157- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 158 release several CPUs out of reset. It can take either 0 (several CPUs may be 159 brought up) or 1 (only one CPU will ever be brought up during cold reset). 160 Default is 0. If the platform always brings up a single CPU, there is no 161 need to distinguish between primary and secondary CPUs and the boot path can 162 be optimised. The ``plat_is_my_cpu_primary()`` and 163 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 164 to be implemented in this case. 165 166- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 167 Defaults to ``tbbr``. 168 169- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 170 register state when an unexpected exception occurs during execution of 171 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 172 this is only enabled for a debug build of the firmware. 173 174- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 175 certificate generation tool to create new keys in case no valid keys are 176 present or specified. Allowed options are '0' or '1'. Default is '1'. 177 178- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 179 the AArch32 system registers to be included when saving and restoring the 180 CPU context. The option must be set to 0 for AArch64-only platforms (that 181 is on hardware that does not implement AArch32, or at least not at EL1 and 182 higher ELs). Default value is 1. 183 184- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 185 registers to be included when saving and restoring the CPU context. Default 186 is 0. 187 188- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 189 Memory System Resource Partitioning and Monitoring (MPAM) 190 registers to be included when saving and restoring the CPU context. 191 Default is '0'. 192 193- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 194 registers to be saved/restored when entering/exiting an EL2 execution 195 context. This flag can take values 0 to 2, to align with the 196 ``ENABLE_FEAT`` mechanism. Default value is 0. 197 198- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 199 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 200 to be included when saving and restoring the CPU context as part of world 201 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 202 mechanism. Default value is 0. 203 204 Note that Pointer Authentication is enabled for Non-secure world irrespective 205 of the value of this flag if the CPU supports it. 206 207- ``DEBUG``: Chooses between a debug and release build. It can take either 0 208 (release) or 1 (debug) as values. 0 is the default. 209 210- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 211 authenticated decryption algorithm to be used to decrypt firmware/s during 212 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 213 this flag is ``none`` to disable firmware decryption which is an optional 214 feature as per TBBR. 215 216- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 217 of the binary image. If set to 1, then only the ELF image is built. 218 0 is the default. 219 220- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 221 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 222 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 223 mechanism. Default is ``0``. 224 225- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 226 Board Boot authentication at runtime. This option is meant to be enabled only 227 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 228 flag has to be enabled. 0 is the default. 229 230- ``E``: Boolean option to make warnings into errors. Default is 1. 231 232 When specifying higher warnings levels (``W=1`` and higher), this option 233 defaults to 0. This is done to encourage contributors to use them, as they 234 are expected to produce warnings that would otherwise fail the build. New 235 contributions are still expected to build with ``W=0`` and ``E=1`` (the 236 default). 237 238- ``EARLY_CONSOLE``: This option is used to enable early traces before default 239 console is properly setup. It introduces EARLY_* traces macros, that will 240 use the non-EARLY traces macros if the flag is enabled, or do nothing 241 otherwise. To use this feature, platforms will have to create the function 242 plat_setup_early_console(). 243 Default is 0 (disabled) 244 245- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 246 the normal boot flow. It must specify the entry point address of the EL3 247 payload. Please refer to the "Booting an EL3 payload" section for more 248 details. 249 250- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 251 (also known as group 1 counters). These are implementation-defined counters, 252 and as such require additional platform configuration. Default is 0. 253 254- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 255 allows platforms with auxiliary counters to describe them via the 256 ``HW_CONFIG`` device tree blob. Default is 0. 257 258- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 259 are compiled out. For debug builds, this option defaults to 1, and calls to 260 ``assert()`` are left in place. For release builds, this option defaults to 0 261 and calls to ``assert()`` function are compiled out. This option can be set 262 independently of ``DEBUG``. It can also be used to hide any auxiliary code 263 that is only required for the assertion and does not fit in the assertion 264 itself. 265 266- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 267 dumps or not. It is supported in both AArch64 and AArch32. However, in 268 AArch32 the format of the frame records are not defined in the AAPCS and they 269 are defined by the implementation. This implementation of backtrace only 270 supports the format used by GCC when T32 interworking is disabled. For this 271 reason enabling this option in AArch32 will force the compiler to only 272 generate A32 code. This option is enabled by default only in AArch64 debug 273 builds, but this behaviour can be overridden in each platform's Makefile or 274 in the build command line. 275 276- ``ENABLE_FEAT`` 277 The Arm architecture defines several architecture extension features, 278 named FEAT_xxx in the architecure manual. Some of those features require 279 setup code in higher exception levels, other features might be used by TF-A 280 code itself. 281 Most of the feature flags defined in the TF-A build system permit to take 282 the values 0, 1 or 2, with the following meaning: 283 284 :: 285 286 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 287 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 288 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 289 290 When setting the flag to 0, the feature is disabled during compilation, 291 and the compiler's optimisation stage and the linker will try to remove 292 as much of this code as possible. 293 If it is defined to 1, the code will use the feature unconditionally, so the 294 CPU is expected to support that feature. The FEATURE_DETECTION debug 295 feature, if enabled, will verify this. 296 If the feature flag is set to 2, support for the feature will be compiled 297 in, but its existence will be checked at runtime, so it works on CPUs with 298 or without the feature. This is mostly useful for platforms which either 299 support multiple different CPUs, or where the CPU is configured at runtime, 300 like in emulators. 301 302- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 303 extensions. This flag can take the values 0 to 2, to align with the 304 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 305 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 306 and this option can be used to enable this feature on those systems as well. 307 This flag can take the values 0 to 2, the default is 0. 308 309- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 310 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 311 onwards. This flag can take the values 0 to 2, to align with the 312 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 313 314- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 315 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 316 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 317 optional feature available on Arm v8.0 onwards. This flag can take values 318 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 319 Default value is ``0``. 320 321- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 322 extension. This feature is supported in AArch64 state only and is an optional 323 feature available in Arm v8.0 implementations. 324 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 325 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 326 mechanism. Default value is ``0``. 327 328- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 329 extension which allows the ability to implement more than 16 breakpoints 330 and/or watchpoints. This feature is mandatory from v8.9 and is optional 331 from v8.8. This flag can take the values of 0 to 2, to align with the 332 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 333 334- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 335 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 336 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 337 and upwards. This flag can take the values 0 to 2, to align with the 338 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 339 340- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 341 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 342 Physical Offset register) during EL2 to EL3 context save/restore operations. 343 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 344 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 345 mechanism. Default value is ``0``. 346 347- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 348 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 349 Read Trap Register) during EL2 to EL3 context save/restore operations. 350 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 351 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 352 mechanism. Default value is ``0``. 353 354- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 355 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 356 during EL2 to EL3 context save/restore operations. 357 Its an optional architectural feature and is available from v8.8 and upwards. 358 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 359 mechanism. Default value is ``0``. 360 361- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 362 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 363 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 364 mandatory architectural feature and is enabled from v8.7 and upwards. This 365 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 366 mechanism. Default value is ``0``. 367 368- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 369 if the platform wants to use this feature and MTE2 is enabled at ELX. 370 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 371 mechanism. Default value is ``0``. 372 373- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 374 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 375 permission fault for any privileged data access from EL1/EL2 to virtual 376 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 377 mandatory architectural feature and is enabled from v8.1 and upwards. This 378 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 379 mechanism. Default value is ``0``. 380 381- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 382 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 383 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 384 mechanism. Default value is ``0``. 385 386- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 387 extension. This feature is only supported in AArch64 state. This flag can 388 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 389 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 390 Armv8.5 onwards. 391 392- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 393 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 394 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 395 later CPUs. It is enabled from v8.5 and upwards and if needed can be 396 overidden from platforms explicitly. 397 398- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 399 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 400 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 401 mechanism. Default is ``0``. 402 403- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 404 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 405 available on Arm v8.6. This flag can take values 0 to 2, to align with the 406 ``ENABLE_FEAT`` mechanism. Default is ``0``. 407 408 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 409 delayed by the amount of value in ``TWED_DELAY``. 410 411- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 412 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 413 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 414 architectural feature and is enabled from v8.1 and upwards. It can take 415 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 416 Default value is ``0``. 417 418- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 419 allow access to TCR2_EL2 (extended translation control) from EL2 as 420 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 421 mandatory architectural feature and is enabled from v8.9 and upwards. This 422 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 423 mechanism. Default value is ``0``. 424 425- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 426 at EL2 and below, and context switch relevant registers. This flag 427 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 428 mechanism. Default value is ``0``. 429 430- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 431 at EL2 and below, and context switch relevant registers. This flag 432 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 433 mechanism. Default value is ``0``. 434 435- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 436 at EL2 and below, and context switch relevant registers. This flag 437 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 438 mechanism. Default value is ``0``. 439 440- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 441 at EL2 and below, and context switch relevant registers. This flag 442 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 443 mechanism. Default value is ``0``. 444 445- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 446 allow use of Guarded Control Stack from EL2 as well as adding the GCS 447 registers to the EL2 context save/restore operations. This flag can take 448 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 449 Default value is ``0``. 450 451- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 452 support in GCC for TF-A. This option is currently only supported for 453 AArch64. Default is 0. 454 455- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 456 feature. MPAM is an optional Armv8.4 extension that enables various memory 457 system components and resources to define partitions; software running at 458 various ELs can assign themselves to desired partition to control their 459 performance aspects. 460 461 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 462 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 463 access their own MPAM registers without trapping into EL3. This option 464 doesn't make use of partitioning in EL3, however. Platform initialisation 465 code should configure and use partitions in EL3 as required. This option 466 defaults to ``2`` since MPAM is enabled by default for NS world only. 467 The flag is automatically disabled when the target 468 architecture is AArch32. 469 470- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 471 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 472 firmware to detect and limit high activity events to assist in SoC processor 473 power domain dynamic power budgeting and limit the triggering of whole-rail 474 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 475 476- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 477 allows platforms with cores supporting MPMM to describe them via the 478 ``HW_CONFIG`` device tree blob. Default is 0. 479 480- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 481 support within generic code in TF-A. This option is currently only supported 482 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 483 in BL32 (SP_min) for AARCH32. Default is 0. 484 485- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 486 Measurement Framework(PMF). Default is 0. 487 488- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 489 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 490 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 491 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 492 software. 493 494- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 495 instrumentation which injects timestamp collection points into TF-A to 496 allow runtime performance to be measured. Currently, only PSCI is 497 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 498 as well. Default is 0. 499 500- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 501 extensions. This is an optional architectural feature for AArch64. 502 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 503 mechanism. The default is 2 but is automatically disabled when the target 504 architecture is AArch32. 505 506- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 507 (SVE) for the Non-secure world only. SVE is an optional architectural feature 508 for AArch64. Note that when SVE is enabled for the Non-secure world, access 509 to SIMD and floating-point functionality from the Secure world is disabled by 510 default and controlled with ENABLE_SVE_FOR_SWD. 511 This is to avoid corruption of the Non-secure world data in the Z-registers 512 which are aliased by the SIMD and FP registers. The build option is not 513 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 514 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 515 enabled. This flag can take the values 0 to 2, to align with the 516 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 517 used on systems that have SPM_MM enabled. The default is 1. 518 519- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 520 SVE is an optional architectural feature for AArch64. Note that this option 521 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 522 automatically disabled when the target architecture is AArch32. 523 524- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 525 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 526 default value is set to "none". "strong" is the recommended stack protection 527 level if this feature is desired. "none" disables the stack protection. For 528 all values other than "none", the ``plat_get_stack_protector_canary()`` 529 platform hook needs to be implemented. The value is passed as the last 530 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 531 532- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 533 flag depends on ``DECRYPTION_SUPPORT`` build flag. 534 535- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 536 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 537 538- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 539 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 540 on ``DECRYPTION_SUPPORT`` build flag. 541 542- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 543 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 544 build flag. 545 546- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 547 deprecated platform APIs, helper functions or drivers within Trusted 548 Firmware as error. It can take the value 1 (flag the use of deprecated 549 APIs as error) or 0. The default is 0. 550 551- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 552 configure an Arm® Ethos™-N NPU. To use this service the target platform's 553 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 554 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 555 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 556 557- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 558 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 559 ``TRUSTED_BOARD_BOOT`` to be enabled. 560 561- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 562 (```ethosn.bin```). This firmware image will be included in the FIP and 563 loaded at runtime. 564 565- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 566 targeted at EL3. When set ``0`` (default), no exceptions are expected or 567 handled at EL3, and a panic will result. The exception to this rule is when 568 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 569 occuring during normal world execution, are trapped to EL3. Any exception 570 trapped during secure world execution are trapped to the SPMC. This is 571 supported only for AArch64 builds. 572 573- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 574 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 575 Default value is 40 (LOG_LEVEL_INFO). 576 577- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 578 injection from lower ELs, and this build option enables lower ELs to use 579 Error Records accessed via System Registers to inject faults. This is 580 applicable only to AArch64 builds. 581 582 This feature is intended for testing purposes only, and is advisable to keep 583 disabled for production images. 584 585- ``FIP_NAME``: This is an optional build option which specifies the FIP 586 filename for the ``fip`` target. Default is ``fip.bin``. 587 588- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 589 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 590 591- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 592 593 :: 594 595 0: Encryption is done with Secret Symmetric Key (SSK) which is common 596 for a class of devices. 597 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 598 unique per device. 599 600 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 601 602- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 603 tool to create certificates as per the Chain of Trust described in 604 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 605 include the certificates in the FIP and FWU_FIP. Default value is '0'. 606 607 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 608 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 609 the corresponding certificates, and to include those certificates in the 610 FIP and FWU_FIP. 611 612 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 613 images will not include support for Trusted Board Boot. The FIP will still 614 include the corresponding certificates. This FIP can be used to verify the 615 Chain of Trust on the host machine through other mechanisms. 616 617 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 618 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 619 will not include the corresponding certificates, causing a boot failure. 620 621- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 622 inherent support for specific EL3 type interrupts. Setting this build option 623 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 624 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 625 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 626 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 627 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 628 the Secure Payload interrupts needs to be synchronously handed over to Secure 629 EL1 for handling. The default value of this option is ``0``, which means the 630 Group 0 interrupts are assumed to be handled by Secure EL1. 631 632- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 633 Interrupts, resulting from errors in NS world, will be always trapped in 634 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 635 will be trapped in the current exception level (or in EL1 if the current 636 exception level is EL0). 637 638- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 639 software operations are required for CPUs to enter and exit coherency. 640 However, newer systems exist where CPUs' entry to and exit from coherency 641 is managed in hardware. Such systems require software to only initiate these 642 operations, and the rest is managed in hardware, minimizing active software 643 management. In such systems, this boolean option enables TF-A to carry out 644 build and run-time optimizations during boot and power management operations. 645 This option defaults to 0 and if it is enabled, then it implies 646 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 647 648 If this flag is disabled while the platform which TF-A is compiled for 649 includes cores that manage coherency in hardware, then a compilation error is 650 generated. This is based on the fact that a system cannot have, at the same 651 time, cores that manage coherency in hardware and cores that don't. In other 652 words, a platform cannot have, at the same time, cores that require 653 ``HW_ASSISTED_COHERENCY=1`` and cores that require 654 ``HW_ASSISTED_COHERENCY=0``. 655 656 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 657 translation library (xlat tables v2) must be used; version 1 of translation 658 library is not supported. 659 660- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 661 implementation defined system register accesses from lower ELs. Default 662 value is ``0``. 663 664- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 665 bottom, higher addresses at the top. This build flag can be set to '1' to 666 invert this behavior. Lower addresses will be printed at the top and higher 667 addresses at the bottom. 668 669- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 670 used for generating the PKCS keys and subsequent signing of the certificate. 671 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 672 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 673 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 674 compatibility. The default value of this flag is ``rsa`` which is the TBBR 675 compliant PKCS#1 RSA 2.1 scheme. 676 677- ``KEY_SIZE``: This build flag enables the user to select the key size for 678 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 679 depend on the chosen algorithm and the cryptographic module. 680 681 +---------------------------+------------------------------------+ 682 | KEY_ALG | Possible key sizes | 683 +===========================+====================================+ 684 | rsa | 1024 , 2048 (default), 3072, 4096 | 685 +---------------------------+------------------------------------+ 686 | ecdsa | 256 (default), 384 | 687 +---------------------------+------------------------------------+ 688 | ecdsa-brainpool-regular | unavailable | 689 +---------------------------+------------------------------------+ 690 | ecdsa-brainpool-twisted | unavailable | 691 +---------------------------+------------------------------------+ 692 693- ``HASH_ALG``: This build flag enables the user to select the secure hash 694 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 695 The default value of this flag is ``sha256``. 696 697- ``LDFLAGS``: Extra user options appended to the linkers' command line in 698 addition to the one set by the build system. 699 700- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 701 output compiled into the build. This should be one of the following: 702 703 :: 704 705 0 (LOG_LEVEL_NONE) 706 10 (LOG_LEVEL_ERROR) 707 20 (LOG_LEVEL_NOTICE) 708 30 (LOG_LEVEL_WARNING) 709 40 (LOG_LEVEL_INFO) 710 50 (LOG_LEVEL_VERBOSE) 711 712 All log output up to and including the selected log level is compiled into 713 the build. The default value is 40 in debug builds and 20 in release builds. 714 715- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 716 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 717 provide trust that the code taking the measurements and recording them has 718 not been tampered with. 719 720 This option defaults to 0. 721 722- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 723 options to the compiler. An example usage: 724 725 .. code:: make 726 727 MARCH_DIRECTIVE := -march=armv8.5-a 728 729- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 730 options to the compiler currently supporting only of the options. 731 GCC documentation: 732 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 733 734 An example usage: 735 736 .. code:: make 737 738 HARDEN_SLS := 1 739 740 This option defaults to 0. 741 742- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 743 specifies a file that contains the Non-Trusted World private key in PEM 744 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 745 will be used to save the key. 746 747- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 748 optional. It is only needed if the platform makefile specifies that it 749 is required in order to build the ``fwu_fip`` target. 750 751- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 752 contents upon world switch. It can take either 0 (don't save and restore) or 753 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 754 wants the timer registers to be saved and restored. 755 756- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 757 for the BL image. It can be either 0 (include) or 1 (remove). The default 758 value is 0. 759 760- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 761 the underlying hardware is not a full PL011 UART but a minimally compliant 762 generic UART, which is a subset of the PL011. The driver will not access 763 any register that is not part of the SBSA generic UART specification. 764 Default value is 0 (a full PL011 compliant UART is present). 765 766- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 767 must be subdirectory of any depth under ``plat/``, and must contain a 768 platform makefile named ``platform.mk``. For example, to build TF-A for the 769 Arm Juno board, select PLAT=juno. 770 771- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 772 each core as well as the global context. The data includes the memory used 773 by each world and each privileged exception level. This build option is 774 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 775 776- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 777 instead of the normal boot flow. When defined, it must specify the entry 778 point address for the preloaded BL33 image. This option is incompatible with 779 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 780 over ``PRELOADED_BL33_BASE``. 781 782- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 783 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 784 registers when the cluster goes through a power cycle. This is disabled by 785 default and platforms that require this feature have to enable them. 786 787- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 788 vector address can be programmed or is fixed on the platform. It can take 789 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 790 programmable reset address, it is expected that a CPU will start executing 791 code directly at the right address, both on a cold and warm reset. In this 792 case, there is no need to identify the entrypoint on boot and the boot path 793 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 794 does not need to be implemented in this case. 795 796- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 797 possible for the PSCI power-state parameter: original and extended State-ID 798 formats. This flag if set to 1, configures the generic PSCI layer to use the 799 extended format. The default value of this flag is 0, which means by default 800 the original power-state format is used by the PSCI implementation. This flag 801 should be specified by the platform makefile and it governs the return value 802 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 803 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 804 set to 1 as well. 805 806- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 807 OS-initiated mode. This option defaults to 0. 808 809- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 810 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 811 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 812 NOTE: This flag enables use of IESB capability to reduce entry latency into 813 EL3 even when RAS error handling is not performed on the platform. Hence this 814 flag is recommended to be turned on Armv8.2 and later CPUs. 815 816- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 817 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 818 entrypoint) or 1 (CPU reset to BL31 entrypoint). 819 The default value is 0. 820 821- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 822 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 823 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 824 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 825 826- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 827- blocks) covered by a single bit of the bitlock structure during RME GPT 828- operations. The lower the block size, the better opportunity for 829- parallelising GPT operations but at the cost of more bits being needed 830- for the bitlock structure. This numeric parameter can take the values 831- from 0 to 512 and must be a power of 2. The value of 0 is special and 832- and it chooses a single spinlock for all GPT L1 table entries. Default 833- value is 1 which corresponds to block size of 512MB per bit of bitlock 834- structure. 835 836- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 837 supported contiguous blocks in GPT Library. This parameter can take the 838 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 839 descriptors. Default value is 2. 840 841- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 842 file that contains the ROT private key in PEM format or a PKCS11 URI and 843 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 844 accepted and it will be used to save the key. 845 846- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 847 certificate generation tool to save the keys used to establish the Chain of 848 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 849 850- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 851 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 852 target. 853 854- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 855 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 856 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 857 858- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 859 optional. It is only needed if the platform makefile specifies that it 860 is required in order to build the ``fwu_fip`` target. 861 862- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 863 Delegated Exception Interface to BL31 image. This defaults to ``0``. 864 865 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 866 set to ``1``. 867 868- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 869 isolated on separate memory pages. This is a trade-off between security and 870 memory usage. See "Isolating code and read-only data on separate memory 871 pages" section in :ref:`Firmware Design`. This flag is disabled by default 872 and affects all BL images. 873 874- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 875 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 876 allocated in RAM discontiguous from the loaded firmware image. When set, the 877 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 878 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 879 sections are placed in RAM immediately following the loaded firmware image. 880 881- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 882 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 883 discontiguous from loaded firmware images. When set, the platform need to 884 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 885 flag is disabled by default and NOLOAD sections are placed in RAM immediately 886 following the loaded firmware image. 887 888- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 889 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 890 UEFI+ACPI this can provide a certain amount of OS forward compatibility 891 with newer platforms that aren't ECAM compliant. 892 893- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 894 This build option is only valid if ``ARCH=aarch64``. The value should be 895 the path to the directory containing the SPD source, relative to 896 ``services/spd/``; the directory is expected to contain a makefile called 897 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 898 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 899 cannot be enabled when the ``SPM_MM`` option is enabled. 900 901- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 902 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 903 execution in BL1 just before handing over to BL31. At this point, all 904 firmware images have been loaded in memory, and the MMU and caches are 905 turned off. Refer to the "Debugging options" section for more details. 906 907- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 908 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 909 component runs at the EL3 exception level. The default value is ``0`` ( 910 disabled). This configuration supports pre-Armv8.4 platforms (aka not 911 implementing the ``FEAT_SEL2`` extension). 912 913- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 914 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 915 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 916 917- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 918 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 919 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 920 mechanism should be used. 921 922- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 923 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 924 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 925 extension. This is the default when enabling the SPM Dispatcher. When 926 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 927 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 928 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 929 extension). 930 931- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 932 Partition Manager (SPM) implementation. The default value is ``0`` 933 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 934 enabled (``SPD=spmd``). 935 936- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 937 description of secure partitions. The build system will parse this file and 938 package all secure partition blobs into the FIP. This file is not 939 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 940 941- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 942 secure interrupts (caught through the FIQ line). Platforms can enable 943 this directive if they need to handle such interruption. When enabled, 944 the FIQ are handled in monitor mode and non secure world is not allowed 945 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 946 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 947 948- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 949 Platforms can configure this if they need to lower the hardware 950 limit, for example due to asymmetric configuration or limitations of 951 software run at lower ELs. The default is the architectural maximum 952 of 2048 which should be suitable for most configurations, the 953 hardware will limit the effective VL to the maximum physically supported 954 VL. 955 956- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 957 Random Number Generator Interface to BL31 image. This defaults to ``0``. 958 959- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 960 Boot feature. When set to '1', BL1 and BL2 images include support to load 961 and verify the certificates and images in a FIP, and BL1 includes support 962 for the Firmware Update. The default value is '0'. Generation and inclusion 963 of certificates in the FIP and FWU_FIP depends upon the value of the 964 ``GENERATE_COT`` option. 965 966 .. warning:: 967 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 968 already exist in disk, they will be overwritten without further notice. 969 970- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 971 specifies a file that contains the Trusted World private key in PEM 972 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 973 it will be used to save the key. 974 975- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 976 synchronous, (see "Initializing a BL32 Image" section in 977 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 978 synchronous method) or 1 (BL32 is initialized using asynchronous method). 979 Default is 0. 980 981- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 982 routing model which routes non-secure interrupts asynchronously from TSP 983 to EL3 causing immediate preemption of TSP. The EL3 is responsible 984 for saving and restoring the TSP context in this routing model. The 985 default routing model (when the value is 0) is to route non-secure 986 interrupts to TSP allowing it to save its context and hand over 987 synchronously to EL3 via an SMC. 988 989 .. note:: 990 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 991 must also be set to ``1``. 992 993- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 994 internal-trusted-storage) as SP in tb_fw_config device tree. 995 996- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 997 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 998 this delay. It can take values in the range (0-15). Default value is ``0`` 999 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1000 Platforms need to explicitly update this value based on their requirements. 1001 1002- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1003 linker. When the ``LINKER`` build variable points to the armlink linker, 1004 this flag is enabled automatically. To enable support for armlink, platforms 1005 will have to provide a scatter file for the BL image. Currently, Tegra 1006 platforms use the armlink support to compile BL3-1 images. 1007 1008- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1009 memory region in the BL memory map or not (see "Use of Coherent memory in 1010 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1011 (Coherent memory region is included) or 0 (Coherent memory region is 1012 excluded). Default is 1. 1013 1014- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1015 firmware configuration framework. This will move the io_policies into a 1016 configuration device tree, instead of static structure in the code base. 1017 1018- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1019 at runtime using fconf. If this flag is enabled, COT descriptors are 1020 statically captured in tb_fw_config file in the form of device tree nodes 1021 and properties. Currently, COT descriptors used by BL2 are moved to the 1022 device tree and COT descriptors used by BL1 are retained in the code 1023 base statically. 1024 1025- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1026 runtime using firmware configuration framework. The platform specific SDEI 1027 shared and private events configuration is retrieved from device tree rather 1028 than static C structures at compile time. This is only supported if 1029 SDEI_SUPPORT build flag is enabled. 1030 1031- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1032 and Group1 secure interrupts using the firmware configuration framework. The 1033 platform specific secure interrupt property descriptor is retrieved from 1034 device tree in runtime rather than depending on static C structure at compile 1035 time. 1036 1037- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1038 This feature creates a library of functions to be placed in ROM and thus 1039 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1040 is 0. 1041 1042- ``V``: Verbose build. If assigned anything other than 0, the build commands 1043 are printed. Default is 0. 1044 1045- ``VERSION_STRING``: String used in the log output for each TF-A image. 1046 Defaults to a string formed by concatenating the version number, build type 1047 and build string. 1048 1049- ``W``: Warning level. Some compiler warning options of interest have been 1050 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1051 each level enabling more warning options. Default is 0. 1052 1053 This option is closely related to the ``E`` option, which enables 1054 ``-Werror``. 1055 1056 - ``W=0`` (default) 1057 1058 Enables a wide assortment of warnings, most notably ``-Wall`` and 1059 ``-Wextra``, as well as various bad practices and things that are likely to 1060 result in errors. Includes some compiler specific flags. No warnings are 1061 expected at this level for any build. 1062 1063 - ``W=1`` 1064 1065 Enables warnings we want the generic build to include but are too time 1066 consuming to fix at the moment. It re-enables warnings taken out for 1067 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1068 to eventually be merged into ``W=0``. Some warnings are expected on some 1069 builds, but new contributions should not introduce new ones. 1070 1071 - ``W=2`` (recommended) 1072 1073 Enables warnings we want the generic build to include but cannot be enabled 1074 due to external libraries. This level is expected to eventually be merged 1075 into ``W=0``. Lots of warnings are expected, primarily from external 1076 libraries like zlib and compiler-rt, but new controbutions should not 1077 introduce new ones. 1078 1079 - ``W=3`` 1080 1081 Enables warnings that are informative but not necessary and generally too 1082 verbose and frequently ignored. A very large number of warnings are 1083 expected. 1084 1085 The exact set of warning flags depends on the compiler and TF-A warning 1086 level, however they are all succinctly set in the top-level Makefile. Please 1087 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1088 individual flags. 1089 1090- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1091 the CPU after warm boot. This is applicable for platforms which do not 1092 require interconnect programming to enable cache coherency (eg: single 1093 cluster platforms). If this option is enabled, then warm boot path 1094 enables D-caches immediately after enabling MMU. This option defaults to 0. 1095 1096- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1097 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1098 default value of this flag is ``no``. Note this option must be enabled only 1099 for ARM architecture greater than Armv8.5-A. 1100 1101- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1102 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1103 The default value of this flag is ``0``. 1104 1105 ``AT`` speculative errata workaround disables stage1 page table walk for 1106 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1107 produces either the correct result or failure without TLB allocation. 1108 1109 This boolean option enables errata for all below CPUs. 1110 1111 +---------+--------------+-------------------------+ 1112 | Errata | CPU | Workaround Define | 1113 +=========+==============+=========================+ 1114 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1115 +---------+--------------+-------------------------+ 1116 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1117 +---------+--------------+-------------------------+ 1118 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1119 +---------+--------------+-------------------------+ 1120 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1121 +---------+--------------+-------------------------+ 1122 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1123 +---------+--------------+-------------------------+ 1124 1125 .. note:: 1126 This option is enabled by build only if platform sets any of above defines 1127 mentioned in ’Workaround Define' column in the table. 1128 If this option is enabled for the EL3 software then EL2 software also must 1129 implement this workaround due to the behaviour of the errata mentioned 1130 in new SDEN document which will get published soon. 1131 1132- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1133 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1134 This flag is disabled by default. 1135 1136- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1137 host machine where a custom installation of OpenSSL is located, which is used 1138 to build the certificate generation, firmware encryption and FIP tools. If 1139 this option is not set, the default OS installation will be used. 1140 1141- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1142 functions that wait for an arbitrary time length (udelay and mdelay). The 1143 default value is 0. 1144 1145- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1146 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1147 optional architectural feature for AArch64. This flag can take the values 1148 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1149 and it is automatically disabled when the target architecture is AArch32. 1150 1151- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1152 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1153 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1154 feature for AArch64. This flag can take the values 0 to 2, to align with the 1155 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1156 disabled when the target architecture is AArch32. 1157 1158- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1159 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1160 but unused). This feature is available if trace unit such as ETMv4.x, and 1161 ETE(extending ETM feature) is implemented. This flag can take the values 1162 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1163 1164- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1165 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1166 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1167 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1168 1169- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1170 ``plat_can_cmo`` which will return zero if cache management operations should 1171 be skipped and non-zero otherwise. By default, this option is disabled which 1172 means platform hook won't be checked and CMOs will always be performed when 1173 related functions are called. 1174 1175- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1176 firmware interface for the BL31 image. By default its disabled (``0``). 1177 1178- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1179 errata mitigation for platforms with a non-arm interconnect using the errata 1180 ABI. By default its disabled (``0``). 1181 1182- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1183 driver(s). By default it is disabled (``0``) because it constitutes an attack 1184 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1185 This option should only be enabled on a need basis if there is a use case for 1186 reading characters from the console. 1187 1188GICv3 driver options 1189-------------------- 1190 1191GICv3 driver files are included using directive: 1192 1193``include drivers/arm/gic/v3/gicv3.mk`` 1194 1195The driver can be configured with the following options set in the platform 1196makefile: 1197 1198- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1199 Enabling this option will add runtime detection support for the 1200 GIC-600, so is safe to select even for a GIC500 implementation. 1201 This option defaults to 0. 1202 1203- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1204 for GIC-600 AE. Enabling this option will introduce support to initialize 1205 the FMU. Platforms should call the init function during boot to enable the 1206 FMU and its safety mechanisms. This option defaults to 0. 1207 1208- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1209 functionality. This option defaults to 0 1210 1211- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1212 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1213 functions. This is required for FVP platform which need to simulate GIC save 1214 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1215 1216- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1217 This option defaults to 0. 1218 1219- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1220 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1221 1222Debugging options 1223----------------- 1224 1225To compile a debug version and make the build more verbose use 1226 1227.. code:: shell 1228 1229 make PLAT=<platform> DEBUG=1 V=1 all 1230 1231AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1232(for example Arm-DS) might not support this and may need an older version of 1233DWARF symbols to be emitted by GCC. This can be achieved by using the 1234``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1235the version to 4 is recommended for Arm-DS. 1236 1237When debugging logic problems it might also be useful to disable all compiler 1238optimizations by using ``-O0``. 1239 1240.. warning:: 1241 Using ``-O0`` could cause output images to be larger and base addresses 1242 might need to be recalculated (see the **Memory layout on Arm development 1243 platforms** section in the :ref:`Firmware Design`). 1244 1245Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1246``LDFLAGS``: 1247 1248.. code:: shell 1249 1250 CFLAGS='-O0 -gdwarf-2' \ 1251 make PLAT=<platform> DEBUG=1 V=1 all 1252 1253Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1254ignored as the linker is called directly. 1255 1256It is also possible to introduce an infinite loop to help in debugging the 1257post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1258``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1259section. In this case, the developer may take control of the target using a 1260debugger when indicated by the console output. When using Arm-DS, the following 1261commands can be used: 1262 1263:: 1264 1265 # Stop target execution 1266 interrupt 1267 1268 # 1269 # Prepare your debugging environment, e.g. set breakpoints 1270 # 1271 1272 # Jump over the debug loop 1273 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1274 1275 # Resume execution 1276 continue 1277 1278.. _build_options_experimental: 1279 1280Experimental build options 1281--------------------------- 1282 1283Common build options 1284~~~~~~~~~~~~~~~~~~~~ 1285 1286- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1287 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1288 set to ``1`` then measurements and additional metadata collected during the 1289 measured boot process are sent to the DICE Protection Environment for storage 1290 and processing. A certificate chain, which represents the boot state of the 1291 device, can be queried from the DPE. 1292 1293- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1294 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1295 the measurements and recording them as per `PSA DRTM specification`_. For 1296 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1297 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1298 should have mechanism to authenticate BL31. This option defaults to 0. 1299 1300- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1301 Management Extension. This flag can take the values 0 to 2, to align with 1302 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1303 1304- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1305 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1306 registers so are enabled together. Using this option without 1307 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1308 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1309 superset of SVE. SME is an optional architectural feature for AArch64. 1310 At this time, this build option cannot be used on systems that have 1311 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1312 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1313 mechanism. Default is 0. 1314 1315- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1316 version 2 (SME2) for the non-secure world only. SME2 is an optional 1317 architectural feature for AArch64. 1318 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1319 accesses will still be trapped. This flag can take the values 0 to 2, to 1320 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1321 1322- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1323 Extension for secure world. Used along with SVE and FPU/SIMD. 1324 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1325 Default is 0. 1326 1327- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1328 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1329 for logical partitions in EL3, managed by the SPMD as defined in the 1330 FF-A v1.2 specification. This flag is disabled by default. This flag 1331 must not be used if ``SPMC_AT_EL3`` is enabled. 1332 1333- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1334 verification mechanism. This is a debug feature that compares the 1335 architectural features enabled through the feature specific build flags 1336 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1337 and reports any discrepancies. 1338 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1339 1340 It is expected that this feature is only used for flexible platforms like 1341 software emulators, or for hardware platforms at bringup time, to verify 1342 that the configured feature set matches the CPU. 1343 The ``FEATURE_DETECTION`` macro is disabled by default. 1344 1345- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1346 The platform will use PSA compliant Crypto APIs during authentication and 1347 image measurement process by enabling this option. It uses APIs defined as 1348 per the `PSA Crypto API specification`_. This feature is only supported if 1349 using MbedTLS 3.x version. It is disabled (``0``) by default. 1350 1351- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1352 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1353 This defaults to ``0``. Current implementation follows the Firmware Handoff 1354 specification v0.9. 1355 1356- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1357 interface through BL31 as a SiP SMC function. 1358 Default is disabled (0). 1359 1360Firmware update options 1361~~~~~~~~~~~~~~~~~~~~~~~ 1362 1363- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1364 `PSA FW update specification`_. The default value is 0. 1365 PSA firmware update implementation has few limitations, such as: 1366 1367 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1368 be updated, then it should be done through another platform-defined 1369 mechanism. 1370 1371 - It assumes the platform's hardware supports CRC32 instructions. 1372 1373- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1374 in defining the firmware update metadata structure. This flag is by default 1375 set to '2'. 1376 1377- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1378 firmware bank. Each firmware bank must have the same number of images as per 1379 the `PSA FW update specification`_. 1380 This flag is used in defining the firmware update metadata structure. This 1381 flag is by default set to '1'. 1382 1383- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1384 metadata contains image description. The default value is 1. 1385 1386 The version 2 of the FWU metadata allows for an opaque metadata 1387 structure where a platform can choose to not include the firmware 1388 store description in the metadata structure. This option indicates 1389 if the firmware store description, which provides information on 1390 the updatable images is part of the structure. 1391 1392-------------- 1393 1394*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1395 1396.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1397.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1398.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1399.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1400.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1401.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1402.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1403