1 /* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 #include <plat/common/platform.h> 19 #include <plat_arm.h> 20 #include <plat_console.h> 21 #include <plat_clkfunc.h> 22 23 #include <plat_fdt.h> 24 #include <plat_private.h> 25 #include <plat_startup.h> 26 #include "pm_api_sys.h" 27 #include "pm_client.h" 28 #include <pm_ipi.h> 29 #include <versal_def.h> 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Return a pointer to the 'entry_point_info' structure of the next image for 36 * the security state specified. BL33 corresponds to the non-secure image type 37 * while BL32 corresponds to the secure image type. A NULL pointer is returned 38 * if the image does not exist. 39 */ 40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 assert(sec_state_is_valid(type)); 43 44 if (type == NON_SECURE) { 45 return &bl33_image_ep_info; 46 } 47 48 return &bl32_image_ep_info; 49 } 50 51 /* 52 * Set the build time defaults,if we can't find any config data. 53 */ 54 static inline void bl31_set_default_config(void) 55 { 56 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 57 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 58 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 59 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 60 DISABLE_ALL_EXCEPTIONS); 61 } 62 63 /* 64 * Perform any BL31 specific platform actions. Here is an opportunity to copy 65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 66 * are lost (potentially). This needs to be done before the MMU is initialized 67 * so that the memory layout can be used while creating page tables. 68 */ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 uint64_t tfa_handoff_addr; 73 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 74 enum pm_ret_status ret_status; 75 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; 76 77 /* 78 * Do initial security configuration to allow DRAM/device access. On 79 * Base VERSAL only DRAM security is programmable (via TrustZone), but 80 * other platforms might have more programmable security devices 81 * present. 82 */ 83 versal_config_setup(); 84 85 /* Initialize the platform config for future decision making */ 86 board_detection(); 87 88 switch (platform_id) { 89 case VERSAL_SPP: 90 cpu_clock = 2720000; 91 break; 92 case VERSAL_EMU: 93 cpu_clock = 212000; 94 break; 95 case VERSAL_QEMU: 96 case VERSAL_SILICON: 97 cpu_clock = 100000000; 98 break; 99 default: 100 panic(); 101 } 102 set_cnt_freq(); 103 104 generic_delay_timer_init(); 105 106 setup_console(); 107 108 NOTICE("TF-A running on %s %d\n", board_name_decode(), platform_version); 109 110 /* Populate common information for BL32 and BL33 */ 111 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 112 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 113 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 114 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 115 116 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 117 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 118 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 119 if (ret_status == PM_RET_SUCCESS) { 120 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 121 tfa_handoff_addr = (uintptr_t)&addr; 122 } else { 123 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n"); 124 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 125 } 126 127 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 128 &bl33_image_ep_info, 129 tfa_handoff_addr); 130 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) { 131 bl31_set_default_config(); 132 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) { 133 ERROR("BL31: Error too many partitions %u\n", ret); 134 } else if (ret != XBL_HANDOFF_SUCCESS) { 135 panic(); 136 } else { 137 INFO("BL31: PLM to TF-A handover success %u\n", ret); 138 } 139 140 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 141 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 142 } 143 144 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 145 146 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 147 { 148 static uint32_t index; 149 uint32_t i; 150 151 /* Validate 'handler' and 'id' parameters */ 152 if (handler == NULL || index >= MAX_INTR_EL3) { 153 return -EINVAL; 154 } 155 156 /* Check if a handler has already been registered */ 157 for (i = 0; i < index; i++) { 158 if (id == type_el3_interrupt_table[i].id) { 159 return -EALREADY; 160 } 161 } 162 163 type_el3_interrupt_table[index].id = id; 164 type_el3_interrupt_table[index].handler = handler; 165 166 index++; 167 168 return 0; 169 } 170 171 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 172 void *handle, void *cookie) 173 { 174 uint32_t intr_id; 175 uint32_t i; 176 interrupt_type_handler_t handler = NULL; 177 178 intr_id = plat_ic_get_pending_interrupt_id(); 179 180 for (i = 0; i < MAX_INTR_EL3; i++) { 181 if (intr_id == type_el3_interrupt_table[i].id) { 182 handler = type_el3_interrupt_table[i].handler; 183 } 184 } 185 186 if (handler != NULL) { 187 return handler(intr_id, flags, handle, cookie); 188 } 189 190 return 0; 191 } 192 193 void bl31_platform_setup(void) 194 { 195 prepare_dtb(); 196 197 /* Initialize the gic cpu and distributor interfaces */ 198 plat_versal_gic_driver_init(); 199 plat_versal_gic_init(); 200 } 201 202 void bl31_plat_runtime_setup(void) 203 { 204 uint64_t flags = 0; 205 int32_t rc; 206 207 set_interrupt_rm_flag(flags, NON_SECURE); 208 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 209 rdo_el3_interrupt_handler, flags); 210 if (rc != 0) { 211 panic(); 212 } 213 } 214 215 /* 216 * Perform the very early platform specific architectural setup here. 217 */ 218 void bl31_plat_arch_setup(void) 219 { 220 plat_arm_interconnect_init(); 221 plat_arm_interconnect_enter_coherency(); 222 223 const mmap_region_t bl_regions[] = { 224 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \ 225 (!defined(PLAT_XLAT_TABLES_DYNAMIC))) 226 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 227 MT_MEMORY | MT_RW | MT_NS), 228 #endif 229 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 230 MT_MEMORY | MT_RW | MT_SECURE), 231 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 232 MT_CODE | MT_SECURE), 233 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 234 MT_RO_DATA | MT_SECURE), 235 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 236 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 237 MT_DEVICE | MT_RW | MT_SECURE), 238 {0} 239 }; 240 241 setup_page_tables(bl_regions, plat_get_mmap()); 242 enable_mmu(0); 243 } 244