1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <platform_def.h> 8 #include <s32cc-clk-drv.h> 9 #include <s32cc-clk-ids.h> 10 #include <s32cc-clk-utils.h> 11 12 #define S32CC_FXOSC_FREQ (40U * MHZ) 13 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 14 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 15 #define S32CC_A53_FREQ (1U * GHZ) 16 #define S32CC_XBAR_2X_FREQ (800U * MHZ) 17 #define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ) 18 #define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ 19 20 static int setup_fxosc(void) 21 { 22 int ret; 23 24 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 25 if (ret != 0) { 26 return ret; 27 } 28 29 return ret; 30 } 31 32 static int setup_arm_pll(void) 33 { 34 int ret; 35 36 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 37 if (ret != 0) { 38 return ret; 39 } 40 41 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 42 if (ret != 0) { 43 return ret; 44 } 45 46 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 47 if (ret != 0) { 48 return ret; 49 } 50 51 return ret; 52 } 53 54 static int setup_periph_pll(void) 55 { 56 int ret; 57 58 ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC); 59 if (ret != 0) { 60 return ret; 61 } 62 63 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); 64 if (ret != 0) { 65 return ret; 66 } 67 68 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); 69 if (ret != 0) { 70 return ret; 71 } 72 73 return ret; 74 } 75 76 static int enable_a53_clk(void) 77 { 78 int ret; 79 80 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 81 if (ret != 0) { 82 return ret; 83 } 84 85 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 86 if (ret != 0) { 87 return ret; 88 } 89 90 ret = clk_enable(S32CC_CLK_A53_CORE); 91 if (ret != 0) { 92 return ret; 93 } 94 95 return ret; 96 } 97 98 static int enable_xbar_clk(void) 99 { 100 int ret; 101 102 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); 103 if (ret != 0) { 104 return ret; 105 } 106 107 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); 108 if (ret != 0) { 109 return ret; 110 } 111 112 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); 113 if (ret != 0) { 114 return ret; 115 } 116 117 ret = clk_enable(S32CC_CLK_XBAR_2X); 118 if (ret != 0) { 119 return ret; 120 } 121 122 return ret; 123 } 124 125 static int enable_uart_clk(void) 126 { 127 int ret; 128 129 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3); 130 if (ret != 0) { 131 return ret; 132 } 133 134 ret = clk_enable(S32CC_CLK_LINFLEX_BAUD); 135 if (ret != 0) { 136 return ret; 137 } 138 139 return ret; 140 } 141 142 int s32cc_init_early_clks(void) 143 { 144 int ret; 145 146 s32cc_clk_register_drv(); 147 148 ret = setup_fxosc(); 149 if (ret != 0) { 150 return ret; 151 } 152 153 ret = setup_arm_pll(); 154 if (ret != 0) { 155 return ret; 156 } 157 158 ret = enable_a53_clk(); 159 if (ret != 0) { 160 return ret; 161 } 162 163 ret = enable_xbar_clk(); 164 if (ret != 0) { 165 return ret; 166 } 167 168 ret = setup_periph_pll(); 169 if (ret != 0) { 170 return ret; 171 } 172 173 ret = enable_uart_clk(); 174 if (ret != 0) { 175 return ret; 176 } 177 178 return ret; 179 } 180