1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 11 #include <platform_def.h> 12 13 #define BKPR_BOOT_MODE 96U 14 15 #if defined(IMAGE_BL31) 16 /* BL31 only uses the first half of the SYSRAM */ 17 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 18 STM32MP_SYSRAM_SIZE / 2U, \ 19 MT_MEMORY | \ 20 MT_RW | \ 21 MT_SECURE | \ 22 MT_EXECUTE_NEVER) 23 #else 24 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 25 STM32MP_SYSRAM_SIZE, \ 26 MT_MEMORY | \ 27 MT_RW | \ 28 MT_SECURE | \ 29 MT_EXECUTE_NEVER) 30 #endif 31 32 #if STM32MP_DDR_FIP_IO_STORAGE 33 #define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \ 34 SRAM1_SIZE_FOR_TFA, \ 35 MT_MEMORY | \ 36 MT_RW | \ 37 MT_SECURE | \ 38 MT_EXECUTE_NEVER) 39 #endif 40 41 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 42 STM32MP_DEVICE_SIZE, \ 43 MT_DEVICE | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 #if defined(IMAGE_BL2) 49 static const mmap_region_t stm32mp2_mmap[] = { 50 MAP_SYSRAM, 51 #if STM32MP_DDR_FIP_IO_STORAGE 52 MAP_SRAM1, 53 #endif 54 MAP_DEVICE, 55 {0} 56 }; 57 #endif 58 #if defined(IMAGE_BL31) 59 static const mmap_region_t stm32mp2_mmap[] = { 60 MAP_SYSRAM, 61 MAP_DEVICE, 62 {0} 63 }; 64 #endif 65 66 void configure_mmu(void) 67 { 68 mmap_add(stm32mp2_mmap); 69 init_xlat_tables(); 70 71 enable_mmu_el3(0); 72 } 73 74 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 75 { 76 if (bank == GPIO_BANK_Z) { 77 return GPIOZ_BASE; 78 } 79 80 assert(bank <= GPIO_BANK_K); 81 82 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 83 } 84 85 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 86 { 87 if (bank == GPIO_BANK_Z) { 88 return 0; 89 } 90 91 assert(bank <= GPIO_BANK_K); 92 93 return bank * GPIO_BANK_OFFSET; 94 } 95 96 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 97 { 98 if (bank == GPIO_BANK_Z) { 99 return CK_BUS_GPIOZ; 100 } 101 102 assert(bank <= GPIO_BANK_K); 103 104 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 105 } 106 107 uint32_t stm32mp_get_chip_version(void) 108 { 109 static uint32_t rev; 110 111 if (rev != 0U) { 112 return rev; 113 } 114 115 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 116 panic(); 117 } 118 119 return rev; 120 } 121 122 uint32_t stm32mp_get_chip_dev_id(void) 123 { 124 return stm32mp_syscfg_get_chip_dev_id(); 125 } 126 127 static uint32_t get_part_number(void) 128 { 129 static uint32_t part_number; 130 131 if (part_number != 0U) { 132 return part_number; 133 } 134 135 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 136 panic(); 137 } 138 139 return part_number; 140 } 141 142 static uint32_t get_cpu_package(void) 143 { 144 static uint32_t package = UINT32_MAX; 145 146 if (package == UINT32_MAX) { 147 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 148 panic(); 149 } 150 } 151 152 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 153 } 154 155 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 156 { 157 char *cpu_s, *cpu_r, *pkg; 158 159 /* MPUs Part Numbers */ 160 switch (get_part_number()) { 161 case STM32MP251A_PART_NB: 162 cpu_s = "251A"; 163 break; 164 case STM32MP251C_PART_NB: 165 cpu_s = "251C"; 166 break; 167 case STM32MP251D_PART_NB: 168 cpu_s = "251D"; 169 break; 170 case STM32MP251F_PART_NB: 171 cpu_s = "251F"; 172 break; 173 case STM32MP253A_PART_NB: 174 cpu_s = "253A"; 175 break; 176 case STM32MP253C_PART_NB: 177 cpu_s = "253C"; 178 break; 179 case STM32MP253D_PART_NB: 180 cpu_s = "253D"; 181 break; 182 case STM32MP253F_PART_NB: 183 cpu_s = "253F"; 184 break; 185 case STM32MP255A_PART_NB: 186 cpu_s = "255A"; 187 break; 188 case STM32MP255C_PART_NB: 189 cpu_s = "255C"; 190 break; 191 case STM32MP255D_PART_NB: 192 cpu_s = "255D"; 193 break; 194 case STM32MP255F_PART_NB: 195 cpu_s = "255F"; 196 break; 197 case STM32MP257A_PART_NB: 198 cpu_s = "257A"; 199 break; 200 case STM32MP257C_PART_NB: 201 cpu_s = "257C"; 202 break; 203 case STM32MP257D_PART_NB: 204 cpu_s = "257D"; 205 break; 206 case STM32MP257F_PART_NB: 207 cpu_s = "257F"; 208 break; 209 default: 210 cpu_s = "????"; 211 break; 212 } 213 214 /* Package */ 215 switch (get_cpu_package()) { 216 case STM32MP25_PKG_CUSTOM: 217 pkg = "XX"; 218 break; 219 case STM32MP25_PKG_AL_VFBGA361: 220 pkg = "AL"; 221 break; 222 case STM32MP25_PKG_AK_VFBGA424: 223 pkg = "AK"; 224 break; 225 case STM32MP25_PKG_AI_TFBGA436: 226 pkg = "AI"; 227 break; 228 default: 229 pkg = "??"; 230 break; 231 } 232 233 /* REVISION */ 234 switch (stm32mp_get_chip_version()) { 235 case STM32MP2_REV_A: 236 cpu_r = "A"; 237 break; 238 case STM32MP2_REV_B: 239 cpu_r = "B"; 240 break; 241 case STM32MP2_REV_X: 242 cpu_r = "X"; 243 break; 244 case STM32MP2_REV_Y: 245 cpu_r = "Y"; 246 break; 247 case STM32MP2_REV_Z: 248 cpu_r = "Z"; 249 break; 250 default: 251 cpu_r = "?"; 252 break; 253 } 254 255 snprintf(name, STM32_SOC_NAME_SIZE, 256 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 257 } 258 259 void stm32mp_print_cpuinfo(void) 260 { 261 char name[STM32_SOC_NAME_SIZE]; 262 263 stm32mp_get_soc_name(name); 264 NOTICE("CPU: %s\n", name); 265 } 266 267 void stm32mp_print_boardinfo(void) 268 { 269 uint32_t board_id = 0U; 270 271 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 272 return; 273 } 274 275 if (board_id != 0U) { 276 stm32_display_board_info(board_id); 277 } 278 } 279 280 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 281 { 282 return tamp_bkpr(BKPR_BOOT_MODE); 283 } 284