1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/debug_v8p9.h> 28 #include <lib/extensions/fgt2.h> 29 #include <lib/extensions/mpam.h> 30 #include <lib/extensions/pmuv3.h> 31 #include <lib/extensions/sme.h> 32 #include <lib/extensions/spe.h> 33 #include <lib/extensions/sve.h> 34 #include <lib/extensions/sys_reg_trace.h> 35 #include <lib/extensions/trbe.h> 36 #include <lib/extensions/trf.h> 37 #include <lib/utils.h> 38 39 #if ENABLE_FEAT_TWED 40 /* Make sure delay value fits within the range(0-15) */ 41 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 42 #endif /* ENABLE_FEAT_TWED */ 43 44 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 45 static bool has_secure_perworld_init; 46 47 static void manage_extensions_common(cpu_context_t *ctx); 48 static void manage_extensions_nonsecure(cpu_context_t *ctx); 49 static void manage_extensions_secure(cpu_context_t *ctx); 50 static void manage_extensions_secure_per_world(void); 51 52 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 53 { 54 u_register_t sctlr_elx, actlr_elx; 55 56 /* 57 * Initialise SCTLR_EL1 to the reset value corresponding to the target 58 * execution state setting all fields rather than relying on the hw. 59 * Some fields have architecturally UNKNOWN reset values and these are 60 * set to zero. 61 * 62 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 63 * 64 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 65 * required by PSCI specification) 66 */ 67 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 68 if (GET_RW(ep->spsr) == MODE_RW_64) { 69 sctlr_elx |= SCTLR_EL1_RES1; 70 } else { 71 /* 72 * If the target execution state is AArch32 then the following 73 * fields need to be set. 74 * 75 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 79 * instructions are not trapped to EL1. 80 * 81 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 82 * CP15DMB, CP15DSB, and CP15ISB instructions. 83 */ 84 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 85 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 86 } 87 88 #if ERRATA_A75_764081 89 /* 90 * If workaround of errata 764081 for Cortex-A75 is used then set 91 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 92 */ 93 sctlr_elx |= SCTLR_IESB_BIT; 94 #endif 95 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 96 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 97 98 /* 99 * Base the context ACTLR_EL1 on the current value, as it is 100 * implementation defined. The context restore process will write 101 * the value from the context to the actual register and can cause 102 * problems for processor cores that don't expect certain bits to 103 * be zero. 104 */ 105 actlr_elx = read_actlr_el1(); 106 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 107 } 108 109 /****************************************************************************** 110 * This function performs initializations that are specific to SECURE state 111 * and updates the cpu context specified by 'ctx'. 112 *****************************************************************************/ 113 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 114 { 115 u_register_t scr_el3; 116 el3_state_t *state; 117 118 state = get_el3state_ctx(ctx); 119 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 120 121 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 122 /* 123 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 124 * indicated by the interrupt routing model for BL31. 125 */ 126 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 127 #endif 128 129 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 130 if (is_feat_mte2_supported()) { 131 scr_el3 |= SCR_ATA_BIT; 132 } 133 134 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 135 136 /* 137 * Initialize EL1 context registers unless SPMC is running 138 * at S-EL2. 139 */ 140 #if !SPMD_SPM_AT_SEL2 141 setup_el1_context(ctx, ep); 142 #endif 143 144 manage_extensions_secure(ctx); 145 146 /** 147 * manage_extensions_secure_per_world api has to be executed once, 148 * as the registers getting initialised, maintain constant value across 149 * all the cpus for the secure world. 150 * Henceforth, this check ensures that the registers are initialised once 151 * and avoids re-initialization from multiple cores. 152 */ 153 if (!has_secure_perworld_init) { 154 manage_extensions_secure_per_world(); 155 } 156 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 /* CSV2 version 2 and above */ 175 if (is_feat_csv2_2_supported()) { 176 /* Enable access to the SCXTNUM_ELx registers. */ 177 scr_el3 |= SCR_EnSCXT_BIT; 178 } 179 180 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 181 } 182 #endif /* ENABLE_RME */ 183 184 /****************************************************************************** 185 * This function performs initializations that are specific to NON-SECURE state 186 * and updates the cpu context specified by 'ctx'. 187 *****************************************************************************/ 188 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 189 { 190 u_register_t scr_el3; 191 el3_state_t *state; 192 193 state = get_el3state_ctx(ctx); 194 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 195 196 /* SCR_NS: Set the NS bit */ 197 scr_el3 |= SCR_NS_BIT; 198 199 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 200 if (is_feat_mte2_supported()) { 201 scr_el3 |= SCR_ATA_BIT; 202 } 203 204 #if !CTX_INCLUDE_PAUTH_REGS 205 /* 206 * Pointer Authentication feature, if present, is always enabled by default 207 * for Non secure lower exception levels. We do not have an explicit 208 * flag to set it. 209 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 210 * exception levels of secure and realm worlds. 211 * 212 * To prevent the leakage between the worlds during world switch, 213 * we enable it only for the non-secure world. 214 * 215 * If the Secure/realm world wants to use pointer authentication, 216 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 217 * it will be enabled globally for all the contexts. 218 * 219 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 220 * other than EL3 221 * 222 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 223 * than EL3 224 */ 225 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 226 227 #endif /* CTX_INCLUDE_PAUTH_REGS */ 228 229 #if HANDLE_EA_EL3_FIRST_NS 230 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 231 scr_el3 |= SCR_EA_BIT; 232 #endif 233 234 #if RAS_TRAP_NS_ERR_REC_ACCESS 235 /* 236 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 237 * and RAS ERX registers from EL1 and EL2(from any security state) 238 * are trapped to EL3. 239 * Set here to trap only for NS EL1/EL2 240 * 241 */ 242 scr_el3 |= SCR_TERR_BIT; 243 #endif 244 245 /* CSV2 version 2 and above */ 246 if (is_feat_csv2_2_supported()) { 247 /* Enable access to the SCXTNUM_ELx registers. */ 248 scr_el3 |= SCR_EnSCXT_BIT; 249 } 250 251 #ifdef IMAGE_BL31 252 /* 253 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 254 * indicated by the interrupt routing model for BL31. 255 */ 256 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 257 #endif 258 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 259 260 /* Initialize EL1 context registers */ 261 setup_el1_context(ctx, ep); 262 263 /* Initialize EL2 context registers */ 264 #if CTX_INCLUDE_EL2_REGS 265 266 /* 267 * Initialize SCTLR_EL2 context register with reset value. 268 */ 269 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 270 271 if (is_feat_hcx_supported()) { 272 /* 273 * Initialize register HCRX_EL2 with its init value. 274 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 275 * chance that this can lead to unexpected behavior in lower 276 * ELs that have not been updated since the introduction of 277 * this feature if not properly initialized, especially when 278 * it comes to those bits that enable/disable traps. 279 */ 280 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 281 HCRX_EL2_INIT_VAL); 282 } 283 284 if (is_feat_fgt_supported()) { 285 /* 286 * Initialize HFG*_EL2 registers with a default value so legacy 287 * systems unaware of FEAT_FGT do not get trapped due to their lack 288 * of initialization for this feature. 289 */ 290 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 291 HFGITR_EL2_INIT_VAL); 292 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 293 HFGRTR_EL2_INIT_VAL); 294 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 295 HFGWTR_EL2_INIT_VAL); 296 } 297 298 #endif /* CTX_INCLUDE_EL2_REGS */ 299 300 manage_extensions_nonsecure(ctx); 301 } 302 303 /******************************************************************************* 304 * The following function performs initialization of the cpu_context 'ctx' 305 * for first use that is common to all security states, and sets the 306 * initial entrypoint state as specified by the entry_point_info structure. 307 * 308 * The EE and ST attributes are used to configure the endianness and secure 309 * timer availability for the new execution context. 310 ******************************************************************************/ 311 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 312 { 313 u_register_t scr_el3; 314 u_register_t mdcr_el3; 315 el3_state_t *state; 316 gp_regs_t *gp_regs; 317 318 state = get_el3state_ctx(ctx); 319 320 /* Clear any residual register values from the context */ 321 zeromem(ctx, sizeof(*ctx)); 322 323 /* 324 * The lower-EL context is zeroed so that no stale values leak to a world. 325 * It is assumed that an all-zero lower-EL context is good enough for it 326 * to boot correctly. However, there are very few registers where this 327 * is not true and some values need to be recreated. 328 */ 329 #if CTX_INCLUDE_EL2_REGS 330 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 331 332 /* 333 * These bits are set in the gicv3 driver. Losing them (especially the 334 * SRE bit) is problematic for all worlds. Henceforth recreate them. 335 */ 336 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 337 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 338 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 339 #endif /* CTX_INCLUDE_EL2_REGS */ 340 341 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 342 scr_el3 = SCR_RESET_VAL; 343 344 /* 345 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 346 * EL2, EL1 and EL0 are not trapped to EL3. 347 * 348 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 349 * EL2, EL1 and EL0 are not trapped to EL3. 350 * 351 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 352 * both Security states and both Execution states. 353 * 354 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 355 * Non-secure memory. 356 */ 357 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 358 359 scr_el3 |= SCR_SIF_BIT; 360 361 /* 362 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 363 * Exception level as specified by SPSR. 364 */ 365 if (GET_RW(ep->spsr) == MODE_RW_64) { 366 scr_el3 |= SCR_RW_BIT; 367 } 368 369 /* 370 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 371 * Secure timer registers to EL3, from AArch64 state only, if specified 372 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 373 * bit always behaves as 1 (i.e. secure physical timer register access 374 * is not trapped) 375 */ 376 if (EP_GET_ST(ep->h.attr) != 0U) { 377 scr_el3 |= SCR_ST_BIT; 378 } 379 380 /* 381 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 382 * SCR_EL3.HXEn. 383 */ 384 if (is_feat_hcx_supported()) { 385 scr_el3 |= SCR_HXEn_BIT; 386 } 387 388 /* 389 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 390 * registers are trapped to EL3. 391 */ 392 #if ENABLE_FEAT_RNG_TRAP 393 scr_el3 |= SCR_TRNDR_BIT; 394 #endif 395 396 #if FAULT_INJECTION_SUPPORT 397 /* Enable fault injection from lower ELs */ 398 scr_el3 |= SCR_FIEN_BIT; 399 #endif 400 401 #if CTX_INCLUDE_PAUTH_REGS 402 /* 403 * Enable Pointer Authentication globally for all the worlds. 404 * 405 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 406 * other than EL3 407 * 408 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 409 * than EL3 410 */ 411 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 412 #endif /* CTX_INCLUDE_PAUTH_REGS */ 413 414 /* 415 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 416 */ 417 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 418 scr_el3 |= SCR_TCR2EN_BIT; 419 } 420 421 /* 422 * SCR_EL3.PIEN: Enable permission indirection and overlay 423 * registers for AArch64 if present. 424 */ 425 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 426 scr_el3 |= SCR_PIEN_BIT; 427 } 428 429 /* 430 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 431 */ 432 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 433 scr_el3 |= SCR_GCSEn_BIT; 434 } 435 436 /* 437 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 438 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 439 * next mode is Hyp. 440 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 441 * same conditions as HVC instructions and when the processor supports 442 * ARMv8.6-FGT. 443 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 444 * CNTPOFF_EL2 register under the same conditions as HVC instructions 445 * and when the processor supports ECV. 446 */ 447 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 448 || ((GET_RW(ep->spsr) != MODE_RW_64) 449 && (GET_M32(ep->spsr) == MODE32_hyp))) { 450 scr_el3 |= SCR_HCE_BIT; 451 452 if (is_feat_fgt_supported()) { 453 scr_el3 |= SCR_FGTEN_BIT; 454 } 455 456 if (is_feat_ecv_supported()) { 457 scr_el3 |= SCR_ECVEN_BIT; 458 } 459 } 460 461 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 462 if (is_feat_twed_supported()) { 463 /* Set delay in SCR_EL3 */ 464 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 465 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 466 << SCR_TWEDEL_SHIFT); 467 468 /* Enable WFE delay */ 469 scr_el3 |= SCR_TWEDEn_BIT; 470 } 471 472 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 473 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 474 if (is_feat_sel2_supported()) { 475 scr_el3 |= SCR_EEL2_BIT; 476 } 477 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 478 479 /* 480 * Populate EL3 state so that we've the right context 481 * before doing ERET 482 */ 483 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 484 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 485 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 486 487 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 488 mdcr_el3 = MDCR_EL3_RESET_VAL; 489 490 /* --------------------------------------------------------------------- 491 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 492 * Some fields are architecturally UNKNOWN on reset. 493 * 494 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 495 * Debug exceptions, other than Breakpoint Instruction exceptions, are 496 * disabled from all ELs in Secure state. 497 * 498 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 499 * privileged debug from S-EL1. 500 * 501 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 502 * access to the powerdown debug registers do not trap to EL3. 503 * 504 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 505 * debug registers, other than those registers that are controlled by 506 * MDCR_EL3.TDOSA. 507 */ 508 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 509 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 510 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 511 512 /* 513 * Configure MDCR_EL3 register as applicable for each world 514 * (NS/Secure/Realm) context. 515 */ 516 manage_extensions_common(ctx); 517 518 /* 519 * Store the X0-X7 value from the entrypoint into the context 520 * Use memcpy as we are in control of the layout of the structures 521 */ 522 gp_regs = get_gpregs_ctx(ctx); 523 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 524 } 525 526 /******************************************************************************* 527 * Context management library initialization routine. This library is used by 528 * runtime services to share pointers to 'cpu_context' structures for secure 529 * non-secure and realm states. Management of the structures and their associated 530 * memory is not done by the context management library e.g. the PSCI service 531 * manages the cpu context used for entry from and exit to the non-secure state. 532 * The Secure payload dispatcher service manages the context(s) corresponding to 533 * the secure state. It also uses this library to get access to the non-secure 534 * state cpu context pointers. 535 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 536 * which will be used for programming an entry into a lower EL. The same context 537 * will be used to save state upon exception entry from that EL. 538 ******************************************************************************/ 539 void __init cm_init(void) 540 { 541 /* 542 * The context management library has only global data to initialize, but 543 * that will be done when the BSS is zeroed out. 544 */ 545 } 546 547 /******************************************************************************* 548 * This is the high-level function used to initialize the cpu_context 'ctx' for 549 * first use. It performs initializations that are common to all security states 550 * and initializations specific to the security state specified in 'ep' 551 ******************************************************************************/ 552 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 553 { 554 unsigned int security_state; 555 556 assert(ctx != NULL); 557 558 /* 559 * Perform initializations that are common 560 * to all security states 561 */ 562 setup_context_common(ctx, ep); 563 564 security_state = GET_SECURITY_STATE(ep->h.attr); 565 566 /* Perform security state specific initializations */ 567 switch (security_state) { 568 case SECURE: 569 setup_secure_context(ctx, ep); 570 break; 571 #if ENABLE_RME 572 case REALM: 573 setup_realm_context(ctx, ep); 574 break; 575 #endif 576 case NON_SECURE: 577 setup_ns_context(ctx, ep); 578 break; 579 default: 580 ERROR("Invalid security state\n"); 581 panic(); 582 break; 583 } 584 } 585 586 /******************************************************************************* 587 * Enable architecture extensions for EL3 execution. This function only updates 588 * registers in-place which are expected to either never change or be 589 * overwritten by el3_exit. 590 ******************************************************************************/ 591 #if IMAGE_BL31 592 void cm_manage_extensions_el3(void) 593 { 594 if (is_feat_amu_supported()) { 595 amu_init_el3(); 596 } 597 598 if (is_feat_sme_supported()) { 599 sme_init_el3(); 600 } 601 602 pmuv3_init_el3(); 603 } 604 #endif /* IMAGE_BL31 */ 605 606 /****************************************************************************** 607 * Function to initialise the registers with the RESET values in the context 608 * memory, which are maintained per world. 609 ******************************************************************************/ 610 #if IMAGE_BL31 611 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 612 { 613 /* 614 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 615 * 616 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 617 * by Advanced SIMD, floating-point or SVE instructions (if 618 * implemented) do not trap to EL3. 619 * 620 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 621 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 622 */ 623 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 624 625 per_world_ctx->ctx_cptr_el3 = cptr_el3; 626 627 /* 628 * Initialize MPAM3_EL3 to its default reset value 629 * 630 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 631 * all lower ELn MPAM3_EL3 register access to, trap to EL3 632 */ 633 634 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 635 } 636 #endif /* IMAGE_BL31 */ 637 638 /******************************************************************************* 639 * Initialise per_world_context for Non-Secure world. 640 * This function enables the architecture extensions, which have same value 641 * across the cores for the non-secure world. 642 ******************************************************************************/ 643 #if IMAGE_BL31 644 void manage_extensions_nonsecure_per_world(void) 645 { 646 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 647 648 if (is_feat_sme_supported()) { 649 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 650 } 651 652 if (is_feat_sve_supported()) { 653 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 654 } 655 656 if (is_feat_amu_supported()) { 657 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 658 } 659 660 if (is_feat_sys_reg_trace_supported()) { 661 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 662 } 663 664 if (is_feat_mpam_supported()) { 665 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 666 } 667 } 668 #endif /* IMAGE_BL31 */ 669 670 /******************************************************************************* 671 * Initialise per_world_context for Secure world. 672 * This function enables the architecture extensions, which have same value 673 * across the cores for the secure world. 674 ******************************************************************************/ 675 static void manage_extensions_secure_per_world(void) 676 { 677 #if IMAGE_BL31 678 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 679 680 if (is_feat_sme_supported()) { 681 682 if (ENABLE_SME_FOR_SWD) { 683 /* 684 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 685 * SME, SVE, and FPU/SIMD context properly managed. 686 */ 687 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 688 } else { 689 /* 690 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 691 * world can safely use the associated registers. 692 */ 693 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 694 } 695 } 696 if (is_feat_sve_supported()) { 697 if (ENABLE_SVE_FOR_SWD) { 698 /* 699 * Enable SVE and FPU in secure context, SPM must ensure 700 * that the SVE and FPU register contexts are properly managed. 701 */ 702 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 703 } else { 704 /* 705 * Disable SVE and FPU in secure context so non-secure world 706 * can safely use them. 707 */ 708 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 709 } 710 } 711 712 /* NS can access this but Secure shouldn't */ 713 if (is_feat_sys_reg_trace_supported()) { 714 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 715 } 716 717 has_secure_perworld_init = true; 718 #endif /* IMAGE_BL31 */ 719 } 720 721 /******************************************************************************* 722 * Enable architecture extensions on first entry to Non-secure world only 723 * and disable for secure world. 724 * 725 * NOTE: Arch features which have been provided with the capability of getting 726 * enabled only for non-secure world and being disabled for secure world are 727 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 728 ******************************************************************************/ 729 static void manage_extensions_common(cpu_context_t *ctx) 730 { 731 #if IMAGE_BL31 732 if (is_feat_spe_supported()) { 733 /* 734 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 735 */ 736 spe_enable(ctx); 737 } 738 739 if (is_feat_trbe_supported()) { 740 /* 741 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 742 * Realm state. 743 */ 744 trbe_enable(ctx); 745 } 746 747 if (is_feat_trf_supported()) { 748 /* 749 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 750 */ 751 trf_enable(ctx); 752 } 753 754 if (is_feat_brbe_supported()) { 755 /* 756 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 757 */ 758 brbe_enable(ctx); 759 } 760 #endif /* IMAGE_BL31 */ 761 } 762 763 /******************************************************************************* 764 * Enable architecture extensions on first entry to Non-secure world. 765 ******************************************************************************/ 766 static void manage_extensions_nonsecure(cpu_context_t *ctx) 767 { 768 #if IMAGE_BL31 769 if (is_feat_amu_supported()) { 770 amu_enable(ctx); 771 } 772 773 if (is_feat_sme_supported()) { 774 sme_enable(ctx); 775 } 776 777 if (is_feat_fgt2_supported()) { 778 fgt2_enable(ctx); 779 } 780 781 if (is_feat_debugv8p9_supported()) { 782 debugv8p9_extended_bp_wp_enable(ctx); 783 } 784 785 pmuv3_enable(ctx); 786 #endif /* IMAGE_BL31 */ 787 } 788 789 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 790 static __unused void enable_pauth_el2(void) 791 { 792 u_register_t hcr_el2 = read_hcr_el2(); 793 /* 794 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 795 * accessing key registers or using pointer authentication instructions 796 * from lower ELs. 797 */ 798 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 799 800 write_hcr_el2(hcr_el2); 801 } 802 803 #if INIT_UNUSED_NS_EL2 804 /******************************************************************************* 805 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 806 * world when EL2 is empty and unused. 807 ******************************************************************************/ 808 static void manage_extensions_nonsecure_el2_unused(void) 809 { 810 #if IMAGE_BL31 811 if (is_feat_spe_supported()) { 812 spe_init_el2_unused(); 813 } 814 815 if (is_feat_amu_supported()) { 816 amu_init_el2_unused(); 817 } 818 819 if (is_feat_mpam_supported()) { 820 mpam_init_el2_unused(); 821 } 822 823 if (is_feat_trbe_supported()) { 824 trbe_init_el2_unused(); 825 } 826 827 if (is_feat_sys_reg_trace_supported()) { 828 sys_reg_trace_init_el2_unused(); 829 } 830 831 if (is_feat_trf_supported()) { 832 trf_init_el2_unused(); 833 } 834 835 pmuv3_init_el2_unused(); 836 837 if (is_feat_sve_supported()) { 838 sve_init_el2_unused(); 839 } 840 841 if (is_feat_sme_supported()) { 842 sme_init_el2_unused(); 843 } 844 845 #if ENABLE_PAUTH 846 enable_pauth_el2(); 847 #endif /* ENABLE_PAUTH */ 848 #endif /* IMAGE_BL31 */ 849 } 850 #endif /* INIT_UNUSED_NS_EL2 */ 851 852 /******************************************************************************* 853 * Enable architecture extensions on first entry to Secure world. 854 ******************************************************************************/ 855 static void manage_extensions_secure(cpu_context_t *ctx) 856 { 857 #if IMAGE_BL31 858 if (is_feat_sme_supported()) { 859 if (ENABLE_SME_FOR_SWD) { 860 /* 861 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 862 * must ensure SME, SVE, and FPU/SIMD context properly managed. 863 */ 864 sme_init_el3(); 865 sme_enable(ctx); 866 } else { 867 /* 868 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 869 * world can safely use the associated registers. 870 */ 871 sme_disable(ctx); 872 } 873 } 874 #endif /* IMAGE_BL31 */ 875 } 876 877 #if !IMAGE_BL1 878 /******************************************************************************* 879 * The following function initializes the cpu_context for a CPU specified by 880 * its `cpu_idx` for first use, and sets the initial entrypoint state as 881 * specified by the entry_point_info structure. 882 ******************************************************************************/ 883 void cm_init_context_by_index(unsigned int cpu_idx, 884 const entry_point_info_t *ep) 885 { 886 cpu_context_t *ctx; 887 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 888 cm_setup_context(ctx, ep); 889 } 890 #endif /* !IMAGE_BL1 */ 891 892 /******************************************************************************* 893 * The following function initializes the cpu_context for the current CPU 894 * for first use, and sets the initial entrypoint state as specified by the 895 * entry_point_info structure. 896 ******************************************************************************/ 897 void cm_init_my_context(const entry_point_info_t *ep) 898 { 899 cpu_context_t *ctx; 900 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 901 cm_setup_context(ctx, ep); 902 } 903 904 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 905 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 906 { 907 #if INIT_UNUSED_NS_EL2 908 u_register_t hcr_el2 = HCR_RESET_VAL; 909 u_register_t mdcr_el2; 910 u_register_t scr_el3; 911 912 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 913 914 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 915 if ((scr_el3 & SCR_RW_BIT) != 0U) { 916 hcr_el2 |= HCR_RW_BIT; 917 } 918 919 write_hcr_el2(hcr_el2); 920 921 /* 922 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 923 * All fields have architecturally UNKNOWN reset values. 924 */ 925 write_cptr_el2(CPTR_EL2_RESET_VAL); 926 927 /* 928 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 929 * reset and are set to zero except for field(s) listed below. 930 * 931 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 932 * Non-secure EL0 and EL1 accesses to the physical timer registers. 933 * 934 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 935 * Non-secure EL0 and EL1 accesses to the physical counter registers. 936 */ 937 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 938 939 /* 940 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 941 * UNKNOWN value. 942 */ 943 write_cntvoff_el2(0); 944 945 /* 946 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 947 * respectively. 948 */ 949 write_vpidr_el2(read_midr_el1()); 950 write_vmpidr_el2(read_mpidr_el1()); 951 952 /* 953 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 954 * 955 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 956 * translation is disabled, cache maintenance operations depend on the 957 * VMID. 958 * 959 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 960 * disabled. 961 */ 962 write_vttbr_el2(VTTBR_RESET_VAL & 963 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 964 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 965 966 /* 967 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 968 * Some fields are architecturally UNKNOWN on reset. 969 * 970 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 971 * register accesses to the Debug ROM registers are not trapped to EL2. 972 * 973 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 974 * accesses to the powerdown debug registers are not trapped to EL2. 975 * 976 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 977 * debug registers do not trap to EL2. 978 * 979 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 980 * EL2. 981 */ 982 mdcr_el2 = MDCR_EL2_RESET_VAL & 983 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 984 MDCR_EL2_TDE_BIT); 985 986 write_mdcr_el2(mdcr_el2); 987 988 /* 989 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 990 * 991 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 992 * EL1 accesses to System registers do not trap to EL2. 993 */ 994 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 995 996 /* 997 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 998 * reset. 999 * 1000 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1001 * and prevent timer interrupts. 1002 */ 1003 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1004 1005 manage_extensions_nonsecure_el2_unused(); 1006 #endif /* INIT_UNUSED_NS_EL2 */ 1007 } 1008 1009 /******************************************************************************* 1010 * Prepare the CPU system registers for first entry into realm, secure, or 1011 * normal world. 1012 * 1013 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1014 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1015 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1016 * For all entries, the EL1 registers are initialized from the cpu_context 1017 ******************************************************************************/ 1018 void cm_prepare_el3_exit(uint32_t security_state) 1019 { 1020 u_register_t sctlr_el2, scr_el3; 1021 cpu_context_t *ctx = cm_get_context(security_state); 1022 1023 assert(ctx != NULL); 1024 1025 if (security_state == NON_SECURE) { 1026 uint64_t el2_implemented = el_implemented(2); 1027 1028 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1029 CTX_SCR_EL3); 1030 1031 if (el2_implemented != EL_IMPL_NONE) { 1032 1033 /* 1034 * If context is not being used for EL2, initialize 1035 * HCRX_EL2 with its init value here. 1036 */ 1037 if (is_feat_hcx_supported()) { 1038 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1039 } 1040 1041 /* 1042 * Initialize Fine-grained trap registers introduced 1043 * by FEAT_FGT so all traps are initially disabled when 1044 * switching to EL2 or a lower EL, preventing undesired 1045 * behavior. 1046 */ 1047 if (is_feat_fgt_supported()) { 1048 /* 1049 * Initialize HFG*_EL2 registers with a default 1050 * value so legacy systems unaware of FEAT_FGT 1051 * do not get trapped due to their lack of 1052 * initialization for this feature. 1053 */ 1054 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1055 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1056 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1057 } 1058 1059 /* Condition to ensure EL2 is being used. */ 1060 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1061 /* Initialize SCTLR_EL2 register with reset value. */ 1062 sctlr_el2 = SCTLR_EL2_RES1; 1063 #if ERRATA_A75_764081 1064 /* 1065 * If workaround of errata 764081 for Cortex-A75 1066 * is used then set SCTLR_EL2.IESB to enable 1067 * Implicit Error Synchronization Barrier. 1068 */ 1069 sctlr_el2 |= SCTLR_IESB_BIT; 1070 #endif 1071 write_sctlr_el2(sctlr_el2); 1072 } else { 1073 /* 1074 * (scr_el3 & SCR_HCE_BIT==0) 1075 * EL2 implemented but unused. 1076 */ 1077 init_nonsecure_el2_unused(ctx); 1078 } 1079 } 1080 } 1081 cm_el1_sysregs_context_restore(security_state); 1082 cm_set_next_eret_context(security_state); 1083 } 1084 1085 #if CTX_INCLUDE_EL2_REGS 1086 1087 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1088 { 1089 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1090 if (is_feat_amu_supported()) { 1091 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1092 } 1093 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1094 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1095 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1096 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1097 } 1098 1099 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1100 { 1101 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1102 if (is_feat_amu_supported()) { 1103 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1104 } 1105 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1106 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1107 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1108 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1109 } 1110 1111 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1112 { 1113 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1114 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1115 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1116 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1117 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1118 } 1119 1120 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1121 { 1122 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1123 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1124 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1125 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1126 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1127 } 1128 1129 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1130 { 1131 u_register_t mpam_idr = read_mpamidr_el1(); 1132 1133 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1134 1135 /* 1136 * The context registers that we intend to save would be part of the 1137 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1138 */ 1139 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1140 return; 1141 } 1142 1143 /* 1144 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1145 * MPAMIDR_HAS_HCR_BIT == 1. 1146 */ 1147 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1148 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1149 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1150 1151 /* 1152 * The number of MPAMVPM registers is implementation defined, their 1153 * number is stored in the MPAMIDR_EL1 register. 1154 */ 1155 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1156 case 7: 1157 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1158 __fallthrough; 1159 case 6: 1160 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1161 __fallthrough; 1162 case 5: 1163 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1164 __fallthrough; 1165 case 4: 1166 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1167 __fallthrough; 1168 case 3: 1169 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1170 __fallthrough; 1171 case 2: 1172 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1173 __fallthrough; 1174 case 1: 1175 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1176 break; 1177 } 1178 } 1179 1180 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1181 { 1182 u_register_t mpam_idr = read_mpamidr_el1(); 1183 1184 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1185 1186 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1187 return; 1188 } 1189 1190 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1191 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1192 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1193 1194 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1195 case 7: 1196 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1197 __fallthrough; 1198 case 6: 1199 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1200 __fallthrough; 1201 case 5: 1202 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1203 __fallthrough; 1204 case 4: 1205 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1206 __fallthrough; 1207 case 3: 1208 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1209 __fallthrough; 1210 case 2: 1211 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1212 __fallthrough; 1213 case 1: 1214 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1215 break; 1216 } 1217 } 1218 1219 /* --------------------------------------------------------------------------- 1220 * The following registers are not added: 1221 * ICH_AP0R<n>_EL2 1222 * ICH_AP1R<n>_EL2 1223 * ICH_LR<n>_EL2 1224 * 1225 * NOTE: For a system with S-EL2 present but not enabled, accessing 1226 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1227 * SCR_EL3.NS = 1 before accessing this register. 1228 * --------------------------------------------------------------------------- 1229 */ 1230 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1231 { 1232 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1233 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1234 #else 1235 u_register_t scr_el3 = read_scr_el3(); 1236 write_scr_el3(scr_el3 | SCR_NS_BIT); 1237 isb(); 1238 1239 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1240 1241 write_scr_el3(scr_el3); 1242 isb(); 1243 #endif 1244 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1245 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1246 } 1247 1248 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1249 { 1250 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1251 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1252 #else 1253 u_register_t scr_el3 = read_scr_el3(); 1254 write_scr_el3(scr_el3 | SCR_NS_BIT); 1255 isb(); 1256 1257 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1258 1259 write_scr_el3(scr_el3); 1260 isb(); 1261 #endif 1262 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1263 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1264 } 1265 1266 /* ----------------------------------------------------- 1267 * The following registers are not added: 1268 * AMEVCNTVOFF0<n>_EL2 1269 * AMEVCNTVOFF1<n>_EL2 1270 * ----------------------------------------------------- 1271 */ 1272 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1273 { 1274 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1275 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1276 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1277 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1278 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1279 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1280 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1281 if (CTX_INCLUDE_AARCH32_REGS) { 1282 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1283 } 1284 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1285 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1286 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1287 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1288 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1289 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1290 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1291 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1292 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1293 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1294 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1295 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1296 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1297 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1298 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1299 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1300 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1301 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1302 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1303 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1304 } 1305 1306 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1307 { 1308 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1309 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1310 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1311 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1312 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1313 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1314 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1315 if (CTX_INCLUDE_AARCH32_REGS) { 1316 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1317 } 1318 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1319 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1320 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1321 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1322 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1323 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1324 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1325 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1326 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1327 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1328 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1329 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1330 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1331 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1332 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1333 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1334 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1335 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1336 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1337 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1338 } 1339 1340 /******************************************************************************* 1341 * Save EL2 sysreg context 1342 ******************************************************************************/ 1343 void cm_el2_sysregs_context_save(uint32_t security_state) 1344 { 1345 cpu_context_t *ctx; 1346 el2_sysregs_t *el2_sysregs_ctx; 1347 1348 ctx = cm_get_context(security_state); 1349 assert(ctx != NULL); 1350 1351 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1352 1353 el2_sysregs_context_save_common(el2_sysregs_ctx); 1354 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1355 1356 if (is_feat_mte2_supported()) { 1357 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1358 } 1359 1360 if (is_feat_mpam_supported()) { 1361 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1362 } 1363 1364 if (is_feat_fgt_supported()) { 1365 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1366 } 1367 1368 if (is_feat_fgt2_supported()) { 1369 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1370 } 1371 1372 if (is_feat_ecv_v2_supported()) { 1373 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1374 } 1375 1376 if (is_feat_vhe_supported()) { 1377 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1378 read_contextidr_el2()); 1379 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1380 } 1381 1382 if (is_feat_ras_supported()) { 1383 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1384 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1385 } 1386 1387 if (is_feat_nv2_supported()) { 1388 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1389 } 1390 1391 if (is_feat_trf_supported()) { 1392 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1393 } 1394 1395 if (is_feat_csv2_2_supported()) { 1396 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1397 read_scxtnum_el2()); 1398 } 1399 1400 if (is_feat_hcx_supported()) { 1401 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1402 } 1403 1404 if (is_feat_tcr2_supported()) { 1405 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1406 } 1407 1408 if (is_feat_sxpie_supported()) { 1409 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1410 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1411 } 1412 1413 if (is_feat_sxpoe_supported()) { 1414 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1415 } 1416 1417 if (is_feat_s2pie_supported()) { 1418 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1419 } 1420 1421 if (is_feat_gcs_supported()) { 1422 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1423 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1424 } 1425 } 1426 1427 /******************************************************************************* 1428 * Restore EL2 sysreg context 1429 ******************************************************************************/ 1430 void cm_el2_sysregs_context_restore(uint32_t security_state) 1431 { 1432 cpu_context_t *ctx; 1433 el2_sysregs_t *el2_sysregs_ctx; 1434 1435 ctx = cm_get_context(security_state); 1436 assert(ctx != NULL); 1437 1438 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1439 1440 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1441 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1442 1443 if (is_feat_mte2_supported()) { 1444 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1445 } 1446 1447 if (is_feat_mpam_supported()) { 1448 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1449 } 1450 1451 if (is_feat_fgt_supported()) { 1452 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1453 } 1454 1455 if (is_feat_fgt2_supported()) { 1456 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1457 } 1458 1459 if (is_feat_ecv_v2_supported()) { 1460 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1461 } 1462 1463 if (is_feat_vhe_supported()) { 1464 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1465 contextidr_el2)); 1466 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1467 } 1468 1469 if (is_feat_ras_supported()) { 1470 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1471 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1472 } 1473 1474 if (is_feat_nv2_supported()) { 1475 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1476 } 1477 1478 if (is_feat_trf_supported()) { 1479 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1480 } 1481 1482 if (is_feat_csv2_2_supported()) { 1483 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1484 scxtnum_el2)); 1485 } 1486 1487 if (is_feat_hcx_supported()) { 1488 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1489 } 1490 1491 if (is_feat_tcr2_supported()) { 1492 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1493 } 1494 1495 if (is_feat_sxpie_supported()) { 1496 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1497 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1498 } 1499 1500 if (is_feat_sxpoe_supported()) { 1501 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1502 } 1503 1504 if (is_feat_s2pie_supported()) { 1505 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1506 } 1507 1508 if (is_feat_gcs_supported()) { 1509 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1510 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1511 } 1512 } 1513 #endif /* CTX_INCLUDE_EL2_REGS */ 1514 1515 /******************************************************************************* 1516 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1517 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1518 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1519 * cm_prepare_el3_exit function. 1520 ******************************************************************************/ 1521 void cm_prepare_el3_exit_ns(void) 1522 { 1523 #if CTX_INCLUDE_EL2_REGS 1524 #if ENABLE_ASSERTIONS 1525 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1526 assert(ctx != NULL); 1527 1528 /* Assert that EL2 is used. */ 1529 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1530 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1531 (el_implemented(2U) != EL_IMPL_NONE)); 1532 #endif /* ENABLE_ASSERTIONS */ 1533 1534 /* Restore EL2 and EL1 sysreg contexts */ 1535 cm_el2_sysregs_context_restore(NON_SECURE); 1536 cm_el1_sysregs_context_restore(NON_SECURE); 1537 cm_set_next_eret_context(NON_SECURE); 1538 #else 1539 cm_prepare_el3_exit(NON_SECURE); 1540 #endif /* CTX_INCLUDE_EL2_REGS */ 1541 } 1542 1543 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1544 { 1545 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1546 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1547 1548 #if !ERRATA_SPECULATIVE_AT 1549 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1550 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1551 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1552 1553 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1554 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1555 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1556 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1557 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1558 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1559 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1560 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1561 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1562 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1563 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1564 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1565 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1566 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1567 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1568 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1569 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1570 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1571 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1572 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1573 1574 #if CTX_INCLUDE_AARCH32_REGS 1575 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1576 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1577 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1578 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1579 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1580 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1581 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1582 1583 #if NS_TIMER_SWITCH 1584 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1585 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1586 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1587 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1588 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1589 #endif /* NS_TIMER_SWITCH */ 1590 1591 #if ENABLE_FEAT_MTE2 1592 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1593 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1594 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1595 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1596 #endif /* ENABLE_FEAT_MTE2 */ 1597 1598 #if ENABLE_FEAT_RAS 1599 if (is_feat_ras_supported()) { 1600 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1601 } 1602 #endif 1603 1604 #if ENABLE_FEAT_S1PIE 1605 if (is_feat_s1pie_supported()) { 1606 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1607 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1608 } 1609 #endif 1610 1611 #if ENABLE_FEAT_S1POE 1612 if (is_feat_s1poe_supported()) { 1613 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1614 } 1615 #endif 1616 1617 #if ENABLE_FEAT_S2POE 1618 if (is_feat_s2poe_supported()) { 1619 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1620 } 1621 #endif 1622 1623 #if ENABLE_FEAT_TCR2 1624 if (is_feat_tcr2_supported()) { 1625 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1626 } 1627 #endif 1628 1629 #if ENABLE_TRF_FOR_NS 1630 if (is_feat_trf_supported()) { 1631 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1632 } 1633 #endif 1634 1635 #if ENABLE_FEAT_CSV2_2 1636 if (is_feat_csv2_2_supported()) { 1637 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1638 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1639 } 1640 #endif 1641 1642 #if ENABLE_FEAT_GCS 1643 if (is_feat_gcs_supported()) { 1644 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1645 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1646 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1647 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1648 } 1649 #endif 1650 } 1651 1652 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1653 { 1654 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1655 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1656 1657 #if !ERRATA_SPECULATIVE_AT 1658 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1659 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1660 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1661 1662 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1663 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1664 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1665 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1666 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1667 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1668 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1669 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1670 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1671 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1672 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1673 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1674 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1675 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1676 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1677 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1678 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1679 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1680 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1681 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1682 1683 #if CTX_INCLUDE_AARCH32_REGS 1684 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1685 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1686 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1687 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1688 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1689 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1690 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1691 1692 #if NS_TIMER_SWITCH 1693 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1694 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1695 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1696 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1697 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1698 #endif /* NS_TIMER_SWITCH */ 1699 1700 #if ENABLE_FEAT_MTE2 1701 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1702 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1703 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1704 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1705 #endif /* ENABLE_FEAT_MTE2 */ 1706 1707 #if ENABLE_FEAT_RAS 1708 if (is_feat_ras_supported()) { 1709 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1710 } 1711 #endif 1712 1713 #if ENABLE_FEAT_S1PIE 1714 if (is_feat_s1pie_supported()) { 1715 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1716 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1717 } 1718 #endif 1719 1720 #if ENABLE_FEAT_S1POE 1721 if (is_feat_s1poe_supported()) { 1722 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1723 } 1724 #endif 1725 1726 #if ENABLE_FEAT_S2POE 1727 if (is_feat_s2poe_supported()) { 1728 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1729 } 1730 #endif 1731 1732 #if ENABLE_FEAT_TCR2 1733 if (is_feat_tcr2_supported()) { 1734 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1735 } 1736 #endif 1737 1738 #if ENABLE_TRF_FOR_NS 1739 if (is_feat_trf_supported()) { 1740 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1741 } 1742 #endif 1743 1744 #if ENABLE_FEAT_CSV2_2 1745 if (is_feat_csv2_2_supported()) { 1746 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1747 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1748 } 1749 #endif 1750 1751 #if ENABLE_FEAT_GCS 1752 if (is_feat_gcs_supported()) { 1753 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1754 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1755 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1756 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1757 } 1758 #endif 1759 } 1760 1761 /******************************************************************************* 1762 * The next four functions are used by runtime services to save and restore 1763 * EL1 context on the 'cpu_context' structure for the specified security 1764 * state. 1765 ******************************************************************************/ 1766 void cm_el1_sysregs_context_save(uint32_t security_state) 1767 { 1768 cpu_context_t *ctx; 1769 1770 ctx = cm_get_context(security_state); 1771 assert(ctx != NULL); 1772 1773 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1774 1775 #if IMAGE_BL31 1776 if (security_state == SECURE) 1777 PUBLISH_EVENT(cm_exited_secure_world); 1778 else 1779 PUBLISH_EVENT(cm_exited_normal_world); 1780 #endif 1781 } 1782 1783 void cm_el1_sysregs_context_restore(uint32_t security_state) 1784 { 1785 cpu_context_t *ctx; 1786 1787 ctx = cm_get_context(security_state); 1788 assert(ctx != NULL); 1789 1790 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1791 1792 #if IMAGE_BL31 1793 if (security_state == SECURE) 1794 PUBLISH_EVENT(cm_entering_secure_world); 1795 else 1796 PUBLISH_EVENT(cm_entering_normal_world); 1797 #endif 1798 } 1799 1800 /******************************************************************************* 1801 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1802 * given security state with the given entrypoint 1803 ******************************************************************************/ 1804 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1805 { 1806 cpu_context_t *ctx; 1807 el3_state_t *state; 1808 1809 ctx = cm_get_context(security_state); 1810 assert(ctx != NULL); 1811 1812 /* Populate EL3 state so that ERET jumps to the correct entry */ 1813 state = get_el3state_ctx(ctx); 1814 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1815 } 1816 1817 /******************************************************************************* 1818 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1819 * pertaining to the given security state 1820 ******************************************************************************/ 1821 void cm_set_elr_spsr_el3(uint32_t security_state, 1822 uintptr_t entrypoint, uint32_t spsr) 1823 { 1824 cpu_context_t *ctx; 1825 el3_state_t *state; 1826 1827 ctx = cm_get_context(security_state); 1828 assert(ctx != NULL); 1829 1830 /* Populate EL3 state so that ERET jumps to the correct entry */ 1831 state = get_el3state_ctx(ctx); 1832 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1833 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1834 } 1835 1836 /******************************************************************************* 1837 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1838 * pertaining to the given security state using the value and bit position 1839 * specified in the parameters. It preserves all other bits. 1840 ******************************************************************************/ 1841 void cm_write_scr_el3_bit(uint32_t security_state, 1842 uint32_t bit_pos, 1843 uint32_t value) 1844 { 1845 cpu_context_t *ctx; 1846 el3_state_t *state; 1847 u_register_t scr_el3; 1848 1849 ctx = cm_get_context(security_state); 1850 assert(ctx != NULL); 1851 1852 /* Ensure that the bit position is a valid one */ 1853 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1854 1855 /* Ensure that the 'value' is only a bit wide */ 1856 assert(value <= 1U); 1857 1858 /* 1859 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1860 * and set it to its new value. 1861 */ 1862 state = get_el3state_ctx(ctx); 1863 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1864 scr_el3 &= ~(1UL << bit_pos); 1865 scr_el3 |= (u_register_t)value << bit_pos; 1866 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1867 } 1868 1869 /******************************************************************************* 1870 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1871 * given security state. 1872 ******************************************************************************/ 1873 u_register_t cm_get_scr_el3(uint32_t security_state) 1874 { 1875 cpu_context_t *ctx; 1876 el3_state_t *state; 1877 1878 ctx = cm_get_context(security_state); 1879 assert(ctx != NULL); 1880 1881 /* Populate EL3 state so that ERET jumps to the correct entry */ 1882 state = get_el3state_ctx(ctx); 1883 return read_ctx_reg(state, CTX_SCR_EL3); 1884 } 1885 1886 /******************************************************************************* 1887 * This function is used to program the context that's used for exception 1888 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1889 * the required security state 1890 ******************************************************************************/ 1891 void cm_set_next_eret_context(uint32_t security_state) 1892 { 1893 cpu_context_t *ctx; 1894 1895 ctx = cm_get_context(security_state); 1896 assert(ctx != NULL); 1897 1898 cm_set_next_context(ctx); 1899 } 1900