1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_common(cpu_context_t *ctx); 46 static void manage_extensions_nonsecure(cpu_context_t *ctx); 47 static void manage_extensions_secure(cpu_context_t *ctx); 48 static void manage_extensions_secure_per_world(void); 49 50 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 51 { 52 u_register_t sctlr_elx, actlr_elx; 53 54 /* 55 * Initialise SCTLR_EL1 to the reset value corresponding to the target 56 * execution state setting all fields rather than relying on the hw. 57 * Some fields have architecturally UNKNOWN reset values and these are 58 * set to zero. 59 * 60 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 61 * 62 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 63 * required by PSCI specification) 64 */ 65 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 66 if (GET_RW(ep->spsr) == MODE_RW_64) { 67 sctlr_elx |= SCTLR_EL1_RES1; 68 } else { 69 /* 70 * If the target execution state is AArch32 then the following 71 * fields need to be set. 72 * 73 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 74 * instructions are not trapped to EL1. 75 * 76 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 77 * instructions are not trapped to EL1. 78 * 79 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 80 * CP15DMB, CP15DSB, and CP15ISB instructions. 81 */ 82 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 83 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 84 } 85 86 #if ERRATA_A75_764081 87 /* 88 * If workaround of errata 764081 for Cortex-A75 is used then set 89 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 90 */ 91 sctlr_elx |= SCTLR_IESB_BIT; 92 #endif 93 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 94 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 95 96 /* 97 * Base the context ACTLR_EL1 on the current value, as it is 98 * implementation defined. The context restore process will write 99 * the value from the context to the actual register and can cause 100 * problems for processor cores that don't expect certain bits to 101 * be zero. 102 */ 103 actlr_elx = read_actlr_el1(); 104 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 105 } 106 107 /****************************************************************************** 108 * This function performs initializations that are specific to SECURE state 109 * and updates the cpu context specified by 'ctx'. 110 *****************************************************************************/ 111 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 112 { 113 u_register_t scr_el3; 114 el3_state_t *state; 115 116 state = get_el3state_ctx(ctx); 117 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 118 119 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 120 /* 121 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 122 * indicated by the interrupt routing model for BL31. 123 */ 124 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 125 #endif 126 127 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 128 if (is_feat_mte2_supported()) { 129 scr_el3 |= SCR_ATA_BIT; 130 } 131 132 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 133 134 /* 135 * Initialize EL1 context registers unless SPMC is running 136 * at S-EL2. 137 */ 138 #if !SPMD_SPM_AT_SEL2 139 setup_el1_context(ctx, ep); 140 #endif 141 142 manage_extensions_secure(ctx); 143 144 /** 145 * manage_extensions_secure_per_world api has to be executed once, 146 * as the registers getting initialised, maintain constant value across 147 * all the cpus for the secure world. 148 * Henceforth, this check ensures that the registers are initialised once 149 * and avoids re-initialization from multiple cores. 150 */ 151 if (!has_secure_perworld_init) { 152 manage_extensions_secure_per_world(); 153 } 154 155 } 156 157 #if ENABLE_RME 158 /****************************************************************************** 159 * This function performs initializations that are specific to REALM state 160 * and updates the cpu context specified by 'ctx'. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 170 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 171 172 /* CSV2 version 2 and above */ 173 if (is_feat_csv2_2_supported()) { 174 /* Enable access to the SCXTNUM_ELx registers. */ 175 scr_el3 |= SCR_EnSCXT_BIT; 176 } 177 178 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 179 } 180 #endif /* ENABLE_RME */ 181 182 /****************************************************************************** 183 * This function performs initializations that are specific to NON-SECURE state 184 * and updates the cpu context specified by 'ctx'. 185 *****************************************************************************/ 186 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 187 { 188 u_register_t scr_el3; 189 el3_state_t *state; 190 191 state = get_el3state_ctx(ctx); 192 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 193 194 /* SCR_NS: Set the NS bit */ 195 scr_el3 |= SCR_NS_BIT; 196 197 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 198 if (is_feat_mte2_supported()) { 199 scr_el3 |= SCR_ATA_BIT; 200 } 201 202 #if !CTX_INCLUDE_PAUTH_REGS 203 /* 204 * Pointer Authentication feature, if present, is always enabled by default 205 * for Non secure lower exception levels. We do not have an explicit 206 * flag to set it. 207 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 208 * exception levels of secure and realm worlds. 209 * 210 * To prevent the leakage between the worlds during world switch, 211 * we enable it only for the non-secure world. 212 * 213 * If the Secure/realm world wants to use pointer authentication, 214 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 215 * it will be enabled globally for all the contexts. 216 * 217 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 218 * other than EL3 219 * 220 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 221 * than EL3 222 */ 223 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 224 225 #endif /* CTX_INCLUDE_PAUTH_REGS */ 226 227 #if HANDLE_EA_EL3_FIRST_NS 228 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 229 scr_el3 |= SCR_EA_BIT; 230 #endif 231 232 #if RAS_TRAP_NS_ERR_REC_ACCESS 233 /* 234 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 235 * and RAS ERX registers from EL1 and EL2(from any security state) 236 * are trapped to EL3. 237 * Set here to trap only for NS EL1/EL2 238 * 239 */ 240 scr_el3 |= SCR_TERR_BIT; 241 #endif 242 243 /* CSV2 version 2 and above */ 244 if (is_feat_csv2_2_supported()) { 245 /* Enable access to the SCXTNUM_ELx registers. */ 246 scr_el3 |= SCR_EnSCXT_BIT; 247 } 248 249 #ifdef IMAGE_BL31 250 /* 251 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 252 * indicated by the interrupt routing model for BL31. 253 */ 254 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 255 #endif 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 258 /* Initialize EL1 context registers */ 259 setup_el1_context(ctx, ep); 260 261 /* Initialize EL2 context registers */ 262 #if CTX_INCLUDE_EL2_REGS 263 264 /* 265 * Initialize SCTLR_EL2 context register using Endianness value 266 * taken from the entrypoint attribute. 267 */ 268 u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 269 sctlr_el2_val |= SCTLR_EL2_RES1; 270 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val); 271 272 273 if (is_feat_hcx_supported()) { 274 /* 275 * Initialize register HCRX_EL2 with its init value. 276 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 277 * chance that this can lead to unexpected behavior in lower 278 * ELs that have not been updated since the introduction of 279 * this feature if not properly initialized, especially when 280 * it comes to those bits that enable/disable traps. 281 */ 282 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 283 HCRX_EL2_INIT_VAL); 284 } 285 286 if (is_feat_fgt_supported()) { 287 /* 288 * Initialize HFG*_EL2 registers with a default value so legacy 289 * systems unaware of FEAT_FGT do not get trapped due to their lack 290 * of initialization for this feature. 291 */ 292 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 293 HFGITR_EL2_INIT_VAL); 294 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 295 HFGRTR_EL2_INIT_VAL); 296 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 297 HFGWTR_EL2_INIT_VAL); 298 } 299 300 #endif /* CTX_INCLUDE_EL2_REGS */ 301 302 manage_extensions_nonsecure(ctx); 303 } 304 305 /******************************************************************************* 306 * The following function performs initialization of the cpu_context 'ctx' 307 * for first use that is common to all security states, and sets the 308 * initial entrypoint state as specified by the entry_point_info structure. 309 * 310 * The EE and ST attributes are used to configure the endianness and secure 311 * timer availability for the new execution context. 312 ******************************************************************************/ 313 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 314 { 315 u_register_t scr_el3; 316 u_register_t mdcr_el3; 317 el3_state_t *state; 318 gp_regs_t *gp_regs; 319 320 state = get_el3state_ctx(ctx); 321 322 /* Clear any residual register values from the context */ 323 zeromem(ctx, sizeof(*ctx)); 324 325 /* 326 * The lower-EL context is zeroed so that no stale values leak to a world. 327 * It is assumed that an all-zero lower-EL context is good enough for it 328 * to boot correctly. However, there are very few registers where this 329 * is not true and some values need to be recreated. 330 */ 331 #if CTX_INCLUDE_EL2_REGS 332 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 333 334 /* 335 * These bits are set in the gicv3 driver. Losing them (especially the 336 * SRE bit) is problematic for all worlds. Henceforth recreate them. 337 */ 338 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 339 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 340 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 341 #endif /* CTX_INCLUDE_EL2_REGS */ 342 343 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 344 scr_el3 = SCR_RESET_VAL; 345 346 /* 347 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 348 * EL2, EL1 and EL0 are not trapped to EL3. 349 * 350 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 351 * EL2, EL1 and EL0 are not trapped to EL3. 352 * 353 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 354 * both Security states and both Execution states. 355 * 356 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 357 * Non-secure memory. 358 */ 359 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 360 361 scr_el3 |= SCR_SIF_BIT; 362 363 /* 364 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 365 * Exception level as specified by SPSR. 366 */ 367 if (GET_RW(ep->spsr) == MODE_RW_64) { 368 scr_el3 |= SCR_RW_BIT; 369 } 370 371 /* 372 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 373 * Secure timer registers to EL3, from AArch64 state only, if specified 374 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 375 * bit always behaves as 1 (i.e. secure physical timer register access 376 * is not trapped) 377 */ 378 if (EP_GET_ST(ep->h.attr) != 0U) { 379 scr_el3 |= SCR_ST_BIT; 380 } 381 382 /* 383 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 384 * SCR_EL3.HXEn. 385 */ 386 if (is_feat_hcx_supported()) { 387 scr_el3 |= SCR_HXEn_BIT; 388 } 389 390 /* 391 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 392 * registers are trapped to EL3. 393 */ 394 #if ENABLE_FEAT_RNG_TRAP 395 scr_el3 |= SCR_TRNDR_BIT; 396 #endif 397 398 #if FAULT_INJECTION_SUPPORT 399 /* Enable fault injection from lower ELs */ 400 scr_el3 |= SCR_FIEN_BIT; 401 #endif 402 403 #if CTX_INCLUDE_PAUTH_REGS 404 /* 405 * Enable Pointer Authentication globally for all the worlds. 406 * 407 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 408 * other than EL3 409 * 410 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 411 * than EL3 412 */ 413 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 414 #endif /* CTX_INCLUDE_PAUTH_REGS */ 415 416 /* 417 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 418 */ 419 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 420 scr_el3 |= SCR_TCR2EN_BIT; 421 } 422 423 /* 424 * SCR_EL3.PIEN: Enable permission indirection and overlay 425 * registers for AArch64 if present. 426 */ 427 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 428 scr_el3 |= SCR_PIEN_BIT; 429 } 430 431 /* 432 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 433 */ 434 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 435 scr_el3 |= SCR_GCSEn_BIT; 436 } 437 438 /* 439 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 440 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 441 * next mode is Hyp. 442 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 443 * same conditions as HVC instructions and when the processor supports 444 * ARMv8.6-FGT. 445 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 446 * CNTPOFF_EL2 register under the same conditions as HVC instructions 447 * and when the processor supports ECV. 448 */ 449 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 450 || ((GET_RW(ep->spsr) != MODE_RW_64) 451 && (GET_M32(ep->spsr) == MODE32_hyp))) { 452 scr_el3 |= SCR_HCE_BIT; 453 454 if (is_feat_fgt_supported()) { 455 scr_el3 |= SCR_FGTEN_BIT; 456 } 457 458 if (is_feat_ecv_supported()) { 459 scr_el3 |= SCR_ECVEN_BIT; 460 } 461 } 462 463 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 464 if (is_feat_twed_supported()) { 465 /* Set delay in SCR_EL3 */ 466 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 467 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 468 << SCR_TWEDEL_SHIFT); 469 470 /* Enable WFE delay */ 471 scr_el3 |= SCR_TWEDEn_BIT; 472 } 473 474 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 475 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 476 if (is_feat_sel2_supported()) { 477 scr_el3 |= SCR_EEL2_BIT; 478 } 479 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 480 481 /* 482 * Populate EL3 state so that we've the right context 483 * before doing ERET 484 */ 485 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 486 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 487 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 488 489 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 490 mdcr_el3 = MDCR_EL3_RESET_VAL; 491 492 /* --------------------------------------------------------------------- 493 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 494 * Some fields are architecturally UNKNOWN on reset. 495 * 496 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 497 * Debug exceptions, other than Breakpoint Instruction exceptions, are 498 * disabled from all ELs in Secure state. 499 * 500 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 501 * privileged debug from S-EL1. 502 * 503 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 504 * access to the powerdown debug registers do not trap to EL3. 505 * 506 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 507 * debug registers, other than those registers that are controlled by 508 * MDCR_EL3.TDOSA. 509 */ 510 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 511 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 512 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 513 514 /* 515 * Configure MDCR_EL3 register as applicable for each world 516 * (NS/Secure/Realm) context. 517 */ 518 manage_extensions_common(ctx); 519 520 /* 521 * Store the X0-X7 value from the entrypoint into the context 522 * Use memcpy as we are in control of the layout of the structures 523 */ 524 gp_regs = get_gpregs_ctx(ctx); 525 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 526 } 527 528 /******************************************************************************* 529 * Context management library initialization routine. This library is used by 530 * runtime services to share pointers to 'cpu_context' structures for secure 531 * non-secure and realm states. Management of the structures and their associated 532 * memory is not done by the context management library e.g. the PSCI service 533 * manages the cpu context used for entry from and exit to the non-secure state. 534 * The Secure payload dispatcher service manages the context(s) corresponding to 535 * the secure state. It also uses this library to get access to the non-secure 536 * state cpu context pointers. 537 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 538 * which will be used for programming an entry into a lower EL. The same context 539 * will be used to save state upon exception entry from that EL. 540 ******************************************************************************/ 541 void __init cm_init(void) 542 { 543 /* 544 * The context management library has only global data to initialize, but 545 * that will be done when the BSS is zeroed out. 546 */ 547 } 548 549 /******************************************************************************* 550 * This is the high-level function used to initialize the cpu_context 'ctx' for 551 * first use. It performs initializations that are common to all security states 552 * and initializations specific to the security state specified in 'ep' 553 ******************************************************************************/ 554 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 555 { 556 unsigned int security_state; 557 558 assert(ctx != NULL); 559 560 /* 561 * Perform initializations that are common 562 * to all security states 563 */ 564 setup_context_common(ctx, ep); 565 566 security_state = GET_SECURITY_STATE(ep->h.attr); 567 568 /* Perform security state specific initializations */ 569 switch (security_state) { 570 case SECURE: 571 setup_secure_context(ctx, ep); 572 break; 573 #if ENABLE_RME 574 case REALM: 575 setup_realm_context(ctx, ep); 576 break; 577 #endif 578 case NON_SECURE: 579 setup_ns_context(ctx, ep); 580 break; 581 default: 582 ERROR("Invalid security state\n"); 583 panic(); 584 break; 585 } 586 } 587 588 /******************************************************************************* 589 * Enable architecture extensions for EL3 execution. This function only updates 590 * registers in-place which are expected to either never change or be 591 * overwritten by el3_exit. 592 ******************************************************************************/ 593 #if IMAGE_BL31 594 void cm_manage_extensions_el3(void) 595 { 596 if (is_feat_amu_supported()) { 597 amu_init_el3(); 598 } 599 600 if (is_feat_sme_supported()) { 601 sme_init_el3(); 602 } 603 604 pmuv3_init_el3(); 605 } 606 #endif /* IMAGE_BL31 */ 607 608 /****************************************************************************** 609 * Function to initialise the registers with the RESET values in the context 610 * memory, which are maintained per world. 611 ******************************************************************************/ 612 #if IMAGE_BL31 613 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 614 { 615 /* 616 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 617 * 618 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 619 * by Advanced SIMD, floating-point or SVE instructions (if 620 * implemented) do not trap to EL3. 621 * 622 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 623 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 624 */ 625 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 626 627 per_world_ctx->ctx_cptr_el3 = cptr_el3; 628 629 /* 630 * Initialize MPAM3_EL3 to its default reset value 631 * 632 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 633 * all lower ELn MPAM3_EL3 register access to, trap to EL3 634 */ 635 636 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 637 } 638 #endif /* IMAGE_BL31 */ 639 640 /******************************************************************************* 641 * Initialise per_world_context for Non-Secure world. 642 * This function enables the architecture extensions, which have same value 643 * across the cores for the non-secure world. 644 ******************************************************************************/ 645 #if IMAGE_BL31 646 void manage_extensions_nonsecure_per_world(void) 647 { 648 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 649 650 if (is_feat_sme_supported()) { 651 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 652 } 653 654 if (is_feat_sve_supported()) { 655 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 656 } 657 658 if (is_feat_amu_supported()) { 659 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 660 } 661 662 if (is_feat_sys_reg_trace_supported()) { 663 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 664 } 665 666 if (is_feat_mpam_supported()) { 667 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 668 } 669 } 670 #endif /* IMAGE_BL31 */ 671 672 /******************************************************************************* 673 * Initialise per_world_context for Secure world. 674 * This function enables the architecture extensions, which have same value 675 * across the cores for the secure world. 676 ******************************************************************************/ 677 static void manage_extensions_secure_per_world(void) 678 { 679 #if IMAGE_BL31 680 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 681 682 if (is_feat_sme_supported()) { 683 684 if (ENABLE_SME_FOR_SWD) { 685 /* 686 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 687 * SME, SVE, and FPU/SIMD context properly managed. 688 */ 689 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 690 } else { 691 /* 692 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 693 * world can safely use the associated registers. 694 */ 695 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 696 } 697 } 698 if (is_feat_sve_supported()) { 699 if (ENABLE_SVE_FOR_SWD) { 700 /* 701 * Enable SVE and FPU in secure context, SPM must ensure 702 * that the SVE and FPU register contexts are properly managed. 703 */ 704 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 705 } else { 706 /* 707 * Disable SVE and FPU in secure context so non-secure world 708 * can safely use them. 709 */ 710 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 711 } 712 } 713 714 /* NS can access this but Secure shouldn't */ 715 if (is_feat_sys_reg_trace_supported()) { 716 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 717 } 718 719 has_secure_perworld_init = true; 720 #endif /* IMAGE_BL31 */ 721 } 722 723 /******************************************************************************* 724 * Enable architecture extensions on first entry to Non-secure world only 725 * and disable for secure world. 726 * 727 * NOTE: Arch features which have been provided with the capability of getting 728 * enabled only for non-secure world and being disabled for secure world are 729 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 730 ******************************************************************************/ 731 static void manage_extensions_common(cpu_context_t *ctx) 732 { 733 #if IMAGE_BL31 734 if (is_feat_spe_supported()) { 735 /* 736 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 737 */ 738 spe_enable(ctx); 739 } 740 741 if (is_feat_trbe_supported()) { 742 /* 743 * Enable FEAT_SPE for Non-Secure and prohibit for Secure and 744 * Realm state. 745 */ 746 trbe_enable(ctx); 747 } 748 749 if (is_feat_trf_supported()) { 750 /* 751 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 752 */ 753 trf_enable(ctx); 754 } 755 756 if (is_feat_brbe_supported()) { 757 /* 758 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 759 */ 760 brbe_enable(ctx); 761 } 762 #endif /* IMAGE_BL31 */ 763 } 764 765 /******************************************************************************* 766 * Enable architecture extensions on first entry to Non-secure world. 767 ******************************************************************************/ 768 static void manage_extensions_nonsecure(cpu_context_t *ctx) 769 { 770 #if IMAGE_BL31 771 if (is_feat_amu_supported()) { 772 amu_enable(ctx); 773 } 774 775 if (is_feat_sme_supported()) { 776 sme_enable(ctx); 777 } 778 779 pmuv3_enable(ctx); 780 #endif /* IMAGE_BL31 */ 781 } 782 783 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 784 static __unused void enable_pauth_el2(void) 785 { 786 u_register_t hcr_el2 = read_hcr_el2(); 787 /* 788 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 789 * accessing key registers or using pointer authentication instructions 790 * from lower ELs. 791 */ 792 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 793 794 write_hcr_el2(hcr_el2); 795 } 796 797 #if INIT_UNUSED_NS_EL2 798 /******************************************************************************* 799 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 800 * world when EL2 is empty and unused. 801 ******************************************************************************/ 802 static void manage_extensions_nonsecure_el2_unused(void) 803 { 804 #if IMAGE_BL31 805 if (is_feat_spe_supported()) { 806 spe_init_el2_unused(); 807 } 808 809 if (is_feat_amu_supported()) { 810 amu_init_el2_unused(); 811 } 812 813 if (is_feat_mpam_supported()) { 814 mpam_init_el2_unused(); 815 } 816 817 if (is_feat_trbe_supported()) { 818 trbe_init_el2_unused(); 819 } 820 821 if (is_feat_sys_reg_trace_supported()) { 822 sys_reg_trace_init_el2_unused(); 823 } 824 825 if (is_feat_trf_supported()) { 826 trf_init_el2_unused(); 827 } 828 829 pmuv3_init_el2_unused(); 830 831 if (is_feat_sve_supported()) { 832 sve_init_el2_unused(); 833 } 834 835 if (is_feat_sme_supported()) { 836 sme_init_el2_unused(); 837 } 838 839 #if ENABLE_PAUTH 840 enable_pauth_el2(); 841 #endif /* ENABLE_PAUTH */ 842 #endif /* IMAGE_BL31 */ 843 } 844 #endif /* INIT_UNUSED_NS_EL2 */ 845 846 /******************************************************************************* 847 * Enable architecture extensions on first entry to Secure world. 848 ******************************************************************************/ 849 static void manage_extensions_secure(cpu_context_t *ctx) 850 { 851 #if IMAGE_BL31 852 if (is_feat_sme_supported()) { 853 if (ENABLE_SME_FOR_SWD) { 854 /* 855 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 856 * must ensure SME, SVE, and FPU/SIMD context properly managed. 857 */ 858 sme_init_el3(); 859 sme_enable(ctx); 860 } else { 861 /* 862 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 863 * world can safely use the associated registers. 864 */ 865 sme_disable(ctx); 866 } 867 } 868 #endif /* IMAGE_BL31 */ 869 } 870 871 #if !IMAGE_BL1 872 /******************************************************************************* 873 * The following function initializes the cpu_context for a CPU specified by 874 * its `cpu_idx` for first use, and sets the initial entrypoint state as 875 * specified by the entry_point_info structure. 876 ******************************************************************************/ 877 void cm_init_context_by_index(unsigned int cpu_idx, 878 const entry_point_info_t *ep) 879 { 880 cpu_context_t *ctx; 881 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 882 cm_setup_context(ctx, ep); 883 } 884 #endif /* !IMAGE_BL1 */ 885 886 /******************************************************************************* 887 * The following function initializes the cpu_context for the current CPU 888 * for first use, and sets the initial entrypoint state as specified by the 889 * entry_point_info structure. 890 ******************************************************************************/ 891 void cm_init_my_context(const entry_point_info_t *ep) 892 { 893 cpu_context_t *ctx; 894 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 895 cm_setup_context(ctx, ep); 896 } 897 898 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 899 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 900 { 901 #if INIT_UNUSED_NS_EL2 902 u_register_t hcr_el2 = HCR_RESET_VAL; 903 u_register_t mdcr_el2; 904 u_register_t scr_el3; 905 906 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 907 908 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 909 if ((scr_el3 & SCR_RW_BIT) != 0U) { 910 hcr_el2 |= HCR_RW_BIT; 911 } 912 913 write_hcr_el2(hcr_el2); 914 915 /* 916 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 917 * All fields have architecturally UNKNOWN reset values. 918 */ 919 write_cptr_el2(CPTR_EL2_RESET_VAL); 920 921 /* 922 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 923 * reset and are set to zero except for field(s) listed below. 924 * 925 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 926 * Non-secure EL0 and EL1 accesses to the physical timer registers. 927 * 928 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 929 * Non-secure EL0 and EL1 accesses to the physical counter registers. 930 */ 931 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 932 933 /* 934 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 935 * UNKNOWN value. 936 */ 937 write_cntvoff_el2(0); 938 939 /* 940 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 941 * respectively. 942 */ 943 write_vpidr_el2(read_midr_el1()); 944 write_vmpidr_el2(read_mpidr_el1()); 945 946 /* 947 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 948 * 949 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 950 * translation is disabled, cache maintenance operations depend on the 951 * VMID. 952 * 953 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 954 * disabled. 955 */ 956 write_vttbr_el2(VTTBR_RESET_VAL & 957 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 958 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 959 960 /* 961 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 962 * Some fields are architecturally UNKNOWN on reset. 963 * 964 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 965 * register accesses to the Debug ROM registers are not trapped to EL2. 966 * 967 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 968 * accesses to the powerdown debug registers are not trapped to EL2. 969 * 970 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 971 * debug registers do not trap to EL2. 972 * 973 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 974 * EL2. 975 */ 976 mdcr_el2 = MDCR_EL2_RESET_VAL & 977 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 978 MDCR_EL2_TDE_BIT); 979 980 write_mdcr_el2(mdcr_el2); 981 982 /* 983 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 984 * 985 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 986 * EL1 accesses to System registers do not trap to EL2. 987 */ 988 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 989 990 /* 991 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 992 * reset. 993 * 994 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 995 * and prevent timer interrupts. 996 */ 997 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 998 999 manage_extensions_nonsecure_el2_unused(); 1000 #endif /* INIT_UNUSED_NS_EL2 */ 1001 } 1002 1003 /******************************************************************************* 1004 * Prepare the CPU system registers for first entry into realm, secure, or 1005 * normal world. 1006 * 1007 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1008 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1009 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1010 * For all entries, the EL1 registers are initialized from the cpu_context 1011 ******************************************************************************/ 1012 void cm_prepare_el3_exit(uint32_t security_state) 1013 { 1014 u_register_t sctlr_elx, scr_el3; 1015 cpu_context_t *ctx = cm_get_context(security_state); 1016 1017 assert(ctx != NULL); 1018 1019 if (security_state == NON_SECURE) { 1020 uint64_t el2_implemented = el_implemented(2); 1021 1022 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1023 CTX_SCR_EL3); 1024 1025 if (el2_implemented != EL_IMPL_NONE) { 1026 1027 /* 1028 * If context is not being used for EL2, initialize 1029 * HCRX_EL2 with its init value here. 1030 */ 1031 if (is_feat_hcx_supported()) { 1032 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1033 } 1034 1035 /* 1036 * Initialize Fine-grained trap registers introduced 1037 * by FEAT_FGT so all traps are initially disabled when 1038 * switching to EL2 or a lower EL, preventing undesired 1039 * behavior. 1040 */ 1041 if (is_feat_fgt_supported()) { 1042 /* 1043 * Initialize HFG*_EL2 registers with a default 1044 * value so legacy systems unaware of FEAT_FGT 1045 * do not get trapped due to their lack of 1046 * initialization for this feature. 1047 */ 1048 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1049 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1050 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1051 } 1052 1053 /* Condition to ensure EL2 is being used. */ 1054 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1055 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 1056 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 1057 CTX_SCTLR_EL1); 1058 sctlr_elx &= SCTLR_EE_BIT; 1059 sctlr_elx |= SCTLR_EL2_RES1; 1060 #if ERRATA_A75_764081 1061 /* 1062 * If workaround of errata 764081 for Cortex-A75 1063 * is used then set SCTLR_EL2.IESB to enable 1064 * Implicit Error Synchronization Barrier. 1065 */ 1066 sctlr_elx |= SCTLR_IESB_BIT; 1067 #endif /* ERRATA_A75_764081 */ 1068 write_sctlr_el2(sctlr_elx); 1069 } else { 1070 /* 1071 * (scr_el3 & SCR_HCE_BIT==0) 1072 * EL2 implemented but unused. 1073 */ 1074 init_nonsecure_el2_unused(ctx); 1075 } 1076 } 1077 } 1078 cm_el1_sysregs_context_restore(security_state); 1079 cm_set_next_eret_context(security_state); 1080 } 1081 1082 #if CTX_INCLUDE_EL2_REGS 1083 1084 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1085 { 1086 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1087 if (is_feat_amu_supported()) { 1088 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1089 } 1090 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1091 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1092 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1093 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1094 } 1095 1096 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1097 { 1098 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1099 if (is_feat_amu_supported()) { 1100 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1101 } 1102 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1103 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1104 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1105 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1106 } 1107 1108 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1109 { 1110 u_register_t mpam_idr = read_mpamidr_el1(); 1111 1112 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1113 1114 /* 1115 * The context registers that we intend to save would be part of the 1116 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1117 */ 1118 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1119 return; 1120 } 1121 1122 /* 1123 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1124 * MPAMIDR_HAS_HCR_BIT == 1. 1125 */ 1126 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1127 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1128 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1129 1130 /* 1131 * The number of MPAMVPM registers is implementation defined, their 1132 * number is stored in the MPAMIDR_EL1 register. 1133 */ 1134 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1135 case 7: 1136 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1137 __fallthrough; 1138 case 6: 1139 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1140 __fallthrough; 1141 case 5: 1142 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1143 __fallthrough; 1144 case 4: 1145 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1146 __fallthrough; 1147 case 3: 1148 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1149 __fallthrough; 1150 case 2: 1151 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1152 __fallthrough; 1153 case 1: 1154 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1155 break; 1156 } 1157 } 1158 1159 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1160 { 1161 u_register_t mpam_idr = read_mpamidr_el1(); 1162 1163 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1164 1165 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1166 return; 1167 } 1168 1169 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1170 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1171 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1172 1173 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1174 case 7: 1175 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1176 __fallthrough; 1177 case 6: 1178 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1179 __fallthrough; 1180 case 5: 1181 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1182 __fallthrough; 1183 case 4: 1184 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1185 __fallthrough; 1186 case 3: 1187 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1188 __fallthrough; 1189 case 2: 1190 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1191 __fallthrough; 1192 case 1: 1193 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1194 break; 1195 } 1196 } 1197 1198 /* --------------------------------------------------------------------------- 1199 * The following registers are not added: 1200 * ICH_AP0R<n>_EL2 1201 * ICH_AP1R<n>_EL2 1202 * ICH_LR<n>_EL2 1203 * 1204 * NOTE: For a system with S-EL2 present but not enabled, accessing 1205 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1206 * SCR_EL3.NS = 1 before accessing this register. 1207 * --------------------------------------------------------------------------- 1208 */ 1209 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1210 { 1211 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1212 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1213 #else 1214 u_register_t scr_el3 = read_scr_el3(); 1215 write_scr_el3(scr_el3 | SCR_NS_BIT); 1216 isb(); 1217 1218 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1219 1220 write_scr_el3(scr_el3); 1221 isb(); 1222 #endif 1223 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1224 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1225 } 1226 1227 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1228 { 1229 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1230 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1231 #else 1232 u_register_t scr_el3 = read_scr_el3(); 1233 write_scr_el3(scr_el3 | SCR_NS_BIT); 1234 isb(); 1235 1236 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1237 1238 write_scr_el3(scr_el3); 1239 isb(); 1240 #endif 1241 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1242 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1243 } 1244 1245 /* ----------------------------------------------------- 1246 * The following registers are not added: 1247 * AMEVCNTVOFF0<n>_EL2 1248 * AMEVCNTVOFF1<n>_EL2 1249 * ----------------------------------------------------- 1250 */ 1251 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1252 { 1253 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1254 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1255 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1256 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1257 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1258 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1259 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1260 if (CTX_INCLUDE_AARCH32_REGS) { 1261 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1262 } 1263 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1264 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1265 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1266 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1267 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1268 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1269 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1270 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1271 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1272 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1273 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1274 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1275 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1276 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1277 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1278 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1279 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1280 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1281 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1282 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1283 } 1284 1285 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1286 { 1287 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1288 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1289 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1290 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1291 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1292 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1293 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1294 if (CTX_INCLUDE_AARCH32_REGS) { 1295 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1296 } 1297 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1298 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1299 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1300 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1301 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1302 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1303 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1304 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1305 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1306 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1307 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1308 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1309 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1310 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1311 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1312 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1313 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1314 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1315 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1316 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1317 } 1318 1319 /******************************************************************************* 1320 * Save EL2 sysreg context 1321 ******************************************************************************/ 1322 void cm_el2_sysregs_context_save(uint32_t security_state) 1323 { 1324 cpu_context_t *ctx; 1325 el2_sysregs_t *el2_sysregs_ctx; 1326 1327 ctx = cm_get_context(security_state); 1328 assert(ctx != NULL); 1329 1330 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1331 1332 el2_sysregs_context_save_common(el2_sysregs_ctx); 1333 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1334 1335 if (is_feat_mte2_supported()) { 1336 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1337 } 1338 1339 if (is_feat_mpam_supported()) { 1340 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1341 } 1342 1343 if (is_feat_fgt_supported()) { 1344 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1345 } 1346 1347 if (is_feat_ecv_v2_supported()) { 1348 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1349 } 1350 1351 if (is_feat_vhe_supported()) { 1352 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1353 read_contextidr_el2()); 1354 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1355 } 1356 1357 if (is_feat_ras_supported()) { 1358 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1359 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1360 } 1361 1362 if (is_feat_nv2_supported()) { 1363 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1364 } 1365 1366 if (is_feat_trf_supported()) { 1367 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1368 } 1369 1370 if (is_feat_csv2_2_supported()) { 1371 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1372 read_scxtnum_el2()); 1373 } 1374 1375 if (is_feat_hcx_supported()) { 1376 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1377 } 1378 1379 if (is_feat_tcr2_supported()) { 1380 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1381 } 1382 1383 if (is_feat_sxpie_supported()) { 1384 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1385 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1386 } 1387 1388 if (is_feat_sxpoe_supported()) { 1389 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1390 } 1391 1392 if (is_feat_s2pie_supported()) { 1393 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1394 } 1395 1396 if (is_feat_gcs_supported()) { 1397 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1398 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1399 } 1400 } 1401 1402 /******************************************************************************* 1403 * Restore EL2 sysreg context 1404 ******************************************************************************/ 1405 void cm_el2_sysregs_context_restore(uint32_t security_state) 1406 { 1407 cpu_context_t *ctx; 1408 el2_sysregs_t *el2_sysregs_ctx; 1409 1410 ctx = cm_get_context(security_state); 1411 assert(ctx != NULL); 1412 1413 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1414 1415 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1416 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1417 1418 if (is_feat_mte2_supported()) { 1419 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1420 } 1421 1422 if (is_feat_mpam_supported()) { 1423 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1424 } 1425 1426 if (is_feat_fgt_supported()) { 1427 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1428 } 1429 1430 if (is_feat_ecv_v2_supported()) { 1431 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1432 } 1433 1434 if (is_feat_vhe_supported()) { 1435 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1436 contextidr_el2)); 1437 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1438 } 1439 1440 if (is_feat_ras_supported()) { 1441 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1442 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1443 } 1444 1445 if (is_feat_nv2_supported()) { 1446 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1447 } 1448 1449 if (is_feat_trf_supported()) { 1450 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1451 } 1452 1453 if (is_feat_csv2_2_supported()) { 1454 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1455 scxtnum_el2)); 1456 } 1457 1458 if (is_feat_hcx_supported()) { 1459 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1460 } 1461 1462 if (is_feat_tcr2_supported()) { 1463 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1464 } 1465 1466 if (is_feat_sxpie_supported()) { 1467 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1468 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1469 } 1470 1471 if (is_feat_sxpoe_supported()) { 1472 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1473 } 1474 1475 if (is_feat_s2pie_supported()) { 1476 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1477 } 1478 1479 if (is_feat_gcs_supported()) { 1480 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1481 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1482 } 1483 } 1484 #endif /* CTX_INCLUDE_EL2_REGS */ 1485 1486 /******************************************************************************* 1487 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1488 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1489 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1490 * cm_prepare_el3_exit function. 1491 ******************************************************************************/ 1492 void cm_prepare_el3_exit_ns(void) 1493 { 1494 #if CTX_INCLUDE_EL2_REGS 1495 #if ENABLE_ASSERTIONS 1496 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1497 assert(ctx != NULL); 1498 1499 /* Assert that EL2 is used. */ 1500 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1501 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1502 (el_implemented(2U) != EL_IMPL_NONE)); 1503 #endif /* ENABLE_ASSERTIONS */ 1504 1505 /* Restore EL2 and EL1 sysreg contexts */ 1506 cm_el2_sysregs_context_restore(NON_SECURE); 1507 cm_el1_sysregs_context_restore(NON_SECURE); 1508 cm_set_next_eret_context(NON_SECURE); 1509 #else 1510 cm_prepare_el3_exit(NON_SECURE); 1511 #endif /* CTX_INCLUDE_EL2_REGS */ 1512 } 1513 1514 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1515 { 1516 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1517 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1518 1519 #if !ERRATA_SPECULATIVE_AT 1520 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1521 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1522 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1523 1524 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1525 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1526 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1527 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1528 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1529 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1530 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1531 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1532 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1533 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1534 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1535 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1536 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1537 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1538 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1539 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1540 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1541 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1542 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1543 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1544 1545 #if CTX_INCLUDE_AARCH32_REGS 1546 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1547 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1548 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1549 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1550 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1551 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1552 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1553 1554 #if NS_TIMER_SWITCH 1555 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1556 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1557 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1558 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1559 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1560 #endif /* NS_TIMER_SWITCH */ 1561 1562 #if ENABLE_FEAT_MTE2 1563 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1564 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1565 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1566 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1567 #endif /* ENABLE_FEAT_MTE2 */ 1568 1569 #if ENABLE_FEAT_RAS 1570 if (is_feat_ras_supported()) { 1571 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1572 } 1573 #endif 1574 1575 #if ENABLE_FEAT_S1PIE 1576 if (is_feat_s1pie_supported()) { 1577 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1578 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1579 } 1580 #endif 1581 1582 #if ENABLE_FEAT_S1POE 1583 if (is_feat_s1poe_supported()) { 1584 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1585 } 1586 #endif 1587 1588 #if ENABLE_FEAT_S2POE 1589 if (is_feat_s2poe_supported()) { 1590 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1591 } 1592 #endif 1593 1594 #if ENABLE_FEAT_TCR2 1595 if (is_feat_tcr2_supported()) { 1596 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1597 } 1598 #endif 1599 1600 #if ENABLE_TRF_FOR_NS 1601 if (is_feat_trf_supported()) { 1602 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1603 } 1604 #endif 1605 1606 #if ENABLE_FEAT_CSV2_2 1607 if (is_feat_csv2_2_supported()) { 1608 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1609 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1610 } 1611 #endif 1612 1613 #if ENABLE_FEAT_GCS 1614 if (is_feat_gcs_supported()) { 1615 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1616 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1617 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1618 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1619 } 1620 #endif 1621 } 1622 1623 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1624 { 1625 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1626 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1627 1628 #if !ERRATA_SPECULATIVE_AT 1629 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1630 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1631 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1632 1633 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1634 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1635 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1636 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1637 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1638 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1639 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1640 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1641 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1642 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1643 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1644 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1645 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1646 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1647 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1648 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1649 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1650 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1651 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1652 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1653 1654 #if CTX_INCLUDE_AARCH32_REGS 1655 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1656 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1657 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1658 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1659 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1660 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1661 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1662 1663 #if NS_TIMER_SWITCH 1664 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1665 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1666 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1667 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1668 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1669 #endif /* NS_TIMER_SWITCH */ 1670 1671 #if ENABLE_FEAT_MTE2 1672 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1673 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1674 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1675 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1676 #endif /* ENABLE_FEAT_MTE2 */ 1677 1678 #if ENABLE_FEAT_RAS 1679 if (is_feat_ras_supported()) { 1680 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1681 } 1682 #endif 1683 1684 #if ENABLE_FEAT_S1PIE 1685 if (is_feat_s1pie_supported()) { 1686 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1687 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1688 } 1689 #endif 1690 1691 #if ENABLE_FEAT_S1POE 1692 if (is_feat_s1poe_supported()) { 1693 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1694 } 1695 #endif 1696 1697 #if ENABLE_FEAT_S2POE 1698 if (is_feat_s2poe_supported()) { 1699 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1700 } 1701 #endif 1702 1703 #if ENABLE_FEAT_TCR2 1704 if (is_feat_tcr2_supported()) { 1705 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1706 } 1707 #endif 1708 1709 #if ENABLE_TRF_FOR_NS 1710 if (is_feat_trf_supported()) { 1711 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1712 } 1713 #endif 1714 1715 #if ENABLE_FEAT_CSV2_2 1716 if (is_feat_csv2_2_supported()) { 1717 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1718 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1719 } 1720 #endif 1721 1722 #if ENABLE_FEAT_GCS 1723 if (is_feat_gcs_supported()) { 1724 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1725 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1726 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1727 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1728 } 1729 #endif 1730 } 1731 1732 /******************************************************************************* 1733 * The next four functions are used by runtime services to save and restore 1734 * EL1 context on the 'cpu_context' structure for the specified security 1735 * state. 1736 ******************************************************************************/ 1737 void cm_el1_sysregs_context_save(uint32_t security_state) 1738 { 1739 cpu_context_t *ctx; 1740 1741 ctx = cm_get_context(security_state); 1742 assert(ctx != NULL); 1743 1744 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1745 1746 #if IMAGE_BL31 1747 if (security_state == SECURE) 1748 PUBLISH_EVENT(cm_exited_secure_world); 1749 else 1750 PUBLISH_EVENT(cm_exited_normal_world); 1751 #endif 1752 } 1753 1754 void cm_el1_sysregs_context_restore(uint32_t security_state) 1755 { 1756 cpu_context_t *ctx; 1757 1758 ctx = cm_get_context(security_state); 1759 assert(ctx != NULL); 1760 1761 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1762 1763 #if IMAGE_BL31 1764 if (security_state == SECURE) 1765 PUBLISH_EVENT(cm_entering_secure_world); 1766 else 1767 PUBLISH_EVENT(cm_entering_normal_world); 1768 #endif 1769 } 1770 1771 /******************************************************************************* 1772 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1773 * given security state with the given entrypoint 1774 ******************************************************************************/ 1775 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1776 { 1777 cpu_context_t *ctx; 1778 el3_state_t *state; 1779 1780 ctx = cm_get_context(security_state); 1781 assert(ctx != NULL); 1782 1783 /* Populate EL3 state so that ERET jumps to the correct entry */ 1784 state = get_el3state_ctx(ctx); 1785 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1786 } 1787 1788 /******************************************************************************* 1789 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1790 * pertaining to the given security state 1791 ******************************************************************************/ 1792 void cm_set_elr_spsr_el3(uint32_t security_state, 1793 uintptr_t entrypoint, uint32_t spsr) 1794 { 1795 cpu_context_t *ctx; 1796 el3_state_t *state; 1797 1798 ctx = cm_get_context(security_state); 1799 assert(ctx != NULL); 1800 1801 /* Populate EL3 state so that ERET jumps to the correct entry */ 1802 state = get_el3state_ctx(ctx); 1803 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1804 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1805 } 1806 1807 /******************************************************************************* 1808 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1809 * pertaining to the given security state using the value and bit position 1810 * specified in the parameters. It preserves all other bits. 1811 ******************************************************************************/ 1812 void cm_write_scr_el3_bit(uint32_t security_state, 1813 uint32_t bit_pos, 1814 uint32_t value) 1815 { 1816 cpu_context_t *ctx; 1817 el3_state_t *state; 1818 u_register_t scr_el3; 1819 1820 ctx = cm_get_context(security_state); 1821 assert(ctx != NULL); 1822 1823 /* Ensure that the bit position is a valid one */ 1824 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1825 1826 /* Ensure that the 'value' is only a bit wide */ 1827 assert(value <= 1U); 1828 1829 /* 1830 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1831 * and set it to its new value. 1832 */ 1833 state = get_el3state_ctx(ctx); 1834 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1835 scr_el3 &= ~(1UL << bit_pos); 1836 scr_el3 |= (u_register_t)value << bit_pos; 1837 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1838 } 1839 1840 /******************************************************************************* 1841 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1842 * given security state. 1843 ******************************************************************************/ 1844 u_register_t cm_get_scr_el3(uint32_t security_state) 1845 { 1846 cpu_context_t *ctx; 1847 el3_state_t *state; 1848 1849 ctx = cm_get_context(security_state); 1850 assert(ctx != NULL); 1851 1852 /* Populate EL3 state so that ERET jumps to the correct entry */ 1853 state = get_el3state_ctx(ctx); 1854 return read_ctx_reg(state, CTX_SCR_EL3); 1855 } 1856 1857 /******************************************************************************* 1858 * This function is used to program the context that's used for exception 1859 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1860 * the required security state 1861 ******************************************************************************/ 1862 void cm_set_next_eret_context(uint32_t security_state) 1863 { 1864 cpu_context_t *ctx; 1865 1866 ctx = cm_get_context(security_state); 1867 assert(ctx != NULL); 1868 1869 cm_set_next_context(ctx); 1870 } 1871