1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL1_H 8 #define CONTEXT_EL1_H 9 10 #ifndef __ASSEMBLER__ 11 12 /******************************************************************************* 13 * EL1 Registers: 14 * AArch64 EL1 system register context structure for preserving the 15 * architectural state during world switches. 16 ******************************************************************************/ 17 18 typedef struct el1_common_regs { 19 uint64_t spsr_el1; 20 uint64_t elr_el1; 21 22 #if (!ERRATA_SPECULATIVE_AT) 23 uint64_t sctlr_el1; 24 uint64_t tcr_el1; 25 #endif /* ERRATA_SPECULATIVE_AT=0 */ 26 27 uint64_t cpacr_el1; 28 uint64_t csselr_el1; 29 uint64_t sp_el1; 30 uint64_t esr_el1; 31 uint64_t ttbr0_el1; 32 uint64_t ttbr1_el1; 33 uint64_t mair_el1; 34 uint64_t amair_el1; 35 uint64_t actlr_el1; 36 uint64_t tpidr_el1; 37 uint64_t tpidr_el0; 38 uint64_t tpidrro_el0; 39 uint64_t par_el1; 40 uint64_t far_el1; 41 uint64_t afsr0_el1; 42 uint64_t afsr1_el1; 43 uint64_t contextidr_el1; 44 uint64_t vbar_el1; 45 uint64_t mdccint_el1; 46 uint64_t mdscr_el1; 47 } el1_common_regs_t; 48 49 typedef struct el1_aarch32_regs { 50 uint64_t spsr_abt; 51 uint64_t spsr_und; 52 uint64_t spsr_irq; 53 uint64_t spsr_fiq; 54 uint64_t dacr32_el2; 55 uint64_t ifsr32_el2; 56 } el1_aarch32_regs_t; 57 58 typedef struct el1_arch_timer_regs { 59 uint64_t cntp_ctl_el0; 60 uint64_t cntp_cval_el0; 61 uint64_t cntv_ctl_el0; 62 uint64_t cntv_cval_el0; 63 uint64_t cntkctl_el1; 64 } el1_arch_timer_regs_t; 65 66 typedef struct el1_mte2_regs { 67 uint64_t tfsre0_el1; 68 uint64_t tfsr_el1; 69 uint64_t rgsr_el1; 70 uint64_t gcr_el1; 71 } el1_mte2_regs_t; 72 73 typedef struct el1_ras_regs { 74 uint64_t disr_el1; 75 } el1_ras_regs_t; 76 77 typedef struct el1_s1pie_regs { 78 uint64_t pire0_el1; 79 uint64_t pir_el1; 80 } el1_s1pie_regs_t; 81 82 typedef struct el1_s1poe_regs { 83 uint64_t por_el1; 84 } el1_s1poe_regs_t; 85 86 typedef struct el1_s2poe_regs { 87 uint64_t s2por_el1; 88 } el1_s2poe_regs_t; 89 90 typedef struct el1_tcr2_regs { 91 uint64_t tcr2_el1; 92 } el1_tcr2_regs_t; 93 94 typedef struct el1_trf_regs { 95 uint64_t trfcr_el1; 96 } el1_trf_regs_t; 97 98 typedef struct el1_csv2_2_regs { 99 uint64_t scxtnum_el0; 100 uint64_t scxtnum_el1; 101 } el1_csv2_2_regs_t; 102 103 typedef struct el1_gcs_regs { 104 uint64_t gcscr_el1; 105 uint64_t gcscre0_el1; 106 uint64_t gcspr_el1; 107 uint64_t gcspr_el0; 108 } el1_gcs_regs_t; 109 110 typedef struct el1_the_regs { 111 uint64_t rcwmask_el1; 112 uint64_t rcwsmask_el1; 113 } el1_the_regs_t; 114 115 typedef struct el1_sctlr2_regs { 116 uint64_t sctlr2_el1; 117 } el1_sctlr2_regs_t; 118 119 typedef struct el1_sysregs { 120 121 el1_common_regs_t common; 122 123 #if CTX_INCLUDE_AARCH32_REGS 124 el1_aarch32_regs_t el1_aarch32; 125 #endif 126 127 #if NS_TIMER_SWITCH 128 el1_arch_timer_regs_t arch_timer; 129 #endif 130 131 #if ENABLE_FEAT_MTE2 132 el1_mte2_regs_t mte2; 133 #endif 134 135 #if ENABLE_FEAT_RAS 136 el1_ras_regs_t ras; 137 #endif 138 139 #if ENABLE_FEAT_S1PIE 140 el1_s1pie_regs_t s1pie; 141 #endif 142 143 #if ENABLE_FEAT_S1POE 144 el1_s1poe_regs_t s1poe; 145 #endif 146 147 #if ENABLE_FEAT_S2POE 148 el1_s2poe_regs_t s2poe; 149 #endif 150 151 #if ENABLE_FEAT_TCR2 152 el1_tcr2_regs_t tcr2; 153 #endif 154 155 #if ENABLE_TRF_FOR_NS 156 el1_trf_regs_t trf; 157 #endif 158 159 #if ENABLE_FEAT_CSV2_2 160 el1_csv2_2_regs_t csv2_2; 161 #endif 162 163 #if ENABLE_FEAT_GCS 164 el1_gcs_regs_t gcs; 165 #endif 166 167 #if ENABLE_FEAT_THE 168 el1_the_regs_t the; 169 #endif 170 171 #if ENABLE_FEAT_SCTLR2 172 el1_sctlr2_regs_t sctlr2; 173 #endif 174 175 } el1_sysregs_t; 176 177 178 /* 179 * Macros to access members related to individual features of the el1_sysregs_t 180 * structures. 181 */ 182 183 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) 184 185 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 186 = (uint64_t) (val)) 187 188 #if NS_TIMER_SWITCH 189 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) 190 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ 191 = (uint64_t) (val)) 192 #else 193 #define read_el1_ctx_arch_timer(ctx, reg) ULL(0) 194 #define write_el1_ctx_arch_timer(ctx, reg, val) 195 #endif /* NS_TIMER_SWITCH */ 196 197 #if CTX_INCLUDE_AARCH32_REGS 198 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) 199 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ 200 = (uint64_t) (val)) 201 #else 202 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) 203 #define write_el1_ctx_aarch32(ctx, reg, val) 204 #endif /* CTX_INCLUDE_AARCH32_REGS */ 205 206 #if ENABLE_FEAT_MTE2 207 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 208 #define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 209 = (uint64_t) (val)) 210 #else 211 #define read_el1_ctx_mte2(ctx, reg) ULL(0) 212 #define write_el1_ctx_mte2(ctx, reg, val) 213 #endif /* ENABLE_FEAT_MTE2 */ 214 215 #if ENABLE_FEAT_RAS 216 #define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg) 217 #define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 218 = (uint64_t) (val)) 219 #else 220 #define read_el1_ctx_ras(ctx, reg) ULL(0) 221 #define write_el1_ctx_ras(ctx, reg, val) 222 #endif /* ENABLE_FEAT_RAS */ 223 224 #if ENABLE_FEAT_S1PIE 225 #define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg) 226 #define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \ 227 = (uint64_t) (val)) 228 #else 229 #define read_el1_ctx_s1pie(ctx, reg) ULL(0) 230 #define write_el1_ctx_s1pie(ctx, reg, val) 231 #endif /* ENABLE_FEAT_S1PIE */ 232 233 #if ENABLE_FEAT_S1POE 234 #define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg) 235 #define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \ 236 = (uint64_t) (val)) 237 #else 238 #define read_el1_ctx_s1poe(ctx, reg) ULL(0) 239 #define write_el1_ctx_s1poe(ctx, reg, val) 240 #endif /* ENABLE_FEAT_S1POE */ 241 242 #if ENABLE_FEAT_S2POE 243 #define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg) 244 #define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \ 245 = (uint64_t) (val)) 246 #else 247 #define read_el1_ctx_s2poe(ctx, reg) ULL(0) 248 #define write_el1_ctx_s2poe(ctx, reg, val) 249 #endif /* ENABLE_FEAT_S2POE */ 250 251 #if ENABLE_FEAT_TCR2 252 #define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 253 #define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 254 = (uint64_t) (val)) 255 #else 256 #define read_el1_ctx_tcr2(ctx, reg) ULL(0) 257 #define write_el1_ctx_tcr2(ctx, reg, val) 258 #endif /* ENABLE_FEAT_TCR2 */ 259 260 #if ENABLE_TRF_FOR_NS 261 #define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg) 262 #define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 263 = (uint64_t) (val)) 264 #else 265 #define read_el1_ctx_trf(ctx, reg) ULL(0) 266 #define write_el1_ctx_trf(ctx, reg, val) 267 #endif /* ENABLE_TRF_FOR_NS */ 268 269 #if ENABLE_FEAT_CSV2_2 270 #define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg) 271 #define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \ 272 = (uint64_t) (val)) 273 #else 274 #define read_el1_ctx_csv2_2(ctx, reg) ULL(0) 275 #define write_el1_ctx_csv2_2(ctx, reg, val) 276 #endif /* ENABLE_FEAT_CSV2_2 */ 277 278 #if ENABLE_FEAT_GCS 279 #define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 280 #define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 281 = (uint64_t) (val)) 282 #else 283 #define read_el1_ctx_gcs(ctx, reg) ULL(0) 284 #define write_el1_ctx_gcs(ctx, reg, val) 285 #endif /* ENABLE_FEAT_GCS */ 286 287 #if ENABLE_FEAT_THE 288 #define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg) 289 #define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \ 290 = (uint64_t) (val)) 291 #else 292 #define read_el1_ctx_the(ctx, reg) ULL(0) 293 #define write_el1_ctx_the(ctx, reg, val) 294 #endif /* ENABLE_FEAT_THE */ 295 296 #if ENABLE_FEAT_SCTLR2 297 #define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 298 #define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 299 = (uint64_t) (val)) 300 #else 301 #define read_el1_ctx_sctlr2(ctx, reg) ULL(0) 302 #define write_el1_ctx_sctlr2(ctx, reg, val) 303 #endif /* ENABLE_FEAT_SCTLR2 */ 304 305 /******************************************************************************/ 306 #endif /* __ASSEMBLER__ */ 307 308 #endif /* CONTEXT_EL1_H */ 309