1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. Selects the branch protection features to use: 117- 0: Default value turns off all types of branch protection 118- 1: Enables all types of branch protection features 119- 2: Return address signing to its standard level 120- 3: Extend the signing to include leaf functions 121- 4: Turn on branch target identification mechanism 122 123 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 124 and resulting PAuth/BTI features. 125 126 +-------+--------------+-------+-----+ 127 | Value | GCC option | PAuth | BTI | 128 +=======+==============+=======+=====+ 129 | 0 | none | N | N | 130 +-------+--------------+-------+-----+ 131 | 1 | standard | Y | Y | 132 +-------+--------------+-------+-----+ 133 | 2 | pac-ret | Y | N | 134 +-------+--------------+-------+-----+ 135 | 3 | pac-ret+leaf | Y | N | 136 +-------+--------------+-------+-----+ 137 | 4 | bti | N | Y | 138 +-------+--------------+-------+-----+ 139 140 This option defaults to 0. 141 Note that Pointer Authentication is enabled for Non-secure world 142 irrespective of the value of this option if the CPU supports it. 143 144- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 145 compilation of each build. It must be set to a C string (including quotes 146 where applicable). Defaults to a string that contains the time and date of 147 the compilation. 148 149- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 150 build to be uniquely identified. Defaults to the current git commit id. 151 152- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 153 154- ``CFLAGS``: Extra user options appended on the compiler's command line in 155 addition to the options set by the build system. 156 157- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 158 release several CPUs out of reset. It can take either 0 (several CPUs may be 159 brought up) or 1 (only one CPU will ever be brought up during cold reset). 160 Default is 0. If the platform always brings up a single CPU, there is no 161 need to distinguish between primary and secondary CPUs and the boot path can 162 be optimised. The ``plat_is_my_cpu_primary()`` and 163 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 164 to be implemented in this case. 165 166- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 167 Defaults to ``tbbr``. 168 169- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 170 register state when an unexpected exception occurs during execution of 171 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 172 this is only enabled for a debug build of the firmware. 173 174- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 175 certificate generation tool to create new keys in case no valid keys are 176 present or specified. Allowed options are '0' or '1'. Default is '1'. 177 178- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 179 the AArch32 system registers to be included when saving and restoring the 180 CPU context. The option must be set to 0 for AArch64-only platforms (that 181 is on hardware that does not implement AArch32, or at least not at EL1 and 182 higher ELs). Default value is 1. 183 184- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 185 registers to be included when saving and restoring the CPU context. Default 186 is 0. 187 188- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 189 Memory System Resource Partitioning and Monitoring (MPAM) 190 registers to be included when saving and restoring the CPU context. 191 Default is '0'. 192 193- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 194 registers to be saved/restored when entering/exiting an EL2 execution 195 context. This flag can take values 0 to 2, to align with the 196 ``ENABLE_FEAT`` mechanism. Default value is 0. 197 198- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 199 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 200 to be included when saving and restoring the CPU context as part of world 201 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 202 mechanism. Default value is 0. 203 204 Note that Pointer Authentication is enabled for Non-secure world irrespective 205 of the value of this flag if the CPU supports it. 206 207- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 208 SVE registers to be included when saving and restoring the CPU context. Note 209 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 210 general, it is recommended to perform SVE context management in lower ELs 211 and skip in EL3 due to the additional cost of maintaining large data 212 structures to track the SVE state. Hence, the default value is 0. 213 214- ``DEBUG``: Chooses between a debug and release build. It can take either 0 215 (release) or 1 (debug) as values. 0 is the default. 216 217- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 218 authenticated decryption algorithm to be used to decrypt firmware/s during 219 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 220 this flag is ``none`` to disable firmware decryption which is an optional 221 feature as per TBBR. 222 223- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 224 of the binary image. If set to 1, then only the ELF image is built. 225 0 is the default. 226 227- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 228 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 229 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 230 mechanism. Default is ``0``. 231 232- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 233 Board Boot authentication at runtime. This option is meant to be enabled only 234 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 235 flag has to be enabled. 0 is the default. 236 237- ``E``: Boolean option to make warnings into errors. Default is 1. 238 239 When specifying higher warnings levels (``W=1`` and higher), this option 240 defaults to 0. This is done to encourage contributors to use them, as they 241 are expected to produce warnings that would otherwise fail the build. New 242 contributions are still expected to build with ``W=0`` and ``E=1`` (the 243 default). 244 245- ``EARLY_CONSOLE``: This option is used to enable early traces before default 246 console is properly setup. It introduces EARLY_* traces macros, that will 247 use the non-EARLY traces macros if the flag is enabled, or do nothing 248 otherwise. To use this feature, platforms will have to create the function 249 plat_setup_early_console(). 250 Default is 0 (disabled) 251 252- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 253 the normal boot flow. It must specify the entry point address of the EL3 254 payload. Please refer to the "Booting an EL3 payload" section for more 255 details. 256 257- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 258 (also known as group 1 counters). These are implementation-defined counters, 259 and as such require additional platform configuration. Default is 0. 260 261- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 262 allows platforms with auxiliary counters to describe them via the 263 ``HW_CONFIG`` device tree blob. Default is 0. 264 265- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 266 are compiled out. For debug builds, this option defaults to 1, and calls to 267 ``assert()`` are left in place. For release builds, this option defaults to 0 268 and calls to ``assert()`` function are compiled out. This option can be set 269 independently of ``DEBUG``. It can also be used to hide any auxiliary code 270 that is only required for the assertion and does not fit in the assertion 271 itself. 272 273- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 274 dumps or not. It is supported in both AArch64 and AArch32. However, in 275 AArch32 the format of the frame records are not defined in the AAPCS and they 276 are defined by the implementation. This implementation of backtrace only 277 supports the format used by GCC when T32 interworking is disabled. For this 278 reason enabling this option in AArch32 will force the compiler to only 279 generate A32 code. This option is enabled by default only in AArch64 debug 280 builds, but this behaviour can be overridden in each platform's Makefile or 281 in the build command line. 282 283- ``ENABLE_FEAT`` 284 The Arm architecture defines several architecture extension features, 285 named FEAT_xxx in the architecure manual. Some of those features require 286 setup code in higher exception levels, other features might be used by TF-A 287 code itself. 288 Most of the feature flags defined in the TF-A build system permit to take 289 the values 0, 1 or 2, with the following meaning: 290 291 :: 292 293 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 294 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 295 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 296 297 When setting the flag to 0, the feature is disabled during compilation, 298 and the compiler's optimisation stage and the linker will try to remove 299 as much of this code as possible. 300 If it is defined to 1, the code will use the feature unconditionally, so the 301 CPU is expected to support that feature. The FEATURE_DETECTION debug 302 feature, if enabled, will verify this. 303 If the feature flag is set to 2, support for the feature will be compiled 304 in, but its existence will be checked at runtime, so it works on CPUs with 305 or without the feature. This is mostly useful for platforms which either 306 support multiple different CPUs, or where the CPU is configured at runtime, 307 like in emulators. 308 309- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 310 extensions. This flag can take the values 0 to 2, to align with the 311 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 312 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 313 and this option can be used to enable this feature on those systems as well. 314 This flag can take the values 0 to 2, the default is 0. 315 316- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 317 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 318 onwards. This flag can take the values 0 to 2, to align with the 319 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 320 321- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 322 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 323 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 324 optional feature available on Arm v8.0 onwards. This flag can take values 325 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 326 Default value is ``0``. 327 328- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 329 extension. This feature is supported in AArch64 state only and is an optional 330 feature available in Arm v8.0 implementations. 331 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 332 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 333 mechanism. Default value is ``0``. 334 335- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 336 extension which allows the ability to implement more than 16 breakpoints 337 and/or watchpoints. This feature is mandatory from v8.9 and is optional 338 from v8.8. This flag can take the values of 0 to 2, to align with the 339 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 340 341- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 342 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 343 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 344 and upwards. This flag can take the values 0 to 2, to align with the 345 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 346 347- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 348 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 349 Physical Offset register) during EL2 to EL3 context save/restore operations. 350 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 351 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 352 mechanism. Default value is ``0``. 353 354- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 355 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 356 Read Trap Register) during EL2 to EL3 context save/restore operations. 357 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 358 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 359 mechanism. Default value is ``0``. 360 361- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 362 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 363 during EL2 to EL3 context save/restore operations. 364 Its an optional architectural feature and is available from v8.8 and upwards. 365 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 366 mechanism. Default value is ``0``. 367 368- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 369 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 370 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 371 mandatory architectural feature and is enabled from v8.7 and upwards. This 372 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 373 mechanism. Default value is ``0``. 374 375- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 376 if the platform wants to use this feature and MTE2 is enabled at ELX. 377 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 378 mechanism. Default value is ``0``. 379 380- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 381 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 382 permission fault for any privileged data access from EL1/EL2 to virtual 383 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 384 mandatory architectural feature and is enabled from v8.1 and upwards. This 385 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 386 mechanism. Default value is ``0``. 387 388- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 389 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 390 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 391 mechanism. Default value is ``0``. 392 393- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 394 extension. This feature is only supported in AArch64 state. This flag can 395 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 396 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 397 Armv8.5 onwards. 398 399- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 400 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 401 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 402 later CPUs. It is enabled from v8.5 and upwards and if needed can be 403 overidden from platforms explicitly. 404 405- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 406 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 407 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 408 mechanism. Default is ``0``. 409 410- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 411 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 412 available on Arm v8.6. This flag can take values 0 to 2, to align with the 413 ``ENABLE_FEAT`` mechanism. Default is ``0``. 414 415 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 416 delayed by the amount of value in ``TWED_DELAY``. 417 418- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 419 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 420 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 421 architectural feature and is enabled from v8.1 and upwards. It can take 422 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 423 Default value is ``0``. 424 425- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 426 allow access to TCR2_EL2 (extended translation control) from EL2 as 427 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 428 mandatory architectural feature and is enabled from v8.9 and upwards. This 429 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 430 mechanism. Default value is ``0``. 431 432- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 433 at EL2 and below, and context switch relevant registers. This flag 434 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 435 mechanism. Default value is ``0``. 436 437- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 438 at EL2 and below, and context switch relevant registers. This flag 439 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 440 mechanism. Default value is ``0``. 441 442- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 443 at EL2 and below, and context switch relevant registers. This flag 444 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 445 mechanism. Default value is ``0``. 446 447- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 448 at EL2 and below, and context switch relevant registers. This flag 449 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 450 mechanism. Default value is ``0``. 451 452- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 453 allow use of Guarded Control Stack from EL2 as well as adding the GCS 454 registers to the EL2 context save/restore operations. This flag can take 455 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 456 Default value is ``0``. 457 458- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 459 (Translation Hardening Extension) at EL2 and below, setting the bit 460 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 461 registers and context switch them. 462 Its an optional architectural feature and is available from v8.8 and upwards. 463 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 464 mechanism. Default value is ``0``. 465 466- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 467 support in GCC for TF-A. This option is currently only supported for 468 AArch64. Default is 0. 469 470- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 471 feature. MPAM is an optional Armv8.4 extension that enables various memory 472 system components and resources to define partitions; software running at 473 various ELs can assign themselves to desired partition to control their 474 performance aspects. 475 476 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 477 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 478 access their own MPAM registers without trapping into EL3. This option 479 doesn't make use of partitioning in EL3, however. Platform initialisation 480 code should configure and use partitions in EL3 as required. This option 481 defaults to ``2`` since MPAM is enabled by default for NS world only. 482 The flag is automatically disabled when the target 483 architecture is AArch32. 484 485- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 486 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 487 firmware to detect and limit high activity events to assist in SoC processor 488 power domain dynamic power budgeting and limit the triggering of whole-rail 489 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 490 491- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 492 allows platforms with cores supporting MPMM to describe them via the 493 ``HW_CONFIG`` device tree blob. Default is 0. 494 495- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 496 support within generic code in TF-A. This option is currently only supported 497 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 498 in BL32 (SP_min) for AARCH32. Default is 0. 499 500- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 501 Measurement Framework(PMF). Default is 0. 502 503- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 504 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 505 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 506 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 507 software. 508 509- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 510 instrumentation which injects timestamp collection points into TF-A to 511 allow runtime performance to be measured. Currently, only PSCI is 512 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 513 as well. Default is 0. 514 515- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 516 extensions. This is an optional architectural feature for AArch64. 517 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 518 mechanism. The default is 2 but is automatically disabled when the target 519 architecture is AArch32. 520 521- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 522 (SVE) for the Non-secure world only. SVE is an optional architectural feature 523 for AArch64. This flag can take the values 0 to 2, to align with the 524 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 525 systems that have SPM_MM enabled. The default value is 2. 526 527 Note that when SVE is enabled for the Non-secure world, access 528 to SVE, SIMD and floating-point functionality from the Secure world is 529 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 530 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 531 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 532 world data in the Z-registers which are aliased by the SIMD and FP registers. 533 534- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 535 for the Secure world. SVE is an optional architectural feature for AArch64. 536 The default is 0 and it is automatically disabled when the target architecture 537 is AArch32. 538 539 .. note:: 540 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 541 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 542 ``CTX_INCLUDE_SVE_REGS`` is also needed. 543 544- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 545 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 546 default value is set to "none". "strong" is the recommended stack protection 547 level if this feature is desired. "none" disables the stack protection. For 548 all values other than "none", the ``plat_get_stack_protector_canary()`` 549 platform hook needs to be implemented. The value is passed as the last 550 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 551 552- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 553 flag depends on ``DECRYPTION_SUPPORT`` build flag. 554 555- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 556 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 557 558- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 559 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 560 on ``DECRYPTION_SUPPORT`` build flag. 561 562- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 563 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 564 build flag. 565 566- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 567 deprecated platform APIs, helper functions or drivers within Trusted 568 Firmware as error. It can take the value 1 (flag the use of deprecated 569 APIs as error) or 0. The default is 0. 570 571- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 572 configure an Arm® Ethos™-N NPU. To use this service the target platform's 573 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 574 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 575 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 576 577- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 578 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 579 ``TRUSTED_BOARD_BOOT`` to be enabled. 580 581- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 582 (```ethosn.bin```). This firmware image will be included in the FIP and 583 loaded at runtime. 584 585- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 586 targeted at EL3. When set ``0`` (default), no exceptions are expected or 587 handled at EL3, and a panic will result. The exception to this rule is when 588 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 589 occuring during normal world execution, are trapped to EL3. Any exception 590 trapped during secure world execution are trapped to the SPMC. This is 591 supported only for AArch64 builds. 592 593- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 594 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 595 Default value is 40 (LOG_LEVEL_INFO). 596 597- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 598 injection from lower ELs, and this build option enables lower ELs to use 599 Error Records accessed via System Registers to inject faults. This is 600 applicable only to AArch64 builds. 601 602 This feature is intended for testing purposes only, and is advisable to keep 603 disabled for production images. 604 605- ``FIP_NAME``: This is an optional build option which specifies the FIP 606 filename for the ``fip`` target. Default is ``fip.bin``. 607 608- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 609 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 610 611- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 612 613 :: 614 615 0: Encryption is done with Secret Symmetric Key (SSK) which is common 616 for a class of devices. 617 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 618 unique per device. 619 620 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 621 622- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 623 tool to create certificates as per the Chain of Trust described in 624 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 625 include the certificates in the FIP and FWU_FIP. Default value is '0'. 626 627 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 628 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 629 the corresponding certificates, and to include those certificates in the 630 FIP and FWU_FIP. 631 632 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 633 images will not include support for Trusted Board Boot. The FIP will still 634 include the corresponding certificates. This FIP can be used to verify the 635 Chain of Trust on the host machine through other mechanisms. 636 637 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 638 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 639 will not include the corresponding certificates, causing a boot failure. 640 641- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 642 inherent support for specific EL3 type interrupts. Setting this build option 643 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 644 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 645 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 646 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 647 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 648 the Secure Payload interrupts needs to be synchronously handed over to Secure 649 EL1 for handling. The default value of this option is ``0``, which means the 650 Group 0 interrupts are assumed to be handled by Secure EL1. 651 652- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 653 Interrupts, resulting from errors in NS world, will be always trapped in 654 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 655 will be trapped in the current exception level (or in EL1 if the current 656 exception level is EL0). 657 658- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 659 software operations are required for CPUs to enter and exit coherency. 660 However, newer systems exist where CPUs' entry to and exit from coherency 661 is managed in hardware. Such systems require software to only initiate these 662 operations, and the rest is managed in hardware, minimizing active software 663 management. In such systems, this boolean option enables TF-A to carry out 664 build and run-time optimizations during boot and power management operations. 665 This option defaults to 0 and if it is enabled, then it implies 666 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 667 668 If this flag is disabled while the platform which TF-A is compiled for 669 includes cores that manage coherency in hardware, then a compilation error is 670 generated. This is based on the fact that a system cannot have, at the same 671 time, cores that manage coherency in hardware and cores that don't. In other 672 words, a platform cannot have, at the same time, cores that require 673 ``HW_ASSISTED_COHERENCY=1`` and cores that require 674 ``HW_ASSISTED_COHERENCY=0``. 675 676 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 677 translation library (xlat tables v2) must be used; version 1 of translation 678 library is not supported. 679 680- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 681 implementation defined system register accesses from lower ELs. Default 682 value is ``0``. 683 684- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 685 bottom, higher addresses at the top. This build flag can be set to '1' to 686 invert this behavior. Lower addresses will be printed at the top and higher 687 addresses at the bottom. 688 689- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 690 used for generating the PKCS keys and subsequent signing of the certificate. 691 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 692 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 693 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 694 compatibility. The default value of this flag is ``rsa`` which is the TBBR 695 compliant PKCS#1 RSA 2.1 scheme. 696 697- ``KEY_SIZE``: This build flag enables the user to select the key size for 698 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 699 depend on the chosen algorithm and the cryptographic module. 700 701 +---------------------------+------------------------------------+ 702 | KEY_ALG | Possible key sizes | 703 +===========================+====================================+ 704 | rsa | 1024 , 2048 (default), 3072, 4096 | 705 +---------------------------+------------------------------------+ 706 | ecdsa | 256 (default), 384 | 707 +---------------------------+------------------------------------+ 708 | ecdsa-brainpool-regular | unavailable | 709 +---------------------------+------------------------------------+ 710 | ecdsa-brainpool-twisted | unavailable | 711 +---------------------------+------------------------------------+ 712 713- ``HASH_ALG``: This build flag enables the user to select the secure hash 714 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 715 The default value of this flag is ``sha256``. 716 717- ``LDFLAGS``: Extra user options appended to the linkers' command line in 718 addition to the one set by the build system. 719 720- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 721 output compiled into the build. This should be one of the following: 722 723 :: 724 725 0 (LOG_LEVEL_NONE) 726 10 (LOG_LEVEL_ERROR) 727 20 (LOG_LEVEL_NOTICE) 728 30 (LOG_LEVEL_WARNING) 729 40 (LOG_LEVEL_INFO) 730 50 (LOG_LEVEL_VERBOSE) 731 732 All log output up to and including the selected log level is compiled into 733 the build. The default value is 40 in debug builds and 20 in release builds. 734 735- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 736 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 737 provide trust that the code taking the measurements and recording them has 738 not been tampered with. 739 740 This option defaults to 0. 741 742- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 743 options to the compiler. An example usage: 744 745 .. code:: make 746 747 MARCH_DIRECTIVE := -march=armv8.5-a 748 749- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 750 options to the compiler currently supporting only of the options. 751 GCC documentation: 752 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 753 754 An example usage: 755 756 .. code:: make 757 758 HARDEN_SLS := 1 759 760 This option defaults to 0. 761 762- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 763 specifies a file that contains the Non-Trusted World private key in PEM 764 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 765 will be used to save the key. 766 767- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 768 optional. It is only needed if the platform makefile specifies that it 769 is required in order to build the ``fwu_fip`` target. 770 771- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 772 contents upon world switch. It can take either 0 (don't save and restore) or 773 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 774 wants the timer registers to be saved and restored. 775 776- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 777 for the BL image. It can be either 0 (include) or 1 (remove). The default 778 value is 0. 779 780- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 781 the underlying hardware is not a full PL011 UART but a minimally compliant 782 generic UART, which is a subset of the PL011. The driver will not access 783 any register that is not part of the SBSA generic UART specification. 784 Default value is 0 (a full PL011 compliant UART is present). 785 786- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 787 must be subdirectory of any depth under ``plat/``, and must contain a 788 platform makefile named ``platform.mk``. For example, to build TF-A for the 789 Arm Juno board, select PLAT=juno. 790 791- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 792 each core as well as the global context. The data includes the memory used 793 by each world and each privileged exception level. This build option is 794 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 795 796- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 797 instead of the normal boot flow. When defined, it must specify the entry 798 point address for the preloaded BL33 image. This option is incompatible with 799 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 800 over ``PRELOADED_BL33_BASE``. 801 802- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 803 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 804 registers when the cluster goes through a power cycle. This is disabled by 805 default and platforms that require this feature have to enable them. 806 807- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 808 vector address can be programmed or is fixed on the platform. It can take 809 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 810 programmable reset address, it is expected that a CPU will start executing 811 code directly at the right address, both on a cold and warm reset. In this 812 case, there is no need to identify the entrypoint on boot and the boot path 813 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 814 does not need to be implemented in this case. 815 816- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 817 possible for the PSCI power-state parameter: original and extended State-ID 818 formats. This flag if set to 1, configures the generic PSCI layer to use the 819 extended format. The default value of this flag is 0, which means by default 820 the original power-state format is used by the PSCI implementation. This flag 821 should be specified by the platform makefile and it governs the return value 822 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 823 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 824 set to 1 as well. 825 826- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 827 OS-initiated mode. This option defaults to 0. 828 829- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 830 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 831 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 832 NOTE: This flag enables use of IESB capability to reduce entry latency into 833 EL3 even when RAS error handling is not performed on the platform. Hence this 834 flag is recommended to be turned on Armv8.2 and later CPUs. 835 836- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 837 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 838 entrypoint) or 1 (CPU reset to BL31 entrypoint). 839 The default value is 0. 840 841- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 842 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 843 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 844 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 845 846- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 847- blocks) covered by a single bit of the bitlock structure during RME GPT 848- operations. The lower the block size, the better opportunity for 849- parallelising GPT operations but at the cost of more bits being needed 850- for the bitlock structure. This numeric parameter can take the values 851- from 0 to 512 and must be a power of 2. The value of 0 is special and 852- and it chooses a single spinlock for all GPT L1 table entries. Default 853- value is 1 which corresponds to block size of 512MB per bit of bitlock 854- structure. 855 856- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 857 supported contiguous blocks in GPT Library. This parameter can take the 858 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 859 descriptors. Default value is 512. 860 861- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 862 file that contains the ROT private key in PEM format or a PKCS11 URI and 863 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 864 accepted and it will be used to save the key. 865 866- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 867 certificate generation tool to save the keys used to establish the Chain of 868 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 869 870- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 871 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 872 target. 873 874- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 875 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 876 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 877 878- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 879 optional. It is only needed if the platform makefile specifies that it 880 is required in order to build the ``fwu_fip`` target. 881 882- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 883 Delegated Exception Interface to BL31 image. This defaults to ``0``. 884 885 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 886 set to ``1``. 887 888- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 889 isolated on separate memory pages. This is a trade-off between security and 890 memory usage. See "Isolating code and read-only data on separate memory 891 pages" section in :ref:`Firmware Design`. This flag is disabled by default 892 and affects all BL images. 893 894- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 895 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 896 allocated in RAM discontiguous from the loaded firmware image. When set, the 897 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 898 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 899 sections are placed in RAM immediately following the loaded firmware image. 900 901- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 902 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 903 discontiguous from loaded firmware images. When set, the platform need to 904 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 905 flag is disabled by default and NOLOAD sections are placed in RAM immediately 906 following the loaded firmware image. 907 908- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 909 data structures to be put in a dedicated memory region as decided by platform 910 integrator. Default value is ``0`` which means the SIMD context is put in BSS 911 section of EL3 firmware. 912 913- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 914 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 915 UEFI+ACPI this can provide a certain amount of OS forward compatibility 916 with newer platforms that aren't ECAM compliant. 917 918- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 919 This build option is only valid if ``ARCH=aarch64``. The value should be 920 the path to the directory containing the SPD source, relative to 921 ``services/spd/``; the directory is expected to contain a makefile called 922 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 923 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 924 cannot be enabled when the ``SPM_MM`` option is enabled. 925 926- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 927 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 928 execution in BL1 just before handing over to BL31. At this point, all 929 firmware images have been loaded in memory, and the MMU and caches are 930 turned off. Refer to the "Debugging options" section for more details. 931 932- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 933 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 934 component runs at the EL3 exception level. The default value is ``0`` ( 935 disabled). This configuration supports pre-Armv8.4 platforms (aka not 936 implementing the ``FEAT_SEL2`` extension). 937 938- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 939 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 940 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 941 942- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 943 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 944 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 945 mechanism should be used. 946 947- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 948 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 949 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 950 extension. This is the default when enabling the SPM Dispatcher. When 951 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 952 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 953 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 954 extension). 955 956- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 957 Partition Manager (SPM) implementation. The default value is ``0`` 958 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 959 enabled (``SPD=spmd``). 960 961- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 962 description of secure partitions. The build system will parse this file and 963 package all secure partition blobs into the FIP. This file is not 964 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 965 966- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 967 secure interrupts (caught through the FIQ line). Platforms can enable 968 this directive if they need to handle such interruption. When enabled, 969 the FIQ are handled in monitor mode and non secure world is not allowed 970 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 971 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 972 973- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 974 Platforms can configure this if they need to lower the hardware 975 limit, for example due to asymmetric configuration or limitations of 976 software run at lower ELs. The default is the architectural maximum 977 of 2048 which should be suitable for most configurations, the 978 hardware will limit the effective VL to the maximum physically supported 979 VL. 980 981- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 982 Random Number Generator Interface to BL31 image. This defaults to ``0``. 983 984- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 985 Boot feature. When set to '1', BL1 and BL2 images include support to load 986 and verify the certificates and images in a FIP, and BL1 includes support 987 for the Firmware Update. The default value is '0'. Generation and inclusion 988 of certificates in the FIP and FWU_FIP depends upon the value of the 989 ``GENERATE_COT`` option. 990 991 .. warning:: 992 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 993 already exist in disk, they will be overwritten without further notice. 994 995- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 996 specifies a file that contains the Trusted World private key in PEM 997 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 998 it will be used to save the key. 999 1000- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1001 synchronous, (see "Initializing a BL32 Image" section in 1002 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1003 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1004 Default is 0. 1005 1006- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1007 routing model which routes non-secure interrupts asynchronously from TSP 1008 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1009 for saving and restoring the TSP context in this routing model. The 1010 default routing model (when the value is 0) is to route non-secure 1011 interrupts to TSP allowing it to save its context and hand over 1012 synchronously to EL3 via an SMC. 1013 1014 .. note:: 1015 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1016 must also be set to ``1``. 1017 1018- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1019 internal-trusted-storage) as SP in tb_fw_config device tree. 1020 1021- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1022 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1023 this delay. It can take values in the range (0-15). Default value is ``0`` 1024 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1025 Platforms need to explicitly update this value based on their requirements. 1026 1027- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1028 linker. When the ``LINKER`` build variable points to the armlink linker, 1029 this flag is enabled automatically. To enable support for armlink, platforms 1030 will have to provide a scatter file for the BL image. Currently, Tegra 1031 platforms use the armlink support to compile BL3-1 images. 1032 1033- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1034 memory region in the BL memory map or not (see "Use of Coherent memory in 1035 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1036 (Coherent memory region is included) or 0 (Coherent memory region is 1037 excluded). Default is 1. 1038 1039- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1040 firmware configuration framework. This will move the io_policies into a 1041 configuration device tree, instead of static structure in the code base. 1042 1043- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1044 at runtime using fconf. If this flag is enabled, COT descriptors are 1045 statically captured in tb_fw_config file in the form of device tree nodes 1046 and properties. Currently, COT descriptors used by BL2 are moved to the 1047 device tree and COT descriptors used by BL1 are retained in the code 1048 base statically. 1049 1050- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1051 runtime using firmware configuration framework. The platform specific SDEI 1052 shared and private events configuration is retrieved from device tree rather 1053 than static C structures at compile time. This is only supported if 1054 SDEI_SUPPORT build flag is enabled. 1055 1056- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1057 and Group1 secure interrupts using the firmware configuration framework. The 1058 platform specific secure interrupt property descriptor is retrieved from 1059 device tree in runtime rather than depending on static C structure at compile 1060 time. 1061 1062- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1063 This feature creates a library of functions to be placed in ROM and thus 1064 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1065 is 0. 1066 1067- ``V``: Verbose build. If assigned anything other than 0, the build commands 1068 are printed. Default is 0. 1069 1070- ``VERSION_STRING``: String used in the log output for each TF-A image. 1071 Defaults to a string formed by concatenating the version number, build type 1072 and build string. 1073 1074- ``W``: Warning level. Some compiler warning options of interest have been 1075 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1076 each level enabling more warning options. Default is 0. 1077 1078 This option is closely related to the ``E`` option, which enables 1079 ``-Werror``. 1080 1081 - ``W=0`` (default) 1082 1083 Enables a wide assortment of warnings, most notably ``-Wall`` and 1084 ``-Wextra``, as well as various bad practices and things that are likely to 1085 result in errors. Includes some compiler specific flags. No warnings are 1086 expected at this level for any build. 1087 1088 - ``W=1`` 1089 1090 Enables warnings we want the generic build to include but are too time 1091 consuming to fix at the moment. It re-enables warnings taken out for 1092 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1093 to eventually be merged into ``W=0``. Some warnings are expected on some 1094 builds, but new contributions should not introduce new ones. 1095 1096 - ``W=2`` (recommended) 1097 1098 Enables warnings we want the generic build to include but cannot be enabled 1099 due to external libraries. This level is expected to eventually be merged 1100 into ``W=0``. Lots of warnings are expected, primarily from external 1101 libraries like zlib and compiler-rt, but new controbutions should not 1102 introduce new ones. 1103 1104 - ``W=3`` 1105 1106 Enables warnings that are informative but not necessary and generally too 1107 verbose and frequently ignored. A very large number of warnings are 1108 expected. 1109 1110 The exact set of warning flags depends on the compiler and TF-A warning 1111 level, however they are all succinctly set in the top-level Makefile. Please 1112 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1113 individual flags. 1114 1115- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1116 the CPU after warm boot. This is applicable for platforms which do not 1117 require interconnect programming to enable cache coherency (eg: single 1118 cluster platforms). If this option is enabled, then warm boot path 1119 enables D-caches immediately after enabling MMU. This option defaults to 0. 1120 1121- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1122 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1123 default value of this flag is ``no``. Note this option must be enabled only 1124 for ARM architecture greater than Armv8.5-A. 1125 1126- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1127 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1128 The default value of this flag is ``0``. 1129 1130 ``AT`` speculative errata workaround disables stage1 page table walk for 1131 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1132 produces either the correct result or failure without TLB allocation. 1133 1134 This boolean option enables errata for all below CPUs. 1135 1136 +---------+--------------+-------------------------+ 1137 | Errata | CPU | Workaround Define | 1138 +=========+==============+=========================+ 1139 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1140 +---------+--------------+-------------------------+ 1141 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1142 +---------+--------------+-------------------------+ 1143 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1144 +---------+--------------+-------------------------+ 1145 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1146 +---------+--------------+-------------------------+ 1147 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1148 +---------+--------------+-------------------------+ 1149 1150 .. note:: 1151 This option is enabled by build only if platform sets any of above defines 1152 mentioned in ’Workaround Define' column in the table. 1153 If this option is enabled for the EL3 software then EL2 software also must 1154 implement this workaround due to the behaviour of the errata mentioned 1155 in new SDEN document which will get published soon. 1156 1157- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1158 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1159 This flag is disabled by default. 1160 1161- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1162 host machine where a custom installation of OpenSSL is located, which is used 1163 to build the certificate generation, firmware encryption and FIP tools. If 1164 this option is not set, the default OS installation will be used. 1165 1166- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1167 functions that wait for an arbitrary time length (udelay and mdelay). The 1168 default value is 0. 1169 1170- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1171 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1172 optional architectural feature for AArch64. This flag can take the values 1173 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1174 and it is automatically disabled when the target architecture is AArch32. 1175 1176- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1177 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1178 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1179 feature for AArch64. This flag can take the values 0 to 2, to align with the 1180 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1181 disabled when the target architecture is AArch32. 1182 1183- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1184 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1185 but unused). This feature is available if trace unit such as ETMv4.x, and 1186 ETE(extending ETM feature) is implemented. This flag can take the values 1187 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1188 1189- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1190 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1191 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1192 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1193 1194- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1195 ``plat_can_cmo`` which will return zero if cache management operations should 1196 be skipped and non-zero otherwise. By default, this option is disabled which 1197 means platform hook won't be checked and CMOs will always be performed when 1198 related functions are called. 1199 1200- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1201 firmware interface for the BL31 image. By default its disabled (``0``). 1202 1203- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1204 errata mitigation for platforms with a non-arm interconnect using the errata 1205 ABI. By default its disabled (``0``). 1206 1207- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1208 driver(s). By default it is disabled (``0``) because it constitutes an attack 1209 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1210 This option should only be enabled on a need basis if there is a use case for 1211 reading characters from the console. 1212 1213GICv3 driver options 1214-------------------- 1215 1216GICv3 driver files are included using directive: 1217 1218``include drivers/arm/gic/v3/gicv3.mk`` 1219 1220The driver can be configured with the following options set in the platform 1221makefile: 1222 1223- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1224 Enabling this option will add runtime detection support for the 1225 GIC-600, so is safe to select even for a GIC500 implementation. 1226 This option defaults to 0. 1227 1228- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1229 for GIC-600 AE. Enabling this option will introduce support to initialize 1230 the FMU. Platforms should call the init function during boot to enable the 1231 FMU and its safety mechanisms. This option defaults to 0. 1232 1233- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1234 functionality. This option defaults to 0 1235 1236- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1237 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1238 functions. This is required for FVP platform which need to simulate GIC save 1239 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1240 1241- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1242 This option defaults to 0. 1243 1244- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1245 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1246 1247Debugging options 1248----------------- 1249 1250To compile a debug version and make the build more verbose use 1251 1252.. code:: shell 1253 1254 make PLAT=<platform> DEBUG=1 V=1 all 1255 1256AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1257(for example Arm-DS) might not support this and may need an older version of 1258DWARF symbols to be emitted by GCC. This can be achieved by using the 1259``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1260the version to 4 is recommended for Arm-DS. 1261 1262When debugging logic problems it might also be useful to disable all compiler 1263optimizations by using ``-O0``. 1264 1265.. warning:: 1266 Using ``-O0`` could cause output images to be larger and base addresses 1267 might need to be recalculated (see the **Memory layout on Arm development 1268 platforms** section in the :ref:`Firmware Design`). 1269 1270Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1271``LDFLAGS``: 1272 1273.. code:: shell 1274 1275 CFLAGS='-O0 -gdwarf-2' \ 1276 make PLAT=<platform> DEBUG=1 V=1 all 1277 1278Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1279ignored as the linker is called directly. 1280 1281It is also possible to introduce an infinite loop to help in debugging the 1282post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1283``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1284section. In this case, the developer may take control of the target using a 1285debugger when indicated by the console output. When using Arm-DS, the following 1286commands can be used: 1287 1288:: 1289 1290 # Stop target execution 1291 interrupt 1292 1293 # 1294 # Prepare your debugging environment, e.g. set breakpoints 1295 # 1296 1297 # Jump over the debug loop 1298 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1299 1300 # Resume execution 1301 continue 1302 1303.. _build_options_experimental: 1304 1305Experimental build options 1306--------------------------- 1307 1308Common build options 1309~~~~~~~~~~~~~~~~~~~~ 1310 1311- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1312 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1313 set to ``1`` then measurements and additional metadata collected during the 1314 measured boot process are sent to the DICE Protection Environment for storage 1315 and processing. A certificate chain, which represents the boot state of the 1316 device, can be queried from the DPE. 1317 1318- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1319 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1320 the measurements and recording them as per `PSA DRTM specification`_. For 1321 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1322 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1323 should have mechanism to authenticate BL31. This option defaults to 0. 1324 1325- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1326 Management Extension. This flag can take the values 0 to 2, to align with 1327 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1328 1329- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1330 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1331 registers so are enabled together. Using this option without 1332 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1333 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1334 superset of SVE. SME is an optional architectural feature for AArch64. 1335 At this time, this build option cannot be used on systems that have 1336 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1337 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1338 mechanism. Default is 0. 1339 1340- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1341 version 2 (SME2) for the non-secure world only. SME2 is an optional 1342 architectural feature for AArch64. 1343 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1344 accesses will still be trapped. This flag can take the values 0 to 2, to 1345 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1346 1347- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1348 Extension for secure world. Used along with SVE and FPU/SIMD. 1349 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1350 Default is 0. 1351 1352- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1353 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1354 for logical partitions in EL3, managed by the SPMD as defined in the 1355 FF-A v1.2 specification. This flag is disabled by default. This flag 1356 must not be used if ``SPMC_AT_EL3`` is enabled. 1357 1358- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1359 verification mechanism. This is a debug feature that compares the 1360 architectural features enabled through the feature specific build flags 1361 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1362 and reports any discrepancies. 1363 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1364 1365 It is expected that this feature is only used for flexible platforms like 1366 software emulators, or for hardware platforms at bringup time, to verify 1367 that the configured feature set matches the CPU. 1368 The ``FEATURE_DETECTION`` macro is disabled by default. 1369 1370- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1371 The platform will use PSA compliant Crypto APIs during authentication and 1372 image measurement process by enabling this option. It uses APIs defined as 1373 per the `PSA Crypto API specification`_. This feature is only supported if 1374 using MbedTLS 3.x version. It is disabled (``0``) by default. 1375 1376- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1377 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1378 This defaults to ``0``. Current implementation follows the Firmware Handoff 1379 specification v0.9. 1380 1381- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1382 interface through BL31 as a SiP SMC function. 1383 Default is disabled (0). 1384 1385Firmware update options 1386~~~~~~~~~~~~~~~~~~~~~~~ 1387 1388- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1389 `PSA FW update specification`_. The default value is 0. 1390 PSA firmware update implementation has few limitations, such as: 1391 1392 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1393 be updated, then it should be done through another platform-defined 1394 mechanism. 1395 1396 - It assumes the platform's hardware supports CRC32 instructions. 1397 1398- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1399 in defining the firmware update metadata structure. This flag is by default 1400 set to '2'. 1401 1402- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1403 firmware bank. Each firmware bank must have the same number of images as per 1404 the `PSA FW update specification`_. 1405 This flag is used in defining the firmware update metadata structure. This 1406 flag is by default set to '1'. 1407 1408- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1409 metadata contains image description. The default value is 1. 1410 1411 The version 2 of the FWU metadata allows for an opaque metadata 1412 structure where a platform can choose to not include the firmware 1413 store description in the metadata structure. This option indicates 1414 if the firmware store description, which provides information on 1415 the updatable images is part of the structure. 1416 1417-------------- 1418 1419*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1420 1421.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1422.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1423.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1424.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1425.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1426.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1427.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1428