1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sys_reg_trace.h> 37 #include <lib/extensions/trbe.h> 38 #include <lib/extensions/trf.h> 39 #include <lib/utils.h> 40 41 #if ENABLE_FEAT_TWED 42 /* Make sure delay value fits within the range(0-15) */ 43 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 44 #endif /* ENABLE_FEAT_TWED */ 45 46 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 47 static bool has_secure_perworld_init; 48 49 static void manage_extensions_common(cpu_context_t *ctx); 50 static void manage_extensions_nonsecure(cpu_context_t *ctx); 51 static void manage_extensions_secure(cpu_context_t *ctx); 52 static void manage_extensions_secure_per_world(void); 53 54 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 55 { 56 u_register_t sctlr_elx, actlr_elx; 57 58 /* 59 * Initialise SCTLR_EL1 to the reset value corresponding to the target 60 * execution state setting all fields rather than relying on the hw. 61 * Some fields have architecturally UNKNOWN reset values and these are 62 * set to zero. 63 * 64 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 65 * 66 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 67 * required by PSCI specification) 68 */ 69 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 70 if (GET_RW(ep->spsr) == MODE_RW_64) { 71 sctlr_elx |= SCTLR_EL1_RES1; 72 } else { 73 /* 74 * If the target execution state is AArch32 then the following 75 * fields need to be set. 76 * 77 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 78 * instructions are not trapped to EL1. 79 * 80 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 84 * CP15DMB, CP15DSB, and CP15ISB instructions. 85 */ 86 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 87 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 88 } 89 90 #if ERRATA_A75_764081 91 /* 92 * If workaround of errata 764081 for Cortex-A75 is used then set 93 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 94 */ 95 sctlr_elx |= SCTLR_IESB_BIT; 96 #endif 97 98 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 99 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 100 101 /* 102 * Base the context ACTLR_EL1 on the current value, as it is 103 * implementation defined. The context restore process will write 104 * the value from the context to the actual register and can cause 105 * problems for processor cores that don't expect certain bits to 106 * be zero. 107 */ 108 actlr_elx = read_actlr_el1(); 109 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 110 } 111 112 /****************************************************************************** 113 * This function performs initializations that are specific to SECURE state 114 * and updates the cpu context specified by 'ctx'. 115 *****************************************************************************/ 116 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 117 { 118 u_register_t scr_el3; 119 el3_state_t *state; 120 121 state = get_el3state_ctx(ctx); 122 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 123 124 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 125 /* 126 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 127 * indicated by the interrupt routing model for BL31. 128 */ 129 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 130 #endif 131 132 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 133 if (is_feat_mte2_supported()) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 137 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 138 139 /* 140 * Initialize EL1 context registers unless SPMC is running 141 * at S-EL2. 142 */ 143 #if !SPMD_SPM_AT_SEL2 144 setup_el1_context(ctx, ep); 145 #endif 146 147 manage_extensions_secure(ctx); 148 149 /** 150 * manage_extensions_secure_per_world api has to be executed once, 151 * as the registers getting initialised, maintain constant value across 152 * all the cpus for the secure world. 153 * Henceforth, this check ensures that the registers are initialised once 154 * and avoids re-initialization from multiple cores. 155 */ 156 if (!has_secure_perworld_init) { 157 manage_extensions_secure_per_world(); 158 } 159 160 } 161 162 #if ENABLE_RME 163 /****************************************************************************** 164 * This function performs initializations that are specific to REALM state 165 * and updates the cpu context specified by 'ctx'. 166 *****************************************************************************/ 167 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 168 { 169 u_register_t scr_el3; 170 el3_state_t *state; 171 172 state = get_el3state_ctx(ctx); 173 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 174 175 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 176 177 /* CSV2 version 2 and above */ 178 if (is_feat_csv2_2_supported()) { 179 /* Enable access to the SCXTNUM_ELx registers. */ 180 scr_el3 |= SCR_EnSCXT_BIT; 181 } 182 183 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 184 } 185 #endif /* ENABLE_RME */ 186 187 /****************************************************************************** 188 * This function performs initializations that are specific to NON-SECURE state 189 * and updates the cpu context specified by 'ctx'. 190 *****************************************************************************/ 191 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 192 { 193 u_register_t scr_el3; 194 el3_state_t *state; 195 196 state = get_el3state_ctx(ctx); 197 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 198 199 /* SCR_NS: Set the NS bit */ 200 scr_el3 |= SCR_NS_BIT; 201 202 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 203 if (is_feat_mte2_supported()) { 204 scr_el3 |= SCR_ATA_BIT; 205 } 206 207 #if !CTX_INCLUDE_PAUTH_REGS 208 /* 209 * Pointer Authentication feature, if present, is always enabled by default 210 * for Non secure lower exception levels. We do not have an explicit 211 * flag to set it. 212 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 213 * exception levels of secure and realm worlds. 214 * 215 * To prevent the leakage between the worlds during world switch, 216 * we enable it only for the non-secure world. 217 * 218 * If the Secure/realm world wants to use pointer authentication, 219 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 220 * it will be enabled globally for all the contexts. 221 * 222 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 223 * other than EL3 224 * 225 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 226 * than EL3 227 */ 228 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 229 230 #endif /* CTX_INCLUDE_PAUTH_REGS */ 231 232 #if HANDLE_EA_EL3_FIRST_NS 233 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 234 scr_el3 |= SCR_EA_BIT; 235 #endif 236 237 #if RAS_TRAP_NS_ERR_REC_ACCESS 238 /* 239 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 240 * and RAS ERX registers from EL1 and EL2(from any security state) 241 * are trapped to EL3. 242 * Set here to trap only for NS EL1/EL2 243 * 244 */ 245 scr_el3 |= SCR_TERR_BIT; 246 #endif 247 248 /* CSV2 version 2 and above */ 249 if (is_feat_csv2_2_supported()) { 250 /* Enable access to the SCXTNUM_ELx registers. */ 251 scr_el3 |= SCR_EnSCXT_BIT; 252 } 253 254 #ifdef IMAGE_BL31 255 /* 256 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 257 * indicated by the interrupt routing model for BL31. 258 */ 259 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 260 #endif 261 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 262 263 /* Initialize EL1 context registers */ 264 setup_el1_context(ctx, ep); 265 266 /* Initialize EL2 context registers */ 267 #if CTX_INCLUDE_EL2_REGS 268 269 /* 270 * Initialize SCTLR_EL2 context register with reset value. 271 */ 272 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 273 274 if (is_feat_hcx_supported()) { 275 /* 276 * Initialize register HCRX_EL2 with its init value. 277 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 278 * chance that this can lead to unexpected behavior in lower 279 * ELs that have not been updated since the introduction of 280 * this feature if not properly initialized, especially when 281 * it comes to those bits that enable/disable traps. 282 */ 283 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 284 HCRX_EL2_INIT_VAL); 285 } 286 287 if (is_feat_fgt_supported()) { 288 /* 289 * Initialize HFG*_EL2 registers with a default value so legacy 290 * systems unaware of FEAT_FGT do not get trapped due to their lack 291 * of initialization for this feature. 292 */ 293 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 294 HFGITR_EL2_INIT_VAL); 295 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 296 HFGRTR_EL2_INIT_VAL); 297 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 298 HFGWTR_EL2_INIT_VAL); 299 } 300 301 #endif /* CTX_INCLUDE_EL2_REGS */ 302 303 manage_extensions_nonsecure(ctx); 304 } 305 306 /******************************************************************************* 307 * The following function performs initialization of the cpu_context 'ctx' 308 * for first use that is common to all security states, and sets the 309 * initial entrypoint state as specified by the entry_point_info structure. 310 * 311 * The EE and ST attributes are used to configure the endianness and secure 312 * timer availability for the new execution context. 313 ******************************************************************************/ 314 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 315 { 316 u_register_t scr_el3; 317 u_register_t mdcr_el3; 318 el3_state_t *state; 319 gp_regs_t *gp_regs; 320 321 state = get_el3state_ctx(ctx); 322 323 /* Clear any residual register values from the context */ 324 zeromem(ctx, sizeof(*ctx)); 325 326 /* 327 * The lower-EL context is zeroed so that no stale values leak to a world. 328 * It is assumed that an all-zero lower-EL context is good enough for it 329 * to boot correctly. However, there are very few registers where this 330 * is not true and some values need to be recreated. 331 */ 332 #if CTX_INCLUDE_EL2_REGS 333 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 334 335 /* 336 * These bits are set in the gicv3 driver. Losing them (especially the 337 * SRE bit) is problematic for all worlds. Henceforth recreate them. 338 */ 339 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 340 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 341 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 342 343 /* 344 * The actlr_el2 register can be initialized in platform's reset handler 345 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 346 */ 347 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 348 #endif /* CTX_INCLUDE_EL2_REGS */ 349 350 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 351 scr_el3 = SCR_RESET_VAL; 352 353 /* 354 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 355 * EL2, EL1 and EL0 are not trapped to EL3. 356 * 357 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 358 * EL2, EL1 and EL0 are not trapped to EL3. 359 * 360 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 361 * both Security states and both Execution states. 362 * 363 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 364 * Non-secure memory. 365 */ 366 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 367 368 scr_el3 |= SCR_SIF_BIT; 369 370 /* 371 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 372 * Exception level as specified by SPSR. 373 */ 374 if (GET_RW(ep->spsr) == MODE_RW_64) { 375 scr_el3 |= SCR_RW_BIT; 376 } 377 378 /* 379 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 380 * Secure timer registers to EL3, from AArch64 state only, if specified 381 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 382 * bit always behaves as 1 (i.e. secure physical timer register access 383 * is not trapped) 384 */ 385 if (EP_GET_ST(ep->h.attr) != 0U) { 386 scr_el3 |= SCR_ST_BIT; 387 } 388 389 /* 390 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 391 * SCR_EL3.HXEn. 392 */ 393 if (is_feat_hcx_supported()) { 394 scr_el3 |= SCR_HXEn_BIT; 395 } 396 397 /* 398 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 399 * registers are trapped to EL3. 400 */ 401 #if ENABLE_FEAT_RNG_TRAP 402 scr_el3 |= SCR_TRNDR_BIT; 403 #endif 404 405 #if FAULT_INJECTION_SUPPORT 406 /* Enable fault injection from lower ELs */ 407 scr_el3 |= SCR_FIEN_BIT; 408 #endif 409 410 #if CTX_INCLUDE_PAUTH_REGS 411 /* 412 * Enable Pointer Authentication globally for all the worlds. 413 * 414 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 415 * other than EL3 416 * 417 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 418 * than EL3 419 */ 420 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 421 #endif /* CTX_INCLUDE_PAUTH_REGS */ 422 423 /* 424 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 425 */ 426 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 427 scr_el3 |= SCR_TCR2EN_BIT; 428 } 429 430 /* 431 * SCR_EL3.PIEN: Enable permission indirection and overlay 432 * registers for AArch64 if present. 433 */ 434 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 435 scr_el3 |= SCR_PIEN_BIT; 436 } 437 438 /* 439 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 440 */ 441 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 442 scr_el3 |= SCR_GCSEn_BIT; 443 } 444 445 /* 446 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 447 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 448 * next mode is Hyp. 449 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 450 * same conditions as HVC instructions and when the processor supports 451 * ARMv8.6-FGT. 452 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 453 * CNTPOFF_EL2 register under the same conditions as HVC instructions 454 * and when the processor supports ECV. 455 */ 456 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 457 || ((GET_RW(ep->spsr) != MODE_RW_64) 458 && (GET_M32(ep->spsr) == MODE32_hyp))) { 459 scr_el3 |= SCR_HCE_BIT; 460 461 if (is_feat_fgt_supported()) { 462 scr_el3 |= SCR_FGTEN_BIT; 463 } 464 465 if (is_feat_ecv_supported()) { 466 scr_el3 |= SCR_ECVEN_BIT; 467 } 468 } 469 470 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 471 if (is_feat_twed_supported()) { 472 /* Set delay in SCR_EL3 */ 473 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 474 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 475 << SCR_TWEDEL_SHIFT); 476 477 /* Enable WFE delay */ 478 scr_el3 |= SCR_TWEDEn_BIT; 479 } 480 481 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 482 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 483 if (is_feat_sel2_supported()) { 484 scr_el3 |= SCR_EEL2_BIT; 485 } 486 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 487 488 /* 489 * Populate EL3 state so that we've the right context 490 * before doing ERET 491 */ 492 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 493 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 494 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 495 496 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 497 mdcr_el3 = MDCR_EL3_RESET_VAL; 498 499 /* --------------------------------------------------------------------- 500 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 501 * Some fields are architecturally UNKNOWN on reset. 502 * 503 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 504 * Debug exceptions, other than Breakpoint Instruction exceptions, are 505 * disabled from all ELs in Secure state. 506 * 507 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 508 * privileged debug from S-EL1. 509 * 510 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 511 * access to the powerdown debug registers do not trap to EL3. 512 * 513 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 514 * debug registers, other than those registers that are controlled by 515 * MDCR_EL3.TDOSA. 516 */ 517 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 518 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 519 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 520 521 /* 522 * Configure MDCR_EL3 register as applicable for each world 523 * (NS/Secure/Realm) context. 524 */ 525 manage_extensions_common(ctx); 526 527 /* 528 * Store the X0-X7 value from the entrypoint into the context 529 * Use memcpy as we are in control of the layout of the structures 530 */ 531 gp_regs = get_gpregs_ctx(ctx); 532 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 533 } 534 535 /******************************************************************************* 536 * Context management library initialization routine. This library is used by 537 * runtime services to share pointers to 'cpu_context' structures for secure 538 * non-secure and realm states. Management of the structures and their associated 539 * memory is not done by the context management library e.g. the PSCI service 540 * manages the cpu context used for entry from and exit to the non-secure state. 541 * The Secure payload dispatcher service manages the context(s) corresponding to 542 * the secure state. It also uses this library to get access to the non-secure 543 * state cpu context pointers. 544 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 545 * which will be used for programming an entry into a lower EL. The same context 546 * will be used to save state upon exception entry from that EL. 547 ******************************************************************************/ 548 void __init cm_init(void) 549 { 550 /* 551 * The context management library has only global data to initialize, but 552 * that will be done when the BSS is zeroed out. 553 */ 554 } 555 556 /******************************************************************************* 557 * This is the high-level function used to initialize the cpu_context 'ctx' for 558 * first use. It performs initializations that are common to all security states 559 * and initializations specific to the security state specified in 'ep' 560 ******************************************************************************/ 561 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 562 { 563 unsigned int security_state; 564 565 assert(ctx != NULL); 566 567 /* 568 * Perform initializations that are common 569 * to all security states 570 */ 571 setup_context_common(ctx, ep); 572 573 security_state = GET_SECURITY_STATE(ep->h.attr); 574 575 /* Perform security state specific initializations */ 576 switch (security_state) { 577 case SECURE: 578 setup_secure_context(ctx, ep); 579 break; 580 #if ENABLE_RME 581 case REALM: 582 setup_realm_context(ctx, ep); 583 break; 584 #endif 585 case NON_SECURE: 586 setup_ns_context(ctx, ep); 587 break; 588 default: 589 ERROR("Invalid security state\n"); 590 panic(); 591 break; 592 } 593 } 594 595 /******************************************************************************* 596 * Enable architecture extensions for EL3 execution. This function only updates 597 * registers in-place which are expected to either never change or be 598 * overwritten by el3_exit. 599 ******************************************************************************/ 600 #if IMAGE_BL31 601 void cm_manage_extensions_el3(void) 602 { 603 if (is_feat_amu_supported()) { 604 amu_init_el3(); 605 } 606 607 if (is_feat_sme_supported()) { 608 sme_init_el3(); 609 } 610 611 pmuv3_init_el3(); 612 } 613 #endif /* IMAGE_BL31 */ 614 615 /****************************************************************************** 616 * Function to initialise the registers with the RESET values in the context 617 * memory, which are maintained per world. 618 ******************************************************************************/ 619 #if IMAGE_BL31 620 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 621 { 622 /* 623 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 624 * 625 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 626 * by Advanced SIMD, floating-point or SVE instructions (if 627 * implemented) do not trap to EL3. 628 * 629 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 630 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 631 */ 632 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 633 634 per_world_ctx->ctx_cptr_el3 = cptr_el3; 635 636 /* 637 * Initialize MPAM3_EL3 to its default reset value 638 * 639 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 640 * all lower ELn MPAM3_EL3 register access to, trap to EL3 641 */ 642 643 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 644 } 645 #endif /* IMAGE_BL31 */ 646 647 /******************************************************************************* 648 * Initialise per_world_context for Non-Secure world. 649 * This function enables the architecture extensions, which have same value 650 * across the cores for the non-secure world. 651 ******************************************************************************/ 652 #if IMAGE_BL31 653 void manage_extensions_nonsecure_per_world(void) 654 { 655 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 656 657 if (is_feat_sme_supported()) { 658 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 659 } 660 661 if (is_feat_sve_supported()) { 662 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 663 } 664 665 if (is_feat_amu_supported()) { 666 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 667 } 668 669 if (is_feat_sys_reg_trace_supported()) { 670 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 671 } 672 673 if (is_feat_mpam_supported()) { 674 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 675 } 676 } 677 #endif /* IMAGE_BL31 */ 678 679 /******************************************************************************* 680 * Initialise per_world_context for Secure world. 681 * This function enables the architecture extensions, which have same value 682 * across the cores for the secure world. 683 ******************************************************************************/ 684 static void manage_extensions_secure_per_world(void) 685 { 686 #if IMAGE_BL31 687 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 688 689 if (is_feat_sme_supported()) { 690 691 if (ENABLE_SME_FOR_SWD) { 692 /* 693 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 694 * SME, SVE, and FPU/SIMD context properly managed. 695 */ 696 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 697 } else { 698 /* 699 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 700 * world can safely use the associated registers. 701 */ 702 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 703 } 704 } 705 if (is_feat_sve_supported()) { 706 if (ENABLE_SVE_FOR_SWD) { 707 /* 708 * Enable SVE and FPU in secure context, SPM must ensure 709 * that the SVE and FPU register contexts are properly managed. 710 */ 711 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 712 } else { 713 /* 714 * Disable SVE and FPU in secure context so non-secure world 715 * can safely use them. 716 */ 717 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 718 } 719 } 720 721 /* NS can access this but Secure shouldn't */ 722 if (is_feat_sys_reg_trace_supported()) { 723 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 724 } 725 726 has_secure_perworld_init = true; 727 #endif /* IMAGE_BL31 */ 728 } 729 730 /******************************************************************************* 731 * Enable architecture extensions on first entry to Non-secure world only 732 * and disable for secure world. 733 * 734 * NOTE: Arch features which have been provided with the capability of getting 735 * enabled only for non-secure world and being disabled for secure world are 736 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 737 ******************************************************************************/ 738 static void manage_extensions_common(cpu_context_t *ctx) 739 { 740 #if IMAGE_BL31 741 if (is_feat_spe_supported()) { 742 /* 743 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 744 */ 745 spe_enable(ctx); 746 } 747 748 if (is_feat_trbe_supported()) { 749 /* 750 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 751 * Realm state. 752 */ 753 trbe_enable(ctx); 754 } 755 756 if (is_feat_trf_supported()) { 757 /* 758 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 759 */ 760 trf_enable(ctx); 761 } 762 763 if (is_feat_brbe_supported()) { 764 /* 765 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 766 */ 767 brbe_enable(ctx); 768 } 769 #endif /* IMAGE_BL31 */ 770 } 771 772 /******************************************************************************* 773 * Enable architecture extensions on first entry to Non-secure world. 774 ******************************************************************************/ 775 static void manage_extensions_nonsecure(cpu_context_t *ctx) 776 { 777 #if IMAGE_BL31 778 if (is_feat_amu_supported()) { 779 amu_enable(ctx); 780 } 781 782 if (is_feat_sme_supported()) { 783 sme_enable(ctx); 784 } 785 786 if (is_feat_fgt2_supported()) { 787 fgt2_enable(ctx); 788 } 789 790 if (is_feat_debugv8p9_supported()) { 791 debugv8p9_extended_bp_wp_enable(ctx); 792 } 793 794 pmuv3_enable(ctx); 795 #endif /* IMAGE_BL31 */ 796 } 797 798 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 799 static __unused void enable_pauth_el2(void) 800 { 801 u_register_t hcr_el2 = read_hcr_el2(); 802 /* 803 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 804 * accessing key registers or using pointer authentication instructions 805 * from lower ELs. 806 */ 807 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 808 809 write_hcr_el2(hcr_el2); 810 } 811 812 #if INIT_UNUSED_NS_EL2 813 /******************************************************************************* 814 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 815 * world when EL2 is empty and unused. 816 ******************************************************************************/ 817 static void manage_extensions_nonsecure_el2_unused(void) 818 { 819 #if IMAGE_BL31 820 if (is_feat_spe_supported()) { 821 spe_init_el2_unused(); 822 } 823 824 if (is_feat_amu_supported()) { 825 amu_init_el2_unused(); 826 } 827 828 if (is_feat_mpam_supported()) { 829 mpam_init_el2_unused(); 830 } 831 832 if (is_feat_trbe_supported()) { 833 trbe_init_el2_unused(); 834 } 835 836 if (is_feat_sys_reg_trace_supported()) { 837 sys_reg_trace_init_el2_unused(); 838 } 839 840 if (is_feat_trf_supported()) { 841 trf_init_el2_unused(); 842 } 843 844 pmuv3_init_el2_unused(); 845 846 if (is_feat_sve_supported()) { 847 sve_init_el2_unused(); 848 } 849 850 if (is_feat_sme_supported()) { 851 sme_init_el2_unused(); 852 } 853 854 #if ENABLE_PAUTH 855 enable_pauth_el2(); 856 #endif /* ENABLE_PAUTH */ 857 #endif /* IMAGE_BL31 */ 858 } 859 #endif /* INIT_UNUSED_NS_EL2 */ 860 861 /******************************************************************************* 862 * Enable architecture extensions on first entry to Secure world. 863 ******************************************************************************/ 864 static void manage_extensions_secure(cpu_context_t *ctx) 865 { 866 #if IMAGE_BL31 867 if (is_feat_sme_supported()) { 868 if (ENABLE_SME_FOR_SWD) { 869 /* 870 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 871 * must ensure SME, SVE, and FPU/SIMD context properly managed. 872 */ 873 sme_init_el3(); 874 sme_enable(ctx); 875 } else { 876 /* 877 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 878 * world can safely use the associated registers. 879 */ 880 sme_disable(ctx); 881 } 882 } 883 #endif /* IMAGE_BL31 */ 884 } 885 886 #if !IMAGE_BL1 887 /******************************************************************************* 888 * The following function initializes the cpu_context for a CPU specified by 889 * its `cpu_idx` for first use, and sets the initial entrypoint state as 890 * specified by the entry_point_info structure. 891 ******************************************************************************/ 892 void cm_init_context_by_index(unsigned int cpu_idx, 893 const entry_point_info_t *ep) 894 { 895 cpu_context_t *ctx; 896 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 897 cm_setup_context(ctx, ep); 898 } 899 #endif /* !IMAGE_BL1 */ 900 901 /******************************************************************************* 902 * The following function initializes the cpu_context for the current CPU 903 * for first use, and sets the initial entrypoint state as specified by the 904 * entry_point_info structure. 905 ******************************************************************************/ 906 void cm_init_my_context(const entry_point_info_t *ep) 907 { 908 cpu_context_t *ctx; 909 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 910 cm_setup_context(ctx, ep); 911 } 912 913 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 914 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 915 { 916 #if INIT_UNUSED_NS_EL2 917 u_register_t hcr_el2 = HCR_RESET_VAL; 918 u_register_t mdcr_el2; 919 u_register_t scr_el3; 920 921 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 922 923 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 924 if ((scr_el3 & SCR_RW_BIT) != 0U) { 925 hcr_el2 |= HCR_RW_BIT; 926 } 927 928 write_hcr_el2(hcr_el2); 929 930 /* 931 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 932 * All fields have architecturally UNKNOWN reset values. 933 */ 934 write_cptr_el2(CPTR_EL2_RESET_VAL); 935 936 /* 937 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 938 * reset and are set to zero except for field(s) listed below. 939 * 940 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 941 * Non-secure EL0 and EL1 accesses to the physical timer registers. 942 * 943 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 944 * Non-secure EL0 and EL1 accesses to the physical counter registers. 945 */ 946 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 947 948 /* 949 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 950 * UNKNOWN value. 951 */ 952 write_cntvoff_el2(0); 953 954 /* 955 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 956 * respectively. 957 */ 958 write_vpidr_el2(read_midr_el1()); 959 write_vmpidr_el2(read_mpidr_el1()); 960 961 /* 962 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 963 * 964 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 965 * translation is disabled, cache maintenance operations depend on the 966 * VMID. 967 * 968 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 969 * disabled. 970 */ 971 write_vttbr_el2(VTTBR_RESET_VAL & 972 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 973 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 974 975 /* 976 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 977 * Some fields are architecturally UNKNOWN on reset. 978 * 979 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 980 * register accesses to the Debug ROM registers are not trapped to EL2. 981 * 982 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 983 * accesses to the powerdown debug registers are not trapped to EL2. 984 * 985 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 986 * debug registers do not trap to EL2. 987 * 988 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 989 * EL2. 990 */ 991 mdcr_el2 = MDCR_EL2_RESET_VAL & 992 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 993 MDCR_EL2_TDE_BIT); 994 995 write_mdcr_el2(mdcr_el2); 996 997 /* 998 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 999 * 1000 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1001 * EL1 accesses to System registers do not trap to EL2. 1002 */ 1003 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1004 1005 /* 1006 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1007 * reset. 1008 * 1009 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1010 * and prevent timer interrupts. 1011 */ 1012 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1013 1014 manage_extensions_nonsecure_el2_unused(); 1015 #endif /* INIT_UNUSED_NS_EL2 */ 1016 } 1017 1018 /******************************************************************************* 1019 * Prepare the CPU system registers for first entry into realm, secure, or 1020 * normal world. 1021 * 1022 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1023 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1024 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1025 * For all entries, the EL1 registers are initialized from the cpu_context 1026 ******************************************************************************/ 1027 void cm_prepare_el3_exit(uint32_t security_state) 1028 { 1029 u_register_t sctlr_el2, scr_el3; 1030 cpu_context_t *ctx = cm_get_context(security_state); 1031 1032 assert(ctx != NULL); 1033 1034 if (security_state == NON_SECURE) { 1035 uint64_t el2_implemented = el_implemented(2); 1036 1037 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1038 CTX_SCR_EL3); 1039 1040 if (el2_implemented != EL_IMPL_NONE) { 1041 1042 /* 1043 * If context is not being used for EL2, initialize 1044 * HCRX_EL2 with its init value here. 1045 */ 1046 if (is_feat_hcx_supported()) { 1047 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1048 } 1049 1050 /* 1051 * Initialize Fine-grained trap registers introduced 1052 * by FEAT_FGT so all traps are initially disabled when 1053 * switching to EL2 or a lower EL, preventing undesired 1054 * behavior. 1055 */ 1056 if (is_feat_fgt_supported()) { 1057 /* 1058 * Initialize HFG*_EL2 registers with a default 1059 * value so legacy systems unaware of FEAT_FGT 1060 * do not get trapped due to their lack of 1061 * initialization for this feature. 1062 */ 1063 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1064 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1065 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1066 } 1067 1068 /* Condition to ensure EL2 is being used. */ 1069 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1070 /* Initialize SCTLR_EL2 register with reset value. */ 1071 sctlr_el2 = SCTLR_EL2_RES1; 1072 #if ERRATA_A75_764081 1073 /* 1074 * If workaround of errata 764081 for Cortex-A75 1075 * is used then set SCTLR_EL2.IESB to enable 1076 * Implicit Error Synchronization Barrier. 1077 */ 1078 sctlr_el2 |= SCTLR_IESB_BIT; 1079 #endif 1080 write_sctlr_el2(sctlr_el2); 1081 } else { 1082 /* 1083 * (scr_el3 & SCR_HCE_BIT==0) 1084 * EL2 implemented but unused. 1085 */ 1086 init_nonsecure_el2_unused(ctx); 1087 } 1088 } 1089 } 1090 cm_el1_sysregs_context_restore(security_state); 1091 cm_set_next_eret_context(security_state); 1092 } 1093 1094 #if CTX_INCLUDE_EL2_REGS 1095 1096 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1097 { 1098 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1099 if (is_feat_amu_supported()) { 1100 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1101 } 1102 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1103 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1104 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1105 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1106 } 1107 1108 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1109 { 1110 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1111 if (is_feat_amu_supported()) { 1112 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1113 } 1114 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1115 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1116 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1117 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1118 } 1119 1120 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1121 { 1122 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1123 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1124 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1125 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1126 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1127 } 1128 1129 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1130 { 1131 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1132 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1133 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1134 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1135 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1136 } 1137 1138 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1139 { 1140 u_register_t mpam_idr = read_mpamidr_el1(); 1141 1142 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1143 1144 /* 1145 * The context registers that we intend to save would be part of the 1146 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1147 */ 1148 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1149 return; 1150 } 1151 1152 /* 1153 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1154 * MPAMIDR_HAS_HCR_BIT == 1. 1155 */ 1156 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1157 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1158 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1159 1160 /* 1161 * The number of MPAMVPM registers is implementation defined, their 1162 * number is stored in the MPAMIDR_EL1 register. 1163 */ 1164 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1165 case 7: 1166 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1167 __fallthrough; 1168 case 6: 1169 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1170 __fallthrough; 1171 case 5: 1172 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1173 __fallthrough; 1174 case 4: 1175 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1176 __fallthrough; 1177 case 3: 1178 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1179 __fallthrough; 1180 case 2: 1181 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1182 __fallthrough; 1183 case 1: 1184 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1185 break; 1186 } 1187 } 1188 1189 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1190 { 1191 u_register_t mpam_idr = read_mpamidr_el1(); 1192 1193 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1194 1195 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1196 return; 1197 } 1198 1199 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1200 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1201 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1202 1203 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1204 case 7: 1205 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1206 __fallthrough; 1207 case 6: 1208 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1209 __fallthrough; 1210 case 5: 1211 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1212 __fallthrough; 1213 case 4: 1214 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1215 __fallthrough; 1216 case 3: 1217 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1218 __fallthrough; 1219 case 2: 1220 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1221 __fallthrough; 1222 case 1: 1223 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1224 break; 1225 } 1226 } 1227 1228 /* --------------------------------------------------------------------------- 1229 * The following registers are not added: 1230 * ICH_AP0R<n>_EL2 1231 * ICH_AP1R<n>_EL2 1232 * ICH_LR<n>_EL2 1233 * 1234 * NOTE: For a system with S-EL2 present but not enabled, accessing 1235 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1236 * SCR_EL3.NS = 1 before accessing this register. 1237 * --------------------------------------------------------------------------- 1238 */ 1239 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1240 { 1241 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1242 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1243 #else 1244 u_register_t scr_el3 = read_scr_el3(); 1245 write_scr_el3(scr_el3 | SCR_NS_BIT); 1246 isb(); 1247 1248 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1249 1250 write_scr_el3(scr_el3); 1251 isb(); 1252 #endif 1253 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1254 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1255 } 1256 1257 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1258 { 1259 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1260 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1261 #else 1262 u_register_t scr_el3 = read_scr_el3(); 1263 write_scr_el3(scr_el3 | SCR_NS_BIT); 1264 isb(); 1265 1266 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1267 1268 write_scr_el3(scr_el3); 1269 isb(); 1270 #endif 1271 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1272 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1273 } 1274 1275 /* ----------------------------------------------------- 1276 * The following registers are not added: 1277 * AMEVCNTVOFF0<n>_EL2 1278 * AMEVCNTVOFF1<n>_EL2 1279 * ----------------------------------------------------- 1280 */ 1281 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1282 { 1283 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1284 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1285 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1286 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1287 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1288 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1289 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1290 if (CTX_INCLUDE_AARCH32_REGS) { 1291 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1292 } 1293 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1294 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1295 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1296 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1297 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1298 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1299 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1300 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1301 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1302 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1303 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1304 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1305 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1306 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1307 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1308 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1309 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1310 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1311 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1312 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1313 } 1314 1315 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1316 { 1317 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1318 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1319 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1320 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1321 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1322 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1323 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1324 if (CTX_INCLUDE_AARCH32_REGS) { 1325 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1326 } 1327 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1328 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1329 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1330 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1331 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1332 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1333 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1334 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1335 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1336 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1337 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1338 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1339 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1340 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1341 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1342 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1343 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1344 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1345 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1346 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1347 } 1348 1349 /******************************************************************************* 1350 * Save EL2 sysreg context 1351 ******************************************************************************/ 1352 void cm_el2_sysregs_context_save(uint32_t security_state) 1353 { 1354 cpu_context_t *ctx; 1355 el2_sysregs_t *el2_sysregs_ctx; 1356 1357 ctx = cm_get_context(security_state); 1358 assert(ctx != NULL); 1359 1360 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1361 1362 el2_sysregs_context_save_common(el2_sysregs_ctx); 1363 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1364 1365 if (is_feat_mte2_supported()) { 1366 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1367 } 1368 1369 if (is_feat_mpam_supported()) { 1370 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1371 } 1372 1373 if (is_feat_fgt_supported()) { 1374 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1375 } 1376 1377 if (is_feat_fgt2_supported()) { 1378 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1379 } 1380 1381 if (is_feat_ecv_v2_supported()) { 1382 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1383 } 1384 1385 if (is_feat_vhe_supported()) { 1386 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1387 read_contextidr_el2()); 1388 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1389 } 1390 1391 if (is_feat_ras_supported()) { 1392 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1393 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1394 } 1395 1396 if (is_feat_nv2_supported()) { 1397 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1398 } 1399 1400 if (is_feat_trf_supported()) { 1401 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1402 } 1403 1404 if (is_feat_csv2_2_supported()) { 1405 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1406 read_scxtnum_el2()); 1407 } 1408 1409 if (is_feat_hcx_supported()) { 1410 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1411 } 1412 1413 if (is_feat_tcr2_supported()) { 1414 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1415 } 1416 1417 if (is_feat_sxpie_supported()) { 1418 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1419 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1420 } 1421 1422 if (is_feat_sxpoe_supported()) { 1423 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1424 } 1425 1426 if (is_feat_s2pie_supported()) { 1427 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1428 } 1429 1430 if (is_feat_gcs_supported()) { 1431 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1432 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1433 } 1434 } 1435 1436 /******************************************************************************* 1437 * Restore EL2 sysreg context 1438 ******************************************************************************/ 1439 void cm_el2_sysregs_context_restore(uint32_t security_state) 1440 { 1441 cpu_context_t *ctx; 1442 el2_sysregs_t *el2_sysregs_ctx; 1443 1444 ctx = cm_get_context(security_state); 1445 assert(ctx != NULL); 1446 1447 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1448 1449 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1450 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1451 1452 if (is_feat_mte2_supported()) { 1453 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1454 } 1455 1456 if (is_feat_mpam_supported()) { 1457 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1458 } 1459 1460 if (is_feat_fgt_supported()) { 1461 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1462 } 1463 1464 if (is_feat_fgt2_supported()) { 1465 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1466 } 1467 1468 if (is_feat_ecv_v2_supported()) { 1469 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1470 } 1471 1472 if (is_feat_vhe_supported()) { 1473 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1474 contextidr_el2)); 1475 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1476 } 1477 1478 if (is_feat_ras_supported()) { 1479 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1480 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1481 } 1482 1483 if (is_feat_nv2_supported()) { 1484 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1485 } 1486 1487 if (is_feat_trf_supported()) { 1488 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1489 } 1490 1491 if (is_feat_csv2_2_supported()) { 1492 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1493 scxtnum_el2)); 1494 } 1495 1496 if (is_feat_hcx_supported()) { 1497 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1498 } 1499 1500 if (is_feat_tcr2_supported()) { 1501 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1502 } 1503 1504 if (is_feat_sxpie_supported()) { 1505 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1506 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1507 } 1508 1509 if (is_feat_sxpoe_supported()) { 1510 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1511 } 1512 1513 if (is_feat_s2pie_supported()) { 1514 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1515 } 1516 1517 if (is_feat_gcs_supported()) { 1518 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1519 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1520 } 1521 } 1522 #endif /* CTX_INCLUDE_EL2_REGS */ 1523 1524 #if IMAGE_BL31 1525 /********************************************************************************* 1526 * This function allows Architecture features asymmetry among cores. 1527 * TF-A assumes that all the cores in the platform has architecture feature parity 1528 * and hence the context is setup on different core (e.g. primary sets up the 1529 * context for secondary cores).This assumption may not be true for systems where 1530 * cores are not conforming to same Arch version or there is CPU Erratum which 1531 * requires certain feature to be be disabled only on a given core. 1532 * 1533 * This function is called on secondary cores to override any disparity in context 1534 * setup by primary, this would be called during warmboot path. 1535 *********************************************************************************/ 1536 void cm_handle_asymmetric_features(void) 1537 { 1538 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1539 cpu_context_t *spe_ctx = cm_get_context(NON_SECURE); 1540 1541 assert(spe_ctx != NULL); 1542 1543 if (is_feat_spe_supported()) { 1544 spe_enable(spe_ctx); 1545 } else { 1546 spe_disable(spe_ctx); 1547 } 1548 #endif 1549 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1550 cpu_context_t *trbe_ctx = cm_get_context(NON_SECURE); 1551 1552 assert(trbe_ctx != NULL); 1553 1554 if (check_if_affected_core() == ERRATA_APPLIES) { 1555 if (is_feat_trbe_supported()) { 1556 trbe_disable(trbe_ctx); 1557 } 1558 } 1559 #endif 1560 } 1561 #endif 1562 1563 /******************************************************************************* 1564 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1565 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1566 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1567 * cm_prepare_el3_exit function. 1568 ******************************************************************************/ 1569 void cm_prepare_el3_exit_ns(void) 1570 { 1571 #if IMAGE_BL31 1572 /* 1573 * Check and handle Architecture feature asymmetry among cores. 1574 * 1575 * In warmboot path secondary cores context is initialized on core which 1576 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1577 * it in this function call. 1578 * For Symmetric cores this is an empty function. 1579 */ 1580 cm_handle_asymmetric_features(); 1581 #endif 1582 1583 #if CTX_INCLUDE_EL2_REGS 1584 #if ENABLE_ASSERTIONS 1585 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1586 assert(ctx != NULL); 1587 1588 /* Assert that EL2 is used. */ 1589 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1590 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1591 (el_implemented(2U) != EL_IMPL_NONE)); 1592 #endif /* ENABLE_ASSERTIONS */ 1593 1594 /* Restore EL2 and EL1 sysreg contexts */ 1595 cm_el2_sysregs_context_restore(NON_SECURE); 1596 cm_el1_sysregs_context_restore(NON_SECURE); 1597 cm_set_next_eret_context(NON_SECURE); 1598 #else 1599 cm_prepare_el3_exit(NON_SECURE); 1600 #endif /* CTX_INCLUDE_EL2_REGS */ 1601 } 1602 1603 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1604 { 1605 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1606 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1607 1608 #if (!ERRATA_SPECULATIVE_AT) 1609 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1610 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1611 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1612 1613 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1614 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1615 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1616 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1617 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1618 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1619 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1620 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1621 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1622 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1623 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1624 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1625 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1626 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1627 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1628 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1629 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1630 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1631 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1632 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1633 1634 if (CTX_INCLUDE_AARCH32_REGS) { 1635 /* Save Aarch32 registers */ 1636 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1637 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1638 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1639 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1640 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1641 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1642 } 1643 1644 if (NS_TIMER_SWITCH) { 1645 /* Save NS Timer registers */ 1646 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1647 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1648 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1649 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1650 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1651 } 1652 1653 if (is_feat_mte2_supported()) { 1654 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1655 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1656 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1657 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1658 } 1659 1660 if (is_feat_ras_supported()) { 1661 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1662 } 1663 1664 if (is_feat_s1pie_supported()) { 1665 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1666 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1667 } 1668 1669 if (is_feat_s1poe_supported()) { 1670 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1671 } 1672 1673 if (is_feat_s2poe_supported()) { 1674 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1675 } 1676 1677 if (is_feat_tcr2_supported()) { 1678 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1679 } 1680 1681 if (is_feat_trf_supported()) { 1682 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1683 } 1684 1685 if (is_feat_csv2_2_supported()) { 1686 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1687 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1688 } 1689 1690 if (is_feat_gcs_supported()) { 1691 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1692 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1693 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1694 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1695 } 1696 } 1697 1698 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1699 { 1700 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1701 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1702 1703 #if (!ERRATA_SPECULATIVE_AT) 1704 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1705 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1706 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1707 1708 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1709 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1710 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1711 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1712 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1713 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1714 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1715 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1716 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1717 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1718 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1719 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1720 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1721 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1722 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1723 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1724 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1725 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1726 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1727 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1728 1729 if (CTX_INCLUDE_AARCH32_REGS) { 1730 /* Restore Aarch32 registers */ 1731 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1732 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1733 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1734 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1735 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1736 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1737 } 1738 1739 if (NS_TIMER_SWITCH) { 1740 /* Restore NS Timer registers */ 1741 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1742 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1743 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1744 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1745 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1746 } 1747 1748 if (is_feat_mte2_supported()) { 1749 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1750 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1751 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1752 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1753 } 1754 1755 if (is_feat_ras_supported()) { 1756 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1757 } 1758 1759 if (is_feat_s1pie_supported()) { 1760 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1761 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1762 } 1763 1764 if (is_feat_s1poe_supported()) { 1765 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1766 } 1767 1768 if (is_feat_s2poe_supported()) { 1769 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1770 } 1771 1772 if (is_feat_tcr2_supported()) { 1773 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1774 } 1775 1776 if (is_feat_trf_supported()) { 1777 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1778 } 1779 1780 if (is_feat_csv2_2_supported()) { 1781 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1782 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1783 } 1784 1785 if (is_feat_gcs_supported()) { 1786 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1787 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1788 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1789 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1790 } 1791 } 1792 1793 /******************************************************************************* 1794 * The next four functions are used by runtime services to save and restore 1795 * EL1 context on the 'cpu_context' structure for the specified security 1796 * state. 1797 ******************************************************************************/ 1798 void cm_el1_sysregs_context_save(uint32_t security_state) 1799 { 1800 cpu_context_t *ctx; 1801 1802 ctx = cm_get_context(security_state); 1803 assert(ctx != NULL); 1804 1805 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1806 1807 #if IMAGE_BL31 1808 if (security_state == SECURE) 1809 PUBLISH_EVENT(cm_exited_secure_world); 1810 else 1811 PUBLISH_EVENT(cm_exited_normal_world); 1812 #endif 1813 } 1814 1815 void cm_el1_sysregs_context_restore(uint32_t security_state) 1816 { 1817 cpu_context_t *ctx; 1818 1819 ctx = cm_get_context(security_state); 1820 assert(ctx != NULL); 1821 1822 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1823 1824 #if IMAGE_BL31 1825 if (security_state == SECURE) 1826 PUBLISH_EVENT(cm_entering_secure_world); 1827 else 1828 PUBLISH_EVENT(cm_entering_normal_world); 1829 #endif 1830 } 1831 1832 /******************************************************************************* 1833 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1834 * given security state with the given entrypoint 1835 ******************************************************************************/ 1836 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1837 { 1838 cpu_context_t *ctx; 1839 el3_state_t *state; 1840 1841 ctx = cm_get_context(security_state); 1842 assert(ctx != NULL); 1843 1844 /* Populate EL3 state so that ERET jumps to the correct entry */ 1845 state = get_el3state_ctx(ctx); 1846 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1847 } 1848 1849 /******************************************************************************* 1850 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1851 * pertaining to the given security state 1852 ******************************************************************************/ 1853 void cm_set_elr_spsr_el3(uint32_t security_state, 1854 uintptr_t entrypoint, uint32_t spsr) 1855 { 1856 cpu_context_t *ctx; 1857 el3_state_t *state; 1858 1859 ctx = cm_get_context(security_state); 1860 assert(ctx != NULL); 1861 1862 /* Populate EL3 state so that ERET jumps to the correct entry */ 1863 state = get_el3state_ctx(ctx); 1864 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1865 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1866 } 1867 1868 /******************************************************************************* 1869 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1870 * pertaining to the given security state using the value and bit position 1871 * specified in the parameters. It preserves all other bits. 1872 ******************************************************************************/ 1873 void cm_write_scr_el3_bit(uint32_t security_state, 1874 uint32_t bit_pos, 1875 uint32_t value) 1876 { 1877 cpu_context_t *ctx; 1878 el3_state_t *state; 1879 u_register_t scr_el3; 1880 1881 ctx = cm_get_context(security_state); 1882 assert(ctx != NULL); 1883 1884 /* Ensure that the bit position is a valid one */ 1885 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1886 1887 /* Ensure that the 'value' is only a bit wide */ 1888 assert(value <= 1U); 1889 1890 /* 1891 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1892 * and set it to its new value. 1893 */ 1894 state = get_el3state_ctx(ctx); 1895 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1896 scr_el3 &= ~(1UL << bit_pos); 1897 scr_el3 |= (u_register_t)value << bit_pos; 1898 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1899 } 1900 1901 /******************************************************************************* 1902 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1903 * given security state. 1904 ******************************************************************************/ 1905 u_register_t cm_get_scr_el3(uint32_t security_state) 1906 { 1907 cpu_context_t *ctx; 1908 el3_state_t *state; 1909 1910 ctx = cm_get_context(security_state); 1911 assert(ctx != NULL); 1912 1913 /* Populate EL3 state so that ERET jumps to the correct entry */ 1914 state = get_el3state_ctx(ctx); 1915 return read_ctx_reg(state, CTX_SCR_EL3); 1916 } 1917 1918 /******************************************************************************* 1919 * This function is used to program the context that's used for exception 1920 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1921 * the required security state 1922 ******************************************************************************/ 1923 void cm_set_next_eret_context(uint32_t security_state) 1924 { 1925 cpu_context_t *ctx; 1926 1927 ctx = cm_get_context(security_state); 1928 assert(ctx != NULL); 1929 1930 cm_set_next_context(ctx); 1931 } 1932