1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/debug_v8p9.h> 28 #include <lib/extensions/mpam.h> 29 #include <lib/extensions/pmuv3.h> 30 #include <lib/extensions/sme.h> 31 #include <lib/extensions/spe.h> 32 #include <lib/extensions/sve.h> 33 #include <lib/extensions/sys_reg_trace.h> 34 #include <lib/extensions/trbe.h> 35 #include <lib/extensions/trf.h> 36 #include <lib/utils.h> 37 38 #if ENABLE_FEAT_TWED 39 /* Make sure delay value fits within the range(0-15) */ 40 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 41 #endif /* ENABLE_FEAT_TWED */ 42 43 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 44 static bool has_secure_perworld_init; 45 46 static void manage_extensions_common(cpu_context_t *ctx); 47 static void manage_extensions_nonsecure(cpu_context_t *ctx); 48 static void manage_extensions_secure(cpu_context_t *ctx); 49 static void manage_extensions_secure_per_world(void); 50 51 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 52 { 53 u_register_t sctlr_elx, actlr_elx; 54 55 /* 56 * Initialise SCTLR_EL1 to the reset value corresponding to the target 57 * execution state setting all fields rather than relying on the hw. 58 * Some fields have architecturally UNKNOWN reset values and these are 59 * set to zero. 60 * 61 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 62 * 63 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 64 * required by PSCI specification) 65 */ 66 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 67 if (GET_RW(ep->spsr) == MODE_RW_64) { 68 sctlr_elx |= SCTLR_EL1_RES1; 69 } else { 70 /* 71 * If the target execution state is AArch32 then the following 72 * fields need to be set. 73 * 74 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 75 * instructions are not trapped to EL1. 76 * 77 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 78 * instructions are not trapped to EL1. 79 * 80 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 81 * CP15DMB, CP15DSB, and CP15ISB instructions. 82 */ 83 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 84 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 85 } 86 87 #if ERRATA_A75_764081 88 /* 89 * If workaround of errata 764081 for Cortex-A75 is used then set 90 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 91 */ 92 sctlr_elx |= SCTLR_IESB_BIT; 93 #endif 94 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 95 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 96 97 /* 98 * Base the context ACTLR_EL1 on the current value, as it is 99 * implementation defined. The context restore process will write 100 * the value from the context to the actual register and can cause 101 * problems for processor cores that don't expect certain bits to 102 * be zero. 103 */ 104 actlr_elx = read_actlr_el1(); 105 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 106 } 107 108 /****************************************************************************** 109 * This function performs initializations that are specific to SECURE state 110 * and updates the cpu context specified by 'ctx'. 111 *****************************************************************************/ 112 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 113 { 114 u_register_t scr_el3; 115 el3_state_t *state; 116 117 state = get_el3state_ctx(ctx); 118 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 119 120 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 121 /* 122 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 123 * indicated by the interrupt routing model for BL31. 124 */ 125 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 126 #endif 127 128 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 129 if (is_feat_mte2_supported()) { 130 scr_el3 |= SCR_ATA_BIT; 131 } 132 133 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 134 135 /* 136 * Initialize EL1 context registers unless SPMC is running 137 * at S-EL2. 138 */ 139 #if !SPMD_SPM_AT_SEL2 140 setup_el1_context(ctx, ep); 141 #endif 142 143 manage_extensions_secure(ctx); 144 145 /** 146 * manage_extensions_secure_per_world api has to be executed once, 147 * as the registers getting initialised, maintain constant value across 148 * all the cpus for the secure world. 149 * Henceforth, this check ensures that the registers are initialised once 150 * and avoids re-initialization from multiple cores. 151 */ 152 if (!has_secure_perworld_init) { 153 manage_extensions_secure_per_world(); 154 } 155 156 } 157 158 #if ENABLE_RME 159 /****************************************************************************** 160 * This function performs initializations that are specific to REALM state 161 * and updates the cpu context specified by 'ctx'. 162 *****************************************************************************/ 163 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 164 { 165 u_register_t scr_el3; 166 el3_state_t *state; 167 168 state = get_el3state_ctx(ctx); 169 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 170 171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 172 173 /* CSV2 version 2 and above */ 174 if (is_feat_csv2_2_supported()) { 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 } 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 199 if (is_feat_mte2_supported()) { 200 scr_el3 |= SCR_ATA_BIT; 201 } 202 203 #if !CTX_INCLUDE_PAUTH_REGS 204 /* 205 * Pointer Authentication feature, if present, is always enabled by default 206 * for Non secure lower exception levels. We do not have an explicit 207 * flag to set it. 208 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 209 * exception levels of secure and realm worlds. 210 * 211 * To prevent the leakage between the worlds during world switch, 212 * we enable it only for the non-secure world. 213 * 214 * If the Secure/realm world wants to use pointer authentication, 215 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 216 * it will be enabled globally for all the contexts. 217 * 218 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 219 * other than EL3 220 * 221 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 222 * than EL3 223 */ 224 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 225 226 #endif /* CTX_INCLUDE_PAUTH_REGS */ 227 228 #if HANDLE_EA_EL3_FIRST_NS 229 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 230 scr_el3 |= SCR_EA_BIT; 231 #endif 232 233 #if RAS_TRAP_NS_ERR_REC_ACCESS 234 /* 235 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 236 * and RAS ERX registers from EL1 and EL2(from any security state) 237 * are trapped to EL3. 238 * Set here to trap only for NS EL1/EL2 239 * 240 */ 241 scr_el3 |= SCR_TERR_BIT; 242 #endif 243 244 /* CSV2 version 2 and above */ 245 if (is_feat_csv2_2_supported()) { 246 /* Enable access to the SCXTNUM_ELx registers. */ 247 scr_el3 |= SCR_EnSCXT_BIT; 248 } 249 250 #ifdef IMAGE_BL31 251 /* 252 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 253 * indicated by the interrupt routing model for BL31. 254 */ 255 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 256 #endif 257 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 258 259 /* Initialize EL1 context registers */ 260 setup_el1_context(ctx, ep); 261 262 /* Initialize EL2 context registers */ 263 #if CTX_INCLUDE_EL2_REGS 264 265 /* 266 * Initialize SCTLR_EL2 context register with reset value. 267 */ 268 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 269 270 if (is_feat_hcx_supported()) { 271 /* 272 * Initialize register HCRX_EL2 with its init value. 273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 274 * chance that this can lead to unexpected behavior in lower 275 * ELs that have not been updated since the introduction of 276 * this feature if not properly initialized, especially when 277 * it comes to those bits that enable/disable traps. 278 */ 279 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 280 HCRX_EL2_INIT_VAL); 281 } 282 283 if (is_feat_fgt_supported()) { 284 /* 285 * Initialize HFG*_EL2 registers with a default value so legacy 286 * systems unaware of FEAT_FGT do not get trapped due to their lack 287 * of initialization for this feature. 288 */ 289 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 290 HFGITR_EL2_INIT_VAL); 291 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 292 HFGRTR_EL2_INIT_VAL); 293 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 294 HFGWTR_EL2_INIT_VAL); 295 } 296 297 #endif /* CTX_INCLUDE_EL2_REGS */ 298 299 manage_extensions_nonsecure(ctx); 300 } 301 302 /******************************************************************************* 303 * The following function performs initialization of the cpu_context 'ctx' 304 * for first use that is common to all security states, and sets the 305 * initial entrypoint state as specified by the entry_point_info structure. 306 * 307 * The EE and ST attributes are used to configure the endianness and secure 308 * timer availability for the new execution context. 309 ******************************************************************************/ 310 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 311 { 312 u_register_t scr_el3; 313 u_register_t mdcr_el3; 314 el3_state_t *state; 315 gp_regs_t *gp_regs; 316 317 state = get_el3state_ctx(ctx); 318 319 /* Clear any residual register values from the context */ 320 zeromem(ctx, sizeof(*ctx)); 321 322 /* 323 * The lower-EL context is zeroed so that no stale values leak to a world. 324 * It is assumed that an all-zero lower-EL context is good enough for it 325 * to boot correctly. However, there are very few registers where this 326 * is not true and some values need to be recreated. 327 */ 328 #if CTX_INCLUDE_EL2_REGS 329 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 330 331 /* 332 * These bits are set in the gicv3 driver. Losing them (especially the 333 * SRE bit) is problematic for all worlds. Henceforth recreate them. 334 */ 335 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 336 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 337 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 338 #endif /* CTX_INCLUDE_EL2_REGS */ 339 340 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 341 scr_el3 = SCR_RESET_VAL; 342 343 /* 344 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 345 * EL2, EL1 and EL0 are not trapped to EL3. 346 * 347 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 348 * EL2, EL1 and EL0 are not trapped to EL3. 349 * 350 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 351 * both Security states and both Execution states. 352 * 353 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 354 * Non-secure memory. 355 */ 356 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 357 358 scr_el3 |= SCR_SIF_BIT; 359 360 /* 361 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 362 * Exception level as specified by SPSR. 363 */ 364 if (GET_RW(ep->spsr) == MODE_RW_64) { 365 scr_el3 |= SCR_RW_BIT; 366 } 367 368 /* 369 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 370 * Secure timer registers to EL3, from AArch64 state only, if specified 371 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 372 * bit always behaves as 1 (i.e. secure physical timer register access 373 * is not trapped) 374 */ 375 if (EP_GET_ST(ep->h.attr) != 0U) { 376 scr_el3 |= SCR_ST_BIT; 377 } 378 379 /* 380 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 381 * SCR_EL3.HXEn. 382 */ 383 if (is_feat_hcx_supported()) { 384 scr_el3 |= SCR_HXEn_BIT; 385 } 386 387 /* 388 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 389 * registers are trapped to EL3. 390 */ 391 #if ENABLE_FEAT_RNG_TRAP 392 scr_el3 |= SCR_TRNDR_BIT; 393 #endif 394 395 #if FAULT_INJECTION_SUPPORT 396 /* Enable fault injection from lower ELs */ 397 scr_el3 |= SCR_FIEN_BIT; 398 #endif 399 400 #if CTX_INCLUDE_PAUTH_REGS 401 /* 402 * Enable Pointer Authentication globally for all the worlds. 403 * 404 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 405 * other than EL3 406 * 407 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 408 * than EL3 409 */ 410 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 411 #endif /* CTX_INCLUDE_PAUTH_REGS */ 412 413 /* 414 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 415 */ 416 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 417 scr_el3 |= SCR_TCR2EN_BIT; 418 } 419 420 /* 421 * SCR_EL3.PIEN: Enable permission indirection and overlay 422 * registers for AArch64 if present. 423 */ 424 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 425 scr_el3 |= SCR_PIEN_BIT; 426 } 427 428 /* 429 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 430 */ 431 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 432 scr_el3 |= SCR_GCSEn_BIT; 433 } 434 435 /* 436 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 437 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 438 * next mode is Hyp. 439 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 440 * same conditions as HVC instructions and when the processor supports 441 * ARMv8.6-FGT. 442 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 443 * CNTPOFF_EL2 register under the same conditions as HVC instructions 444 * and when the processor supports ECV. 445 */ 446 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 447 || ((GET_RW(ep->spsr) != MODE_RW_64) 448 && (GET_M32(ep->spsr) == MODE32_hyp))) { 449 scr_el3 |= SCR_HCE_BIT; 450 451 if (is_feat_fgt_supported()) { 452 scr_el3 |= SCR_FGTEN_BIT; 453 } 454 455 if (is_feat_ecv_supported()) { 456 scr_el3 |= SCR_ECVEN_BIT; 457 } 458 } 459 460 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 461 if (is_feat_twed_supported()) { 462 /* Set delay in SCR_EL3 */ 463 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 464 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 465 << SCR_TWEDEL_SHIFT); 466 467 /* Enable WFE delay */ 468 scr_el3 |= SCR_TWEDEn_BIT; 469 } 470 471 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 472 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 473 if (is_feat_sel2_supported()) { 474 scr_el3 |= SCR_EEL2_BIT; 475 } 476 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 477 478 /* 479 * Populate EL3 state so that we've the right context 480 * before doing ERET 481 */ 482 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 483 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 484 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 485 486 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 487 mdcr_el3 = MDCR_EL3_RESET_VAL; 488 489 /* --------------------------------------------------------------------- 490 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 491 * Some fields are architecturally UNKNOWN on reset. 492 * 493 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 494 * Debug exceptions, other than Breakpoint Instruction exceptions, are 495 * disabled from all ELs in Secure state. 496 * 497 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 498 * privileged debug from S-EL1. 499 * 500 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 501 * access to the powerdown debug registers do not trap to EL3. 502 * 503 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 504 * debug registers, other than those registers that are controlled by 505 * MDCR_EL3.TDOSA. 506 */ 507 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 508 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 509 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 510 511 /* 512 * Configure MDCR_EL3 register as applicable for each world 513 * (NS/Secure/Realm) context. 514 */ 515 manage_extensions_common(ctx); 516 517 /* 518 * Store the X0-X7 value from the entrypoint into the context 519 * Use memcpy as we are in control of the layout of the structures 520 */ 521 gp_regs = get_gpregs_ctx(ctx); 522 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 523 } 524 525 /******************************************************************************* 526 * Context management library initialization routine. This library is used by 527 * runtime services to share pointers to 'cpu_context' structures for secure 528 * non-secure and realm states. Management of the structures and their associated 529 * memory is not done by the context management library e.g. the PSCI service 530 * manages the cpu context used for entry from and exit to the non-secure state. 531 * The Secure payload dispatcher service manages the context(s) corresponding to 532 * the secure state. It also uses this library to get access to the non-secure 533 * state cpu context pointers. 534 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 535 * which will be used for programming an entry into a lower EL. The same context 536 * will be used to save state upon exception entry from that EL. 537 ******************************************************************************/ 538 void __init cm_init(void) 539 { 540 /* 541 * The context management library has only global data to initialize, but 542 * that will be done when the BSS is zeroed out. 543 */ 544 } 545 546 /******************************************************************************* 547 * This is the high-level function used to initialize the cpu_context 'ctx' for 548 * first use. It performs initializations that are common to all security states 549 * and initializations specific to the security state specified in 'ep' 550 ******************************************************************************/ 551 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 552 { 553 unsigned int security_state; 554 555 assert(ctx != NULL); 556 557 /* 558 * Perform initializations that are common 559 * to all security states 560 */ 561 setup_context_common(ctx, ep); 562 563 security_state = GET_SECURITY_STATE(ep->h.attr); 564 565 /* Perform security state specific initializations */ 566 switch (security_state) { 567 case SECURE: 568 setup_secure_context(ctx, ep); 569 break; 570 #if ENABLE_RME 571 case REALM: 572 setup_realm_context(ctx, ep); 573 break; 574 #endif 575 case NON_SECURE: 576 setup_ns_context(ctx, ep); 577 break; 578 default: 579 ERROR("Invalid security state\n"); 580 panic(); 581 break; 582 } 583 } 584 585 /******************************************************************************* 586 * Enable architecture extensions for EL3 execution. This function only updates 587 * registers in-place which are expected to either never change or be 588 * overwritten by el3_exit. 589 ******************************************************************************/ 590 #if IMAGE_BL31 591 void cm_manage_extensions_el3(void) 592 { 593 if (is_feat_amu_supported()) { 594 amu_init_el3(); 595 } 596 597 if (is_feat_sme_supported()) { 598 sme_init_el3(); 599 } 600 601 pmuv3_init_el3(); 602 } 603 #endif /* IMAGE_BL31 */ 604 605 /****************************************************************************** 606 * Function to initialise the registers with the RESET values in the context 607 * memory, which are maintained per world. 608 ******************************************************************************/ 609 #if IMAGE_BL31 610 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 611 { 612 /* 613 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 614 * 615 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 616 * by Advanced SIMD, floating-point or SVE instructions (if 617 * implemented) do not trap to EL3. 618 * 619 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 620 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 621 */ 622 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 623 624 per_world_ctx->ctx_cptr_el3 = cptr_el3; 625 626 /* 627 * Initialize MPAM3_EL3 to its default reset value 628 * 629 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 630 * all lower ELn MPAM3_EL3 register access to, trap to EL3 631 */ 632 633 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 634 } 635 #endif /* IMAGE_BL31 */ 636 637 /******************************************************************************* 638 * Initialise per_world_context for Non-Secure world. 639 * This function enables the architecture extensions, which have same value 640 * across the cores for the non-secure world. 641 ******************************************************************************/ 642 #if IMAGE_BL31 643 void manage_extensions_nonsecure_per_world(void) 644 { 645 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 646 647 if (is_feat_sme_supported()) { 648 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 649 } 650 651 if (is_feat_sve_supported()) { 652 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 653 } 654 655 if (is_feat_amu_supported()) { 656 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 657 } 658 659 if (is_feat_sys_reg_trace_supported()) { 660 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 661 } 662 663 if (is_feat_mpam_supported()) { 664 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 665 } 666 } 667 #endif /* IMAGE_BL31 */ 668 669 /******************************************************************************* 670 * Initialise per_world_context for Secure world. 671 * This function enables the architecture extensions, which have same value 672 * across the cores for the secure world. 673 ******************************************************************************/ 674 static void manage_extensions_secure_per_world(void) 675 { 676 #if IMAGE_BL31 677 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 678 679 if (is_feat_sme_supported()) { 680 681 if (ENABLE_SME_FOR_SWD) { 682 /* 683 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 684 * SME, SVE, and FPU/SIMD context properly managed. 685 */ 686 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 687 } else { 688 /* 689 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 690 * world can safely use the associated registers. 691 */ 692 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 693 } 694 } 695 if (is_feat_sve_supported()) { 696 if (ENABLE_SVE_FOR_SWD) { 697 /* 698 * Enable SVE and FPU in secure context, SPM must ensure 699 * that the SVE and FPU register contexts are properly managed. 700 */ 701 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 702 } else { 703 /* 704 * Disable SVE and FPU in secure context so non-secure world 705 * can safely use them. 706 */ 707 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 708 } 709 } 710 711 /* NS can access this but Secure shouldn't */ 712 if (is_feat_sys_reg_trace_supported()) { 713 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 714 } 715 716 has_secure_perworld_init = true; 717 #endif /* IMAGE_BL31 */ 718 } 719 720 /******************************************************************************* 721 * Enable architecture extensions on first entry to Non-secure world only 722 * and disable for secure world. 723 * 724 * NOTE: Arch features which have been provided with the capability of getting 725 * enabled only for non-secure world and being disabled for secure world are 726 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 727 ******************************************************************************/ 728 static void manage_extensions_common(cpu_context_t *ctx) 729 { 730 #if IMAGE_BL31 731 if (is_feat_spe_supported()) { 732 /* 733 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 734 */ 735 spe_enable(ctx); 736 } 737 738 if (is_feat_trbe_supported()) { 739 /* 740 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 741 * Realm state. 742 */ 743 trbe_enable(ctx); 744 } 745 746 if (is_feat_trf_supported()) { 747 /* 748 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 749 */ 750 trf_enable(ctx); 751 } 752 753 if (is_feat_brbe_supported()) { 754 /* 755 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 756 */ 757 brbe_enable(ctx); 758 } 759 #endif /* IMAGE_BL31 */ 760 } 761 762 /******************************************************************************* 763 * Enable architecture extensions on first entry to Non-secure world. 764 ******************************************************************************/ 765 static void manage_extensions_nonsecure(cpu_context_t *ctx) 766 { 767 #if IMAGE_BL31 768 if (is_feat_amu_supported()) { 769 amu_enable(ctx); 770 } 771 772 if (is_feat_sme_supported()) { 773 sme_enable(ctx); 774 } 775 776 if (is_feat_debugv8p9_supported()) { 777 debugv8p9_extended_bp_wp_enable(ctx); 778 } 779 780 pmuv3_enable(ctx); 781 #endif /* IMAGE_BL31 */ 782 } 783 784 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 785 static __unused void enable_pauth_el2(void) 786 { 787 u_register_t hcr_el2 = read_hcr_el2(); 788 /* 789 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 790 * accessing key registers or using pointer authentication instructions 791 * from lower ELs. 792 */ 793 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 794 795 write_hcr_el2(hcr_el2); 796 } 797 798 #if INIT_UNUSED_NS_EL2 799 /******************************************************************************* 800 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 801 * world when EL2 is empty and unused. 802 ******************************************************************************/ 803 static void manage_extensions_nonsecure_el2_unused(void) 804 { 805 #if IMAGE_BL31 806 if (is_feat_spe_supported()) { 807 spe_init_el2_unused(); 808 } 809 810 if (is_feat_amu_supported()) { 811 amu_init_el2_unused(); 812 } 813 814 if (is_feat_mpam_supported()) { 815 mpam_init_el2_unused(); 816 } 817 818 if (is_feat_trbe_supported()) { 819 trbe_init_el2_unused(); 820 } 821 822 if (is_feat_sys_reg_trace_supported()) { 823 sys_reg_trace_init_el2_unused(); 824 } 825 826 if (is_feat_trf_supported()) { 827 trf_init_el2_unused(); 828 } 829 830 pmuv3_init_el2_unused(); 831 832 if (is_feat_sve_supported()) { 833 sve_init_el2_unused(); 834 } 835 836 if (is_feat_sme_supported()) { 837 sme_init_el2_unused(); 838 } 839 840 #if ENABLE_PAUTH 841 enable_pauth_el2(); 842 #endif /* ENABLE_PAUTH */ 843 #endif /* IMAGE_BL31 */ 844 } 845 #endif /* INIT_UNUSED_NS_EL2 */ 846 847 /******************************************************************************* 848 * Enable architecture extensions on first entry to Secure world. 849 ******************************************************************************/ 850 static void manage_extensions_secure(cpu_context_t *ctx) 851 { 852 #if IMAGE_BL31 853 if (is_feat_sme_supported()) { 854 if (ENABLE_SME_FOR_SWD) { 855 /* 856 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 857 * must ensure SME, SVE, and FPU/SIMD context properly managed. 858 */ 859 sme_init_el3(); 860 sme_enable(ctx); 861 } else { 862 /* 863 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 864 * world can safely use the associated registers. 865 */ 866 sme_disable(ctx); 867 } 868 } 869 #endif /* IMAGE_BL31 */ 870 } 871 872 #if !IMAGE_BL1 873 /******************************************************************************* 874 * The following function initializes the cpu_context for a CPU specified by 875 * its `cpu_idx` for first use, and sets the initial entrypoint state as 876 * specified by the entry_point_info structure. 877 ******************************************************************************/ 878 void cm_init_context_by_index(unsigned int cpu_idx, 879 const entry_point_info_t *ep) 880 { 881 cpu_context_t *ctx; 882 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 883 cm_setup_context(ctx, ep); 884 } 885 #endif /* !IMAGE_BL1 */ 886 887 /******************************************************************************* 888 * The following function initializes the cpu_context for the current CPU 889 * for first use, and sets the initial entrypoint state as specified by the 890 * entry_point_info structure. 891 ******************************************************************************/ 892 void cm_init_my_context(const entry_point_info_t *ep) 893 { 894 cpu_context_t *ctx; 895 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 896 cm_setup_context(ctx, ep); 897 } 898 899 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 900 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 901 { 902 #if INIT_UNUSED_NS_EL2 903 u_register_t hcr_el2 = HCR_RESET_VAL; 904 u_register_t mdcr_el2; 905 u_register_t scr_el3; 906 907 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 908 909 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 910 if ((scr_el3 & SCR_RW_BIT) != 0U) { 911 hcr_el2 |= HCR_RW_BIT; 912 } 913 914 write_hcr_el2(hcr_el2); 915 916 /* 917 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 918 * All fields have architecturally UNKNOWN reset values. 919 */ 920 write_cptr_el2(CPTR_EL2_RESET_VAL); 921 922 /* 923 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 924 * reset and are set to zero except for field(s) listed below. 925 * 926 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 927 * Non-secure EL0 and EL1 accesses to the physical timer registers. 928 * 929 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 930 * Non-secure EL0 and EL1 accesses to the physical counter registers. 931 */ 932 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 933 934 /* 935 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 936 * UNKNOWN value. 937 */ 938 write_cntvoff_el2(0); 939 940 /* 941 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 942 * respectively. 943 */ 944 write_vpidr_el2(read_midr_el1()); 945 write_vmpidr_el2(read_mpidr_el1()); 946 947 /* 948 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 949 * 950 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 951 * translation is disabled, cache maintenance operations depend on the 952 * VMID. 953 * 954 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 955 * disabled. 956 */ 957 write_vttbr_el2(VTTBR_RESET_VAL & 958 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 959 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 960 961 /* 962 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 963 * Some fields are architecturally UNKNOWN on reset. 964 * 965 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 966 * register accesses to the Debug ROM registers are not trapped to EL2. 967 * 968 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 969 * accesses to the powerdown debug registers are not trapped to EL2. 970 * 971 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 972 * debug registers do not trap to EL2. 973 * 974 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 975 * EL2. 976 */ 977 mdcr_el2 = MDCR_EL2_RESET_VAL & 978 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 979 MDCR_EL2_TDE_BIT); 980 981 write_mdcr_el2(mdcr_el2); 982 983 /* 984 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 985 * 986 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 987 * EL1 accesses to System registers do not trap to EL2. 988 */ 989 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 990 991 /* 992 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 993 * reset. 994 * 995 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 996 * and prevent timer interrupts. 997 */ 998 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 999 1000 manage_extensions_nonsecure_el2_unused(); 1001 #endif /* INIT_UNUSED_NS_EL2 */ 1002 } 1003 1004 /******************************************************************************* 1005 * Prepare the CPU system registers for first entry into realm, secure, or 1006 * normal world. 1007 * 1008 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1009 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1010 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1011 * For all entries, the EL1 registers are initialized from the cpu_context 1012 ******************************************************************************/ 1013 void cm_prepare_el3_exit(uint32_t security_state) 1014 { 1015 u_register_t sctlr_el2, scr_el3; 1016 cpu_context_t *ctx = cm_get_context(security_state); 1017 1018 assert(ctx != NULL); 1019 1020 if (security_state == NON_SECURE) { 1021 uint64_t el2_implemented = el_implemented(2); 1022 1023 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1024 CTX_SCR_EL3); 1025 1026 if (el2_implemented != EL_IMPL_NONE) { 1027 1028 /* 1029 * If context is not being used for EL2, initialize 1030 * HCRX_EL2 with its init value here. 1031 */ 1032 if (is_feat_hcx_supported()) { 1033 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1034 } 1035 1036 /* 1037 * Initialize Fine-grained trap registers introduced 1038 * by FEAT_FGT so all traps are initially disabled when 1039 * switching to EL2 or a lower EL, preventing undesired 1040 * behavior. 1041 */ 1042 if (is_feat_fgt_supported()) { 1043 /* 1044 * Initialize HFG*_EL2 registers with a default 1045 * value so legacy systems unaware of FEAT_FGT 1046 * do not get trapped due to their lack of 1047 * initialization for this feature. 1048 */ 1049 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1050 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1051 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1052 } 1053 1054 /* Condition to ensure EL2 is being used. */ 1055 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1056 /* Initialize SCTLR_EL2 register with reset value. */ 1057 sctlr_el2 = SCTLR_EL2_RES1; 1058 #if ERRATA_A75_764081 1059 /* 1060 * If workaround of errata 764081 for Cortex-A75 1061 * is used then set SCTLR_EL2.IESB to enable 1062 * Implicit Error Synchronization Barrier. 1063 */ 1064 sctlr_el2 |= SCTLR_IESB_BIT; 1065 #endif 1066 write_sctlr_el2(sctlr_el2); 1067 } else { 1068 /* 1069 * (scr_el3 & SCR_HCE_BIT==0) 1070 * EL2 implemented but unused. 1071 */ 1072 init_nonsecure_el2_unused(ctx); 1073 } 1074 } 1075 } 1076 cm_el1_sysregs_context_restore(security_state); 1077 cm_set_next_eret_context(security_state); 1078 } 1079 1080 #if CTX_INCLUDE_EL2_REGS 1081 1082 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1083 { 1084 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1085 if (is_feat_amu_supported()) { 1086 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1087 } 1088 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1089 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1090 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1091 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1092 } 1093 1094 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1095 { 1096 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1097 if (is_feat_amu_supported()) { 1098 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1099 } 1100 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1101 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1102 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1103 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1104 } 1105 1106 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1107 { 1108 u_register_t mpam_idr = read_mpamidr_el1(); 1109 1110 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1111 1112 /* 1113 * The context registers that we intend to save would be part of the 1114 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1115 */ 1116 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1117 return; 1118 } 1119 1120 /* 1121 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1122 * MPAMIDR_HAS_HCR_BIT == 1. 1123 */ 1124 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1125 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1126 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1127 1128 /* 1129 * The number of MPAMVPM registers is implementation defined, their 1130 * number is stored in the MPAMIDR_EL1 register. 1131 */ 1132 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1133 case 7: 1134 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1135 __fallthrough; 1136 case 6: 1137 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1138 __fallthrough; 1139 case 5: 1140 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1141 __fallthrough; 1142 case 4: 1143 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1144 __fallthrough; 1145 case 3: 1146 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1147 __fallthrough; 1148 case 2: 1149 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1150 __fallthrough; 1151 case 1: 1152 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1153 break; 1154 } 1155 } 1156 1157 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1158 { 1159 u_register_t mpam_idr = read_mpamidr_el1(); 1160 1161 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1162 1163 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1164 return; 1165 } 1166 1167 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1168 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1169 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1170 1171 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1172 case 7: 1173 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1174 __fallthrough; 1175 case 6: 1176 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1177 __fallthrough; 1178 case 5: 1179 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1180 __fallthrough; 1181 case 4: 1182 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1183 __fallthrough; 1184 case 3: 1185 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1186 __fallthrough; 1187 case 2: 1188 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1189 __fallthrough; 1190 case 1: 1191 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1192 break; 1193 } 1194 } 1195 1196 /* --------------------------------------------------------------------------- 1197 * The following registers are not added: 1198 * ICH_AP0R<n>_EL2 1199 * ICH_AP1R<n>_EL2 1200 * ICH_LR<n>_EL2 1201 * 1202 * NOTE: For a system with S-EL2 present but not enabled, accessing 1203 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1204 * SCR_EL3.NS = 1 before accessing this register. 1205 * --------------------------------------------------------------------------- 1206 */ 1207 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1208 { 1209 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1210 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1211 #else 1212 u_register_t scr_el3 = read_scr_el3(); 1213 write_scr_el3(scr_el3 | SCR_NS_BIT); 1214 isb(); 1215 1216 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1217 1218 write_scr_el3(scr_el3); 1219 isb(); 1220 #endif 1221 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1222 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1223 } 1224 1225 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1226 { 1227 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1228 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1229 #else 1230 u_register_t scr_el3 = read_scr_el3(); 1231 write_scr_el3(scr_el3 | SCR_NS_BIT); 1232 isb(); 1233 1234 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1235 1236 write_scr_el3(scr_el3); 1237 isb(); 1238 #endif 1239 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1240 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1241 } 1242 1243 /* ----------------------------------------------------- 1244 * The following registers are not added: 1245 * AMEVCNTVOFF0<n>_EL2 1246 * AMEVCNTVOFF1<n>_EL2 1247 * ----------------------------------------------------- 1248 */ 1249 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1250 { 1251 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1252 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1253 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1254 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1255 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1256 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1257 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1258 if (CTX_INCLUDE_AARCH32_REGS) { 1259 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1260 } 1261 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1262 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1263 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1264 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1265 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1266 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1267 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1268 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1269 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1270 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1271 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1272 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1273 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1274 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1275 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1276 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1277 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1278 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1279 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1280 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1281 } 1282 1283 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1284 { 1285 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1286 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1287 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1288 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1289 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1290 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1291 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1292 if (CTX_INCLUDE_AARCH32_REGS) { 1293 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1294 } 1295 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1296 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1297 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1298 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1299 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1300 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1301 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1302 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1303 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1304 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1305 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1306 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1307 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1308 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1309 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1310 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1311 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1312 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1313 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1314 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1315 } 1316 1317 /******************************************************************************* 1318 * Save EL2 sysreg context 1319 ******************************************************************************/ 1320 void cm_el2_sysregs_context_save(uint32_t security_state) 1321 { 1322 cpu_context_t *ctx; 1323 el2_sysregs_t *el2_sysregs_ctx; 1324 1325 ctx = cm_get_context(security_state); 1326 assert(ctx != NULL); 1327 1328 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1329 1330 el2_sysregs_context_save_common(el2_sysregs_ctx); 1331 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1332 1333 if (is_feat_mte2_supported()) { 1334 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1335 } 1336 1337 if (is_feat_mpam_supported()) { 1338 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1339 } 1340 1341 if (is_feat_fgt_supported()) { 1342 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1343 } 1344 1345 if (is_feat_ecv_v2_supported()) { 1346 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1347 } 1348 1349 if (is_feat_vhe_supported()) { 1350 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1351 read_contextidr_el2()); 1352 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1353 } 1354 1355 if (is_feat_ras_supported()) { 1356 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1357 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1358 } 1359 1360 if (is_feat_nv2_supported()) { 1361 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1362 } 1363 1364 if (is_feat_trf_supported()) { 1365 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1366 } 1367 1368 if (is_feat_csv2_2_supported()) { 1369 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1370 read_scxtnum_el2()); 1371 } 1372 1373 if (is_feat_hcx_supported()) { 1374 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1375 } 1376 1377 if (is_feat_tcr2_supported()) { 1378 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1379 } 1380 1381 if (is_feat_sxpie_supported()) { 1382 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1383 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1384 } 1385 1386 if (is_feat_sxpoe_supported()) { 1387 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1388 } 1389 1390 if (is_feat_s2pie_supported()) { 1391 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1392 } 1393 1394 if (is_feat_gcs_supported()) { 1395 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1396 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1397 } 1398 } 1399 1400 /******************************************************************************* 1401 * Restore EL2 sysreg context 1402 ******************************************************************************/ 1403 void cm_el2_sysregs_context_restore(uint32_t security_state) 1404 { 1405 cpu_context_t *ctx; 1406 el2_sysregs_t *el2_sysregs_ctx; 1407 1408 ctx = cm_get_context(security_state); 1409 assert(ctx != NULL); 1410 1411 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1412 1413 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1414 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1415 1416 if (is_feat_mte2_supported()) { 1417 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1418 } 1419 1420 if (is_feat_mpam_supported()) { 1421 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1422 } 1423 1424 if (is_feat_fgt_supported()) { 1425 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1426 } 1427 1428 if (is_feat_ecv_v2_supported()) { 1429 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1430 } 1431 1432 if (is_feat_vhe_supported()) { 1433 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1434 contextidr_el2)); 1435 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1436 } 1437 1438 if (is_feat_ras_supported()) { 1439 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1440 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1441 } 1442 1443 if (is_feat_nv2_supported()) { 1444 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1445 } 1446 1447 if (is_feat_trf_supported()) { 1448 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1449 } 1450 1451 if (is_feat_csv2_2_supported()) { 1452 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1453 scxtnum_el2)); 1454 } 1455 1456 if (is_feat_hcx_supported()) { 1457 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1458 } 1459 1460 if (is_feat_tcr2_supported()) { 1461 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1462 } 1463 1464 if (is_feat_sxpie_supported()) { 1465 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1466 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1467 } 1468 1469 if (is_feat_sxpoe_supported()) { 1470 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1471 } 1472 1473 if (is_feat_s2pie_supported()) { 1474 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1475 } 1476 1477 if (is_feat_gcs_supported()) { 1478 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1479 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1480 } 1481 } 1482 #endif /* CTX_INCLUDE_EL2_REGS */ 1483 1484 /******************************************************************************* 1485 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1486 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1487 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1488 * cm_prepare_el3_exit function. 1489 ******************************************************************************/ 1490 void cm_prepare_el3_exit_ns(void) 1491 { 1492 #if CTX_INCLUDE_EL2_REGS 1493 #if ENABLE_ASSERTIONS 1494 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1495 assert(ctx != NULL); 1496 1497 /* Assert that EL2 is used. */ 1498 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1499 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1500 (el_implemented(2U) != EL_IMPL_NONE)); 1501 #endif /* ENABLE_ASSERTIONS */ 1502 1503 /* Restore EL2 and EL1 sysreg contexts */ 1504 cm_el2_sysregs_context_restore(NON_SECURE); 1505 cm_el1_sysregs_context_restore(NON_SECURE); 1506 cm_set_next_eret_context(NON_SECURE); 1507 #else 1508 cm_prepare_el3_exit(NON_SECURE); 1509 #endif /* CTX_INCLUDE_EL2_REGS */ 1510 } 1511 1512 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1513 { 1514 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1515 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1516 1517 #if !ERRATA_SPECULATIVE_AT 1518 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1519 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1520 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1521 1522 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1523 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1524 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1525 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1526 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1527 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1528 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1529 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1530 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1531 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1532 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1533 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1534 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1535 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1536 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1537 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1538 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1539 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1540 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1541 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1542 1543 #if CTX_INCLUDE_AARCH32_REGS 1544 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1545 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1546 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1547 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1548 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1549 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1550 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1551 1552 #if NS_TIMER_SWITCH 1553 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1554 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1555 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1556 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1557 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1558 #endif /* NS_TIMER_SWITCH */ 1559 1560 #if ENABLE_FEAT_MTE2 1561 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1562 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1563 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1564 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1565 #endif /* ENABLE_FEAT_MTE2 */ 1566 1567 #if ENABLE_FEAT_RAS 1568 if (is_feat_ras_supported()) { 1569 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1570 } 1571 #endif 1572 1573 #if ENABLE_FEAT_S1PIE 1574 if (is_feat_s1pie_supported()) { 1575 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1576 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1577 } 1578 #endif 1579 1580 #if ENABLE_FEAT_S1POE 1581 if (is_feat_s1poe_supported()) { 1582 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1583 } 1584 #endif 1585 1586 #if ENABLE_FEAT_S2POE 1587 if (is_feat_s2poe_supported()) { 1588 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1589 } 1590 #endif 1591 1592 #if ENABLE_FEAT_TCR2 1593 if (is_feat_tcr2_supported()) { 1594 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1595 } 1596 #endif 1597 1598 #if ENABLE_TRF_FOR_NS 1599 if (is_feat_trf_supported()) { 1600 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1601 } 1602 #endif 1603 1604 #if ENABLE_FEAT_CSV2_2 1605 if (is_feat_csv2_2_supported()) { 1606 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1607 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1608 } 1609 #endif 1610 1611 #if ENABLE_FEAT_GCS 1612 if (is_feat_gcs_supported()) { 1613 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1614 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1615 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1616 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1617 } 1618 #endif 1619 } 1620 1621 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1622 { 1623 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1624 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1625 1626 #if !ERRATA_SPECULATIVE_AT 1627 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1628 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1629 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1630 1631 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1632 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1633 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1634 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1635 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1636 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1637 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1638 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1639 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1640 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1641 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1642 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1643 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1644 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1645 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1646 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1647 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1648 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1649 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1650 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1651 1652 #if CTX_INCLUDE_AARCH32_REGS 1653 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1654 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1655 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1656 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1657 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1658 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1659 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1660 1661 #if NS_TIMER_SWITCH 1662 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1663 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1664 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1665 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1666 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1667 #endif /* NS_TIMER_SWITCH */ 1668 1669 #if ENABLE_FEAT_MTE2 1670 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1671 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1672 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1673 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1674 #endif /* ENABLE_FEAT_MTE2 */ 1675 1676 #if ENABLE_FEAT_RAS 1677 if (is_feat_ras_supported()) { 1678 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1679 } 1680 #endif 1681 1682 #if ENABLE_FEAT_S1PIE 1683 if (is_feat_s1pie_supported()) { 1684 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1685 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1686 } 1687 #endif 1688 1689 #if ENABLE_FEAT_S1POE 1690 if (is_feat_s1poe_supported()) { 1691 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1692 } 1693 #endif 1694 1695 #if ENABLE_FEAT_S2POE 1696 if (is_feat_s2poe_supported()) { 1697 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1698 } 1699 #endif 1700 1701 #if ENABLE_FEAT_TCR2 1702 if (is_feat_tcr2_supported()) { 1703 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1704 } 1705 #endif 1706 1707 #if ENABLE_TRF_FOR_NS 1708 if (is_feat_trf_supported()) { 1709 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1710 } 1711 #endif 1712 1713 #if ENABLE_FEAT_CSV2_2 1714 if (is_feat_csv2_2_supported()) { 1715 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1716 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1717 } 1718 #endif 1719 1720 #if ENABLE_FEAT_GCS 1721 if (is_feat_gcs_supported()) { 1722 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1723 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1724 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1725 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1726 } 1727 #endif 1728 } 1729 1730 /******************************************************************************* 1731 * The next four functions are used by runtime services to save and restore 1732 * EL1 context on the 'cpu_context' structure for the specified security 1733 * state. 1734 ******************************************************************************/ 1735 void cm_el1_sysregs_context_save(uint32_t security_state) 1736 { 1737 cpu_context_t *ctx; 1738 1739 ctx = cm_get_context(security_state); 1740 assert(ctx != NULL); 1741 1742 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1743 1744 #if IMAGE_BL31 1745 if (security_state == SECURE) 1746 PUBLISH_EVENT(cm_exited_secure_world); 1747 else 1748 PUBLISH_EVENT(cm_exited_normal_world); 1749 #endif 1750 } 1751 1752 void cm_el1_sysregs_context_restore(uint32_t security_state) 1753 { 1754 cpu_context_t *ctx; 1755 1756 ctx = cm_get_context(security_state); 1757 assert(ctx != NULL); 1758 1759 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1760 1761 #if IMAGE_BL31 1762 if (security_state == SECURE) 1763 PUBLISH_EVENT(cm_entering_secure_world); 1764 else 1765 PUBLISH_EVENT(cm_entering_normal_world); 1766 #endif 1767 } 1768 1769 /******************************************************************************* 1770 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1771 * given security state with the given entrypoint 1772 ******************************************************************************/ 1773 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1774 { 1775 cpu_context_t *ctx; 1776 el3_state_t *state; 1777 1778 ctx = cm_get_context(security_state); 1779 assert(ctx != NULL); 1780 1781 /* Populate EL3 state so that ERET jumps to the correct entry */ 1782 state = get_el3state_ctx(ctx); 1783 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1784 } 1785 1786 /******************************************************************************* 1787 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1788 * pertaining to the given security state 1789 ******************************************************************************/ 1790 void cm_set_elr_spsr_el3(uint32_t security_state, 1791 uintptr_t entrypoint, uint32_t spsr) 1792 { 1793 cpu_context_t *ctx; 1794 el3_state_t *state; 1795 1796 ctx = cm_get_context(security_state); 1797 assert(ctx != NULL); 1798 1799 /* Populate EL3 state so that ERET jumps to the correct entry */ 1800 state = get_el3state_ctx(ctx); 1801 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1802 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1803 } 1804 1805 /******************************************************************************* 1806 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1807 * pertaining to the given security state using the value and bit position 1808 * specified in the parameters. It preserves all other bits. 1809 ******************************************************************************/ 1810 void cm_write_scr_el3_bit(uint32_t security_state, 1811 uint32_t bit_pos, 1812 uint32_t value) 1813 { 1814 cpu_context_t *ctx; 1815 el3_state_t *state; 1816 u_register_t scr_el3; 1817 1818 ctx = cm_get_context(security_state); 1819 assert(ctx != NULL); 1820 1821 /* Ensure that the bit position is a valid one */ 1822 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1823 1824 /* Ensure that the 'value' is only a bit wide */ 1825 assert(value <= 1U); 1826 1827 /* 1828 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1829 * and set it to its new value. 1830 */ 1831 state = get_el3state_ctx(ctx); 1832 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1833 scr_el3 &= ~(1UL << bit_pos); 1834 scr_el3 |= (u_register_t)value << bit_pos; 1835 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1836 } 1837 1838 /******************************************************************************* 1839 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1840 * given security state. 1841 ******************************************************************************/ 1842 u_register_t cm_get_scr_el3(uint32_t security_state) 1843 { 1844 cpu_context_t *ctx; 1845 el3_state_t *state; 1846 1847 ctx = cm_get_context(security_state); 1848 assert(ctx != NULL); 1849 1850 /* Populate EL3 state so that ERET jumps to the correct entry */ 1851 state = get_el3state_ctx(ctx); 1852 return read_ctx_reg(state, CTX_SCR_EL3); 1853 } 1854 1855 /******************************************************************************* 1856 * This function is used to program the context that's used for exception 1857 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1858 * the required security state 1859 ******************************************************************************/ 1860 void cm_set_next_eret_context(uint32_t security_state) 1861 { 1862 cpu_context_t *ctx; 1863 1864 ctx = cm_get_context(security_state); 1865 assert(ctx != NULL); 1866 1867 cm_set_next_context(ctx); 1868 } 1869