1/* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 30 /* dsb before isb of power down sequence */ 31 dsb sy 32workaround_runtime_end cortex_x4, ERRATUM(2740089) 33 34check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 35 36workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 37 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 38workaround_reset_end cortex_x4, ERRATUM(2763018) 39 40check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 41 42workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 43 mrs x1, id_aa64pfr1_el1 44 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 45 cbz x2, #1f 46 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 471: 48workaround_reset_end cortex_x4, ERRATUM(2816013) 49 50check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 51 52workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 53#if IMAGE_BL31 54 /* 55 * The Cortex X4 generic vectors are overridden to apply errata 56 * mitigation on exception entry from lower ELs. 57 */ 58 override_vector_table wa_cve_vbar_cortex_x4 59#endif /* IMAGE_BL31 */ 60workaround_reset_end cortex_x4, CVE(2022, 23960) 61 62check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 63 64cpu_reset_func_start cortex_x4 65 /* Disable speculative loads */ 66 msr SSBS, xzr 67cpu_reset_func_end cortex_x4 68 69 /* ---------------------------------------------------- 70 * HW will do the cache maintenance while powering down 71 * ---------------------------------------------------- 72 */ 73func cortex_x4_core_pwr_dwn 74 /* --------------------------------------------------- 75 * Enable CPU power down bit in power control register 76 * --------------------------------------------------- 77 */ 78 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 79 80 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 81 82 isb 83 ret 84endfunc cortex_x4_core_pwr_dwn 85 86errata_report_shim cortex_x4 87 88 /* --------------------------------------------- 89 * This function provides Cortex X4-specific 90 * register information for crash reporting. 91 * It needs to return with x6 pointing to 92 * a list of register names in ascii and 93 * x8 - x15 having values of registers to be 94 * reported. 95 * --------------------------------------------- 96 */ 97.section .rodata.cortex_x4_regs, "aS" 98cortex_x4_regs: /* The ascii list of register names to be reported */ 99 .asciz "cpuectlr_el1", "" 100 101func cortex_x4_cpu_reg_dump 102 adr x6, cortex_x4_regs 103 mrs x8, CORTEX_X4_CPUECTLR_EL1 104 ret 105endfunc cortex_x4_cpu_reg_dump 106 107declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 108 cortex_x4_reset_func, \ 109 cortex_x4_core_pwr_dwn 110