1# 2# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14ENABLE_PIE := 1 15PROGRAMMABLE_RESET_ADDRESS := 1 16BL2_IN_XIP_MEM := 1 17 18# Default Device tree 19DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 20 21STM32MP25 := 1 22 23# STM32 image header version v2.2 24STM32_HEADER_VERSION_MAJOR := 2 25STM32_HEADER_VERSION_MINOR := 2 26 27# Set load address for serial boot devices 28DWL_BUFFER_BASE ?= 0x87000000 29 30# DDR types 31STM32MP_DDR3_TYPE ?= 0 32STM32MP_DDR4_TYPE ?= 0 33STM32MP_LPDDR4_TYPE ?= 0 34ifeq (${STM32MP_DDR3_TYPE},1) 35DDR_TYPE := ddr3 36endif 37ifeq (${STM32MP_DDR4_TYPE},1) 38DDR_TYPE := ddr4 39endif 40ifeq (${STM32MP_LPDDR4_TYPE},1) 41DDR_TYPE := lpddr4 42endif 43 44# DDR features 45STM32MP_DDR_DUAL_AXI_PORT := 1 46STM32MP_DDR_FIP_IO_STORAGE := 1 47 48# Device tree 49BL2_DTSI := stm32mp25-bl2.dtsi 50FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 51 52# Macros and rules to build TF binary 53STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 54STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 55STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 56 57STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 58STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 59ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 60STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 61STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 62STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 63endif 64FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 65# Add the FW_CONFIG to FIP and specify the same to certtool 66$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 67ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 68# Add the FW_DDR to FIP and specify the same to certtool 69$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 70endif 71 72# Enable flags for C files 73$(eval $(call assert_booleans,\ 74 $(sort \ 75 STM32MP_DDR_DUAL_AXI_PORT \ 76 STM32MP_DDR_FIP_IO_STORAGE \ 77 STM32MP_DDR3_TYPE \ 78 STM32MP_DDR4_TYPE \ 79 STM32MP_LPDDR4_TYPE \ 80 STM32MP25 \ 81))) 82 83$(eval $(call assert_numerics,\ 84 $(sort \ 85 PLAT_PARTITION_MAX_ENTRIES \ 86 STM32_HEADER_VERSION_MAJOR \ 87 STM32_TF_A_COPIES \ 88))) 89 90$(eval $(call add_defines,\ 91 $(sort \ 92 DWL_BUFFER_BASE \ 93 PLAT_DEF_FIP_UUID \ 94 PLAT_PARTITION_MAX_ENTRIES \ 95 PLAT_TBBR_IMG_DEF \ 96 STM32_TF_A_COPIES \ 97 STM32MP_DDR_DUAL_AXI_PORT \ 98 STM32MP_DDR_FIP_IO_STORAGE \ 99 STM32MP_DDR3_TYPE \ 100 STM32MP_DDR4_TYPE \ 101 STM32MP_LPDDR4_TYPE \ 102 STM32MP25 \ 103))) 104 105# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 106# Disable mbranch-protection to avoid adding useless code 107TF_CFLAGS += -mbranch-protection=none 108 109# Include paths and source files 110PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 111PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 112PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 113 114PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 115PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 116PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 117 118PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 119 drivers/st/pmic/stpmic2.c \ 120 121PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 122 123PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 124 125PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 126 drivers/st/reset/stm32mp2_reset.c \ 127 plat/st/stm32mp2/stm32mp2_syscfg.c 128 129PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 130 drivers/st/clk/clk-stm32mp2.c 131 132BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 133 134BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 135 plat/st/stm32mp2/plat_ddr.c 136 137ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 138BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 139endif 140 141ifeq (${STM32MP_USB_PROGRAMMER},1) 142BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 143endif 144 145BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 146 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 147 drivers/st/ddr/stm32mp2_ram.c 148 149BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 150 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 151 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 152 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 153 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 154 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 155 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 156 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 157 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 158 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 159 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 160 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 161 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 162 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 163 164BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 165 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 166 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 167 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 168 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 169 170# BL31 sources 171BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 172 173BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 174 plat/st/stm32mp2/stm32mp2_pm.c \ 175 plat/st/stm32mp2/stm32mp2_topology.c 176# Generic GIC v2 177include drivers/arm/gic/v2/gicv2.mk 178 179BL31_SOURCES += ${GICV2_SOURCES} \ 180 plat/common/plat_gicv2.c \ 181 plat/st/common/stm32mp_gic.c 182 183# Generic PSCI 184BL31_SOURCES += plat/common/plat_psci_common.c 185 186# Compilation rules 187.PHONY: check_ddr_type 188.SUFFIXES: 189 190bl2: check_ddr_type 191 192check_ddr_type: 193 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 194 $(STM32MP_DDR4_TYPE) + \ 195 $(STM32MP_LPDDR4_TYPE))))) 196 @if [ ${DDR_TYPE} != 1 ]; then \ 197 echo "One and only one DDR type must be defined"; \ 198 false; \ 199 fi 200 201include plat/st/common/common_rules.mk 202