1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_pl011 1 22 #define VERSAL_CONSOLE_ID_pl011_0 1 23 #define VERSAL_CONSOLE_ID_pl011_1 2 24 #define VERSAL_CONSOLE_ID_dcc 3 25 26 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27 28 /* List of platforms */ 29 #define VERSAL_SILICON U(0) 30 #define VERSAL_SPP U(1) 31 #define VERSAL_EMU U(2) 32 #define VERSAL_QEMU U(3) 33 #define VERSAL_COSIM U(7) 34 35 /* Firmware Image Package */ 36 #define VERSAL_PRIMARY_CPU 0 37 38 /******************************************************************************* 39 * memory map related constants 40 ******************************************************************************/ 41 #define DEVICE0_BASE 0xFF000000 42 #define DEVICE0_SIZE 0x00E00000 43 #define DEVICE1_BASE 0xF9000000 44 #define DEVICE1_SIZE 0x00800000 45 46 /******************************************************************************* 47 * IRQ constants 48 ******************************************************************************/ 49 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 50 #define ARM_IRQ_SEC_PHY_TIMER 29 51 52 /******************************************************************************* 53 * CCI-400 related constants 54 ******************************************************************************/ 55 #define PLAT_ARM_CCI_BASE 0xFD000000 56 #define PLAT_ARM_CCI_SIZE 0x00100000 57 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 58 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 59 60 /******************************************************************************* 61 * UART related constants 62 ******************************************************************************/ 63 #define VERSAL_UART0_BASE 0xFF000000 64 #define VERSAL_UART1_BASE 0xFF010000 65 66 #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 67 # define UART_BASE VERSAL_UART0_BASE 68 #elif CONSOLE_IS(pl011_1) 69 # define UART_BASE VERSAL_UART1_BASE 70 #else 71 # error "invalid VERSAL_CONSOLE" 72 #endif 73 74 /******************************************************************************* 75 * Platform related constants 76 ******************************************************************************/ 77 #define UART_BAUDRATE 115200 78 79 /* Access control register defines */ 80 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 81 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 82 83 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 84 #define CRF_BASE 0xFD1A0000 85 #define CRF_SIZE 0x00600000 86 87 /* CRF registers and bitfields */ 88 #define CRF_RST_APU (CRF_BASE + 0X00000300) 89 90 #define CRF_RST_APU_ACPU_RESET (1 << 0) 91 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 92 93 /* IOU SCNTRS */ 94 #define IOU_SCNTRS_BASE U(0xFF140000) 95 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 96 97 /* APU registers and bitfields */ 98 #define FPD_APU_BASE 0xFD5C0000U 99 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 100 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 101 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 102 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 103 104 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 105 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 106 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 107 108 /* PMC registers and bitfields */ 109 #define PMC_GLOBAL_BASE 0xF1110000U 110 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 111 112 #endif /* VERSAL_DEF_H */ 113