1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50endif 51endif 52 53 ENABLE_BRBE_FOR_NS := 2 54 ENABLE_TRBE_FOR_NS := 2 55endif 56 57ENABLE_SYS_REG_TRACE_FOR_NS := 2 58ENABLE_FEAT_CSV2_2 := 2 59ENABLE_FEAT_CSV2_3 := 2 60ENABLE_FEAT_DEBUGV8P9 := 2 61ENABLE_FEAT_DIT := 2 62ENABLE_FEAT_PAN := 2 63ENABLE_FEAT_VHE := 2 64CTX_INCLUDE_NEVE_REGS := 2 65ENABLE_FEAT_SEL2 := 2 66ENABLE_TRF_FOR_NS := 2 67ENABLE_FEAT_ECV := 2 68ENABLE_FEAT_FGT := 2 69ENABLE_FEAT_TCR2 := 2 70ENABLE_FEAT_S2PIE := 2 71ENABLE_FEAT_S1PIE := 2 72ENABLE_FEAT_S2POE := 2 73ENABLE_FEAT_S1POE := 2 74 75# The FVP platform depends on this macro to build with correct GIC driver. 76$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 77 78# Pass FVP_CLUSTER_COUNT to the build system. 79$(eval $(call add_define,FVP_CLUSTER_COUNT)) 80 81# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 82$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 83 84# Pass FVP_MAX_PE_PER_CPU to the build system. 85$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 86 87# Pass FVP_GICR_REGION_PROTECTION to the build system. 88$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 89 90# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 91$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 92 93# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 94# choose the CCI driver , else the CCN driver 95ifeq ($(FVP_CLUSTER_COUNT), 0) 96$(error "Incorrect cluster count specified for FVP port") 97else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 98FVP_INTERCONNECT_DRIVER := FVP_CCI 99else 100FVP_INTERCONNECT_DRIVER := FVP_CCN 101endif 102 103$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 104 105# Choose the GIC sources depending upon the how the FVP will be invoked 106ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 107 108# The GIC model (GIC-600 or GIC-500) will be detected at runtime 109GICV3_SUPPORT_GIC600 := 1 110GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 111 112# Include GICv3 driver files 113include drivers/arm/gic/v3/gicv3.mk 114 115FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 116 plat/common/plat_gicv3.c \ 117 plat/arm/common/arm_gicv3.c 118 119 ifeq ($(filter 1,${RESET_TO_BL2} \ 120 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 121 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 122 endif 123 124else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 125 126# No GICv4 extension 127GIC_ENABLE_V4_EXTN := 0 128$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 129 130# Include GICv2 driver files 131include drivers/arm/gic/v2/gicv2.mk 132 133FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 134 plat/common/plat_gicv2.c \ 135 plat/arm/common/arm_gicv2.c 136 137FVP_DT_PREFIX := fvp-base-gicv2-psci 138else 139$(error "Incorrect GIC driver chosen on FVP port") 140endif 141 142ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 143FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 144else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 145FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 146 plat/arm/common/arm_ccn.c 147else 148$(error "Incorrect CCN driver chosen on FVP port") 149endif 150 151FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 152 plat/arm/board/fvp/fvp_security.c \ 153 plat/arm/common/arm_tzc400.c 154 155 156PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 157 -Iinclude/lib/psa 158 159 160PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 161 162FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 163 164ifeq (${ARCH}, aarch64) 165 166# select a different set of CPU files, depending on whether we compile for 167# hardware assisted coherency cores or not 168ifeq (${HW_ASSISTED_COHERENCY}, 0) 169# Cores used without DSU 170 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 171 lib/cpus/aarch64/cortex_a53.S \ 172 lib/cpus/aarch64/cortex_a57.S \ 173 lib/cpus/aarch64/cortex_a72.S \ 174 lib/cpus/aarch64/cortex_a73.S 175else 176# Cores used with DSU only 177 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 178 # AArch64-only cores 179 # TODO: add all cores to the appropriate lists 180 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 181 lib/cpus/aarch64/cortex_a65ae.S \ 182 lib/cpus/aarch64/cortex_a76.S \ 183 lib/cpus/aarch64/cortex_a76ae.S \ 184 lib/cpus/aarch64/cortex_a77.S \ 185 lib/cpus/aarch64/cortex_a78.S \ 186 lib/cpus/aarch64/cortex_a78_ae.S \ 187 lib/cpus/aarch64/cortex_a78c.S \ 188 lib/cpus/aarch64/cortex_a710.S \ 189 lib/cpus/aarch64/cortex_a715.S \ 190 lib/cpus/aarch64/cortex_a720.S \ 191 lib/cpus/aarch64/neoverse_n_common.S \ 192 lib/cpus/aarch64/neoverse_n1.S \ 193 lib/cpus/aarch64/neoverse_n2.S \ 194 lib/cpus/aarch64/neoverse_v1.S \ 195 lib/cpus/aarch64/neoverse_e1.S \ 196 lib/cpus/aarch64/cortex_x2.S \ 197 lib/cpus/aarch64/cortex_x4.S 198 endif 199 # AArch64/AArch32 cores 200 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 201 lib/cpus/aarch64/cortex_a75.S 202endif 203 204#Build AArch64-only CPUs with no FVP model yet. 205ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 206 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 207 lib/cpus/aarch64/cortex_gelas.S \ 208 lib/cpus/aarch64/nevis.S \ 209 lib/cpus/aarch64/travis.S 210endif 211 212else 213FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 214 lib/cpus/aarch32/cortex_a57.S \ 215 lib/cpus/aarch32/cortex_a53.S 216endif 217 218BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 219 drivers/arm/sp805/sp805.c \ 220 drivers/delay_timer/delay_timer.c \ 221 drivers/io/io_semihosting.c \ 222 lib/semihosting/semihosting.c \ 223 lib/semihosting/${ARCH}/semihosting_call.S \ 224 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 225 plat/arm/board/fvp/fvp_bl1_setup.c \ 226 plat/arm/board/fvp/fvp_cpu_pwr.c \ 227 plat/arm/board/fvp/fvp_err.c \ 228 plat/arm/board/fvp/fvp_io_storage.c \ 229 plat/arm/board/fvp/fvp_topology.c \ 230 ${FVP_CPU_LIBS} \ 231 ${FVP_INTERCONNECT_SOURCES} 232 233ifeq (${USE_SP804_TIMER},1) 234BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 235else 236BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 237endif 238 239 240BL2_SOURCES += drivers/arm/sp805/sp805.c \ 241 drivers/io/io_semihosting.c \ 242 lib/utils/mem_region.c \ 243 lib/semihosting/semihosting.c \ 244 lib/semihosting/${ARCH}/semihosting_call.S \ 245 plat/arm/board/fvp/fvp_bl2_setup.c \ 246 plat/arm/board/fvp/fvp_err.c \ 247 plat/arm/board/fvp/fvp_io_storage.c \ 248 plat/arm/common/arm_nor_psci_mem_protect.c \ 249 ${FVP_SECURITY_SOURCES} 250 251 252ifeq (${COT_DESC_IN_DTB},1) 253BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 254endif 255 256ifeq (${ENABLE_RME},1) 257BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 258 plat/arm/board/fvp/fvp_cpu_pwr.c 259 260BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 261 plat/arm/board/fvp/fvp_realm_attest_key.c 262endif 263 264ifeq (${ENABLE_FEAT_RNG_TRAP},1) 265BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 266endif 267 268ifeq (${RESET_TO_BL2},1) 269BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 270 plat/arm/board/fvp/fvp_cpu_pwr.c \ 271 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 272 ${FVP_CPU_LIBS} \ 273 ${FVP_INTERCONNECT_SOURCES} 274endif 275 276ifeq (${USE_SP804_TIMER},1) 277BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 278endif 279 280BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 281 ${FVP_SECURITY_SOURCES} 282 283ifeq (${USE_SP804_TIMER},1) 284BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 285endif 286 287BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 288 drivers/arm/smmu/smmu_v3.c \ 289 drivers/delay_timer/delay_timer.c \ 290 drivers/cfi/v2m/v2m_flash.c \ 291 lib/utils/mem_region.c \ 292 plat/arm/board/fvp/fvp_bl31_setup.c \ 293 plat/arm/board/fvp/fvp_console.c \ 294 plat/arm/board/fvp/fvp_pm.c \ 295 plat/arm/board/fvp/fvp_topology.c \ 296 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 297 plat/arm/board/fvp/fvp_cpu_pwr.c \ 298 plat/arm/common/arm_nor_psci_mem_protect.c \ 299 ${FVP_CPU_LIBS} \ 300 ${FVP_GIC_SOURCES} \ 301 ${FVP_INTERCONNECT_SOURCES} \ 302 ${FVP_SECURITY_SOURCES} 303 304# Support for fconf in BL31 305# Added separately from the above list for better readability 306ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 307BL31_SOURCES += lib/fconf/fconf.c \ 308 lib/fconf/fconf_dyn_cfg_getter.c \ 309 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 310 311BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 312 313ifeq (${SEC_INT_DESC_IN_FCONF},1) 314BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 315endif 316 317endif 318 319ifeq (${USE_SP804_TIMER},1) 320BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 321else 322BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 323endif 324 325ifeq (${TRANSFER_LIST}, 1) 326include lib/transfer_list/transfer_list.mk 327endif 328 329# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 330ifdef UNIX_MK 331FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 332FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 333 334FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 335$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 336 337ifeq (${TRANSFER_LIST}, 1) 338FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 339 ${PLAT}_tb_fw_config.dts \ 340 ) 341else 342FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 343 ${PLAT}_fw_config.dts \ 344 ${PLAT}_tb_fw_config.dts \ 345 ${PLAT}_soc_fw_config.dts \ 346 ${PLAT}_nt_fw_config.dts \ 347 ) 348 349FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 350FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 351FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 352 353ifeq (${SPD},tspd) 354FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 355FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 356 357# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 358$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 359endif 360 361ifeq (${SPD},spmd) 362 363ifeq ($(ARM_SPMC_MANIFEST_DTS),) 364ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 365endif 366 367FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 368FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 369 370# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 372endif 373 374# Add the FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 376# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 378# Add the NT_FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 380endif 381 382# Add the TB_FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 384# Add the HW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 386endif 387 388# Enable dynamic mitigation support by default 389DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 390 391ifneq (${ENABLE_FEAT_AMU},0) 392BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 393 lib/cpus/aarch64/cpuamu_helpers.S 394 395ifeq (${HW_ASSISTED_COHERENCY}, 1) 396BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 397 lib/cpus/aarch64/neoverse_n1_pubsub.c 398endif 399endif 400 401ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 402 ifeq (${ENABLE_FEAT_RAS},1) 403 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 404 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 405 else 406 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 407 endif 408 else 409 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 410 endif 411endif 412 413ifneq (${ENABLE_STACK_PROTECTOR},0) 414PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 415endif 416 417# Enable the dynamic translation tables library. 418ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 419 ifeq (${ARCH},aarch32) 420 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 421 else # AArch64 422 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 423 endif 424endif 425 426ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 427 ifeq (${ARCH},aarch32) 428 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 429 else # AArch64 430 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 431 ifeq (${SPD},tspd) 432 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 433 endif 434 endif 435endif 436 437ifeq (${USE_DEBUGFS},1) 438 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 439endif 440 441# Add support for platform supplied linker script for BL31 build 442$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 443 444ifneq (${RESET_TO_BL2}, 0) 445 override BL1_SOURCES = 446endif 447 448include plat/arm/board/common/board_common.mk 449include plat/arm/common/arm_common.mk 450 451ifeq (${MEASURED_BOOT},1) 452BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 453 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 454 lib/psa/measured_boot.c 455 456BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 457 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 458 lib/psa/measured_boot.c 459endif 460 461ifeq (${DRTM_SUPPORT}, 1) 462BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 463 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 464 plat/arm/board/fvp/fvp_drtm_err.c \ 465 plat/arm/board/fvp/fvp_drtm_measurement.c \ 466 plat/arm/board/fvp/fvp_drtm_stub.c \ 467 plat/arm/common/arm_dyn_cfg.c \ 468 plat/arm/board/fvp/fvp_err.c 469endif 470 471ifeq (${TRUSTED_BOARD_BOOT}, 1) 472BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 473BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 474 475# FVP being a development platform, enable capability to disable Authentication 476# dynamically if TRUSTED_BOARD_BOOT is set. 477DYN_DISABLE_AUTH := 1 478endif 479 480ifeq (${SPMC_AT_EL3}, 1) 481PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 482endif 483 484PSCI_OS_INIT_MODE := 1 485 486ifeq (${SPD},spmd) 487BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 488endif 489 490# Test specific macros, keep them at bottom of this file 491$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 492ifeq (${PLATFORM_TEST_EA_FFH}, 1) 493 ifeq (${FFH_SUPPORT}, 0) 494 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 495 endif 496 497endif 498 499$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 500ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 501 ifeq (${ENABLE_FEAT_RAS}, 0) 502 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 503 endif 504 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 505 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 506 endif 507endif 508 509$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 510ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 511 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 512 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 513 endif 514 ifeq (${ENABLE_SPMD_LP}, 0) 515 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 516 endif 517 ifeq (${ENABLE_FEAT_RAS}, 0) 518 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 519 endif 520 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 521 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 522 endif 523endif 524 525ifeq (${ERRATA_ABI_SUPPORT}, 1) 526include plat/arm/board/fvp/fvp_cpu_errata.mk 527endif 528 529# Build macro necessary for running SPM tests on FVP platform 530$(eval $(call add_define,PLAT_TEST_SPM)) 531