| 9979a20a | 27-Sep-2025 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
feat(rcar): deduplicate SCIF console_rcar_register
The console_rcar_register assembler macro is functionally identical between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.
Signed-off-by
feat(rcar): deduplicate SCIF console_rcar_register
The console_rcar_register assembler macro is functionally identical between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Change-Id: Ib498832dbed9063efdb9979e89e53d119303d9df
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| 4f7e0fa3 | 01-Dec-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
fix(rcar3): fix load address range check
Fixed the check of the address range which the program is loaded to. Use the addresses and sizes in the BL31 and BL32 certificates to check that they are wit
fix(rcar3): fix load address range check
Fixed the check of the address range which the program is loaded to. Use the addresses and sizes in the BL31 and BL32 certificates to check that they are within the range of the target address and size defined inside the TF-A. It also uses the addresses and sizes in the BL33x certificates to check that they are outside the protected area defined inside the TF-A.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Code clean up Change-Id: Iade15431fc86587489fb0ca9106f6baaf7e926e2
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| b469880e | 03-Jul-2023 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
fix(rcar3-drivers): check "rcar_image_number" variable before use
Validate the content of rcar_image_number variable before use.
Reviewed-by: Tomer Fichman <Tomer.Fichman@cymotive.com> Signed-off-b
fix(rcar3-drivers): check "rcar_image_number" variable before use
Validate the content of rcar_image_number variable before use.
Reviewed-by: Tomer Fichman <Tomer.Fichman@cymotive.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ieeabafa8f709d25eebc4a8e490bf623ef32ccf9f
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| 9778b270 | 07-Mar-2023 |
Tobias Rist <tobias.rist@joynext.com> |
fix(rcar3-drivers): check for length underflow
Make sure the length of the payload is not longer than the DRAM size in check_load_area(), and make sure the payload end does not cross protected area
fix(rcar3-drivers): check for length underflow
Make sure the length of the payload is not longer than the DRAM size in check_load_area(), and make sure the payload end does not cross protected area start.
Signed-off-by: Tobias Rist <tobias.rist@joynext.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I4d687be577a138352be9f92e5b0b6f596ffffba9
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| ef38fb1f | 23-Apr-2023 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
fix(rcar3-drivers): add integer overflow check
Check against overflows while calculating the "len" variable.
Reviewed-by: Tomer Fichman <Tomer.Fichman@cymotive.com> Signed-off-by: Yoshifumi Hosoya
fix(rcar3-drivers): add integer overflow check
Check against overflows while calculating the "len" variable.
Reviewed-by: Tomer Fichman <Tomer.Fichman@cymotive.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I0c50152a04365c6f52e0db3096e27e8a800c59ea
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| 90c4b3b6 | 22-Nov-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(renesas): align incompatible function pointers
secure_boot_api_f is defined to take uint32_t, uint32_t, and void * parameters. However rom_secure_boot_api_f is defined to take uint32_t *, uint32
fix(renesas): align incompatible function pointers
secure_boot_api_f is defined to take uint32_t, uint32_t, and void * parameters. However rom_secure_boot_api_f is defined to take uint32_t *, uint32_t *, void *. These are incompatible and cause a warning when compiling with -Wextra. Align the rom definition to the more generic definition from where it's called.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ia030803b3c2335d220aff09fc0eef5c7615276aa
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| ffb725be | 02-Nov-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
feat(plat/rcar3): modify type for Internal function argument
Modify the type of the variable that stores the value for MPIDR in the internal function from uint64_t to u_register_t.
Signed-off-by: K
feat(plat/rcar3): modify type for Internal function argument
Modify the type of the variable that stores the value for MPIDR in the internal function from uint64_t to u_register_t.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
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| d9912cf3 | 02-Nov-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
Add new function so that the value of bit at WUPMSKCA57/53, which points to CPU other than the BOOT CPU, is 1 at initialization.
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
Add new function so that the value of bit at WUPMSKCA57/53, which points to CPU other than the BOOT CPU, is 1 at initialization. Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is basically 0 and target bit value is changed to 1 only when CPU_OFF.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
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| 49593cc1 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9
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| c77ab18e | 13-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(plat/rcar): fix cache maintenance process of reading cert header
Move calling inv_dcache_range from before io_read to after that.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> S
fix(plat/rcar): fix cache maintenance process of reading cert header
Move calling inv_dcache_range from before io_read to after that.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ic0dabf3eb94eeeb04099ed5127cdfda79bbac9b3
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| 993d809c | 20-Mar-2021 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
feat(drivers/rcar3): add extra offset if booting B-side
In case MFISBTSTSR bit 4 is 1, that means the loader was started as B-side. Load the remaining boot components from 8 MiB offset.
Signed-off-
feat(drivers/rcar3): add extra offset if booting B-side
In case MFISBTSTSR bit 4 is 1, that means the loader was started as B-side. Load the remaining boot components from 8 MiB offset.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10
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| 053c1346 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
Modified the SWDT counter setting for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Oga
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
Modified the SWDT counter setting for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If1fa12bf644486f3fad3c6b54cda6c4cbb604103
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| 042d710d | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.o
feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432
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| 14f0a081 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): add process of SSCG setting for R-Car D3
- Added the condition where output the SSCG (MD12) setting to log for R-Car D3. - Added the process to switching the bit rate of SCIF by
feat(plat/rcar3): add process of SSCG setting for R-Car D3
- Added the condition where output the SSCG (MD12) setting to log for R-Car D3. - Added the process to switching the bit rate of SCIF by the SSCG (MD12) setting value for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
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