1 /* 2 * Copyright (c) 2018-2023, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 #include <stdint.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <bl1/bl1.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <common/desc_image_load.h> 20 #include <common/image_decompress.h> 21 #include <drivers/console.h> 22 #include <drivers/io/io_driver.h> 23 #include <drivers/io/io_storage.h> 24 #include <lib/mmio.h> 25 #include <lib/xlat_tables/xlat_tables_defs.h> 26 #include <plat/common/platform.h> 27 #if RCAR_GEN3_BL33_GZIP == 1 28 #include <tf_gunzip.h> 29 #endif 30 31 #include "avs_driver.h" 32 #include "boot_init_dram.h" 33 #include "cpg_registers.h" 34 #include "board.h" 35 #include "emmc_def.h" 36 #include "emmc_hal.h" 37 #include "emmc_std.h" 38 39 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 40 #include "iic_dvfs.h" 41 #endif 42 43 #include "io_common.h" 44 #include "io_rcar.h" 45 #include "qos_init.h" 46 #include "rcar_def.h" 47 #include "rcar_private.h" 48 #include "rcar_version.h" 49 #include "rom_api.h" 50 51 #if RCAR_BL2_DCACHE == 1 52 /* 53 * Following symbols are only used during plat_arch_setup() only 54 * when RCAR_BL2_DCACHE is enabled. 55 */ 56 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 57 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 58 59 #if USE_COHERENT_MEM 60 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 61 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 62 #endif 63 64 #endif 65 66 extern void plat_rcar_gic_driver_init(void); 67 extern void plat_rcar_gic_init(void); 68 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 69 extern void bl2_system_cpg_init(void); 70 extern void bl2_secure_setting(void); 71 extern void bl2_cpg_init(void); 72 extern void rcar_io_emmc_setup(void); 73 extern void rcar_io_setup(void); 74 extern void rcar_swdt_release(void); 75 extern void rcar_swdt_init(void); 76 extern void rcar_rpc_init(void); 77 extern void rcar_pfc_init(void); 78 extern void rcar_dma_init(void); 79 80 static void bl2_init_generic_timer(void); 81 82 /* R-Car Gen3 product check */ 83 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 84 #define TARGET_PRODUCT PRR_PRODUCT_H3 85 #define TARGET_NAME "R-Car H3" 86 #elif RCAR_LSI == RCAR_M3 87 #define TARGET_PRODUCT PRR_PRODUCT_M3 88 #define TARGET_NAME "R-Car M3" 89 #elif RCAR_LSI == RCAR_M3N 90 #define TARGET_PRODUCT PRR_PRODUCT_M3N 91 #define TARGET_NAME "R-Car M3N" 92 #elif RCAR_LSI == RCAR_V3M 93 #define TARGET_PRODUCT PRR_PRODUCT_V3M 94 #define TARGET_NAME "R-Car V3M" 95 #elif RCAR_LSI == RCAR_E3 96 #define TARGET_PRODUCT PRR_PRODUCT_E3 97 #define TARGET_NAME "R-Car E3" 98 #elif RCAR_LSI == RCAR_D3 99 #define TARGET_PRODUCT PRR_PRODUCT_D3 100 #define TARGET_NAME "R-Car D3" 101 #elif RCAR_LSI == RCAR_AUTO 102 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 103 #endif 104 105 #if (RCAR_LSI == RCAR_E3) 106 #define GPIO_INDT (GPIO_INDT6) 107 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 108 #else 109 #define GPIO_INDT (GPIO_INDT1) 110 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 111 #endif 112 113 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 114 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 115 assert_bl31_params_do_not_fit_in_shared_memory); 116 117 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 118 119 /* FDT with DRAM configuration */ 120 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 121 static void *fdt = (void *)fdt_blob; 122 123 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 124 char *string) 125 { 126 /* Just need enough space to store 64 bit decimal integer */ 127 char num_buf[20]; 128 int i = 0; 129 unsigned int rem; 130 131 do { 132 rem = unum % radix; 133 if (rem < 0xa) 134 num_buf[i] = '0' + rem; 135 else 136 num_buf[i] = 'a' + (rem - 0xa); 137 i++; 138 unum /= radix; 139 } while (unum > 0U); 140 141 while (--i >= 0) 142 *string++ = num_buf[i]; 143 *string = 0; 144 } 145 146 #if (RCAR_LOSSY_ENABLE == 1) 147 typedef struct bl2_lossy_info { 148 uint32_t magic; 149 uint32_t a0; 150 uint32_t b0; 151 } bl2_lossy_info_t; 152 153 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 154 uint64_t end_addr, uint32_t format, 155 uint32_t enable, int fcnlnode) 156 { 157 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 158 char nodename[40] = { 0 }; 159 int ret, node; 160 161 /* Ignore undefined addresses */ 162 if (start_addr == 0 && end_addr == 0) 163 return; 164 165 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 166 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 167 168 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 169 if (ret < 0) { 170 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 171 panic(); 172 } 173 174 ret = fdt_setprop_string(fdt, node, "compatible", 175 "renesas,lossy-decompression"); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_appendprop_string(fdt, node, "compatible", 182 "shared-dma-pool"); 183 if (ret < 0) { 184 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 185 panic(); 186 } 187 188 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 189 if (ret < 0) { 190 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 191 panic(); 192 } 193 194 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 195 if (ret < 0) { 196 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 197 panic(); 198 } 199 200 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 201 if (ret < 0) { 202 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 203 panic(); 204 } 205 206 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 207 if (ret < 0) { 208 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 209 panic(); 210 } 211 } 212 213 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 214 uint64_t end_addr, uint32_t format, 215 uint32_t enable, int fcnlnode) 216 { 217 bl2_lossy_info_t info; 218 uint32_t reg; 219 220 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 221 222 reg = format | (start_addr >> 20); 223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 224 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 225 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 226 227 info.magic = 0x12345678U; 228 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 229 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 230 231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 232 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 233 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 234 235 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 236 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 237 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 238 } 239 240 static int bl2_create_reserved_memory(void) 241 { 242 int ret; 243 244 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 245 if (fcnlnode < 0) { 246 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 247 fcnlnode); 248 panic(); 249 } 250 251 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0); 252 if (ret < 0) { 253 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret); 254 panic(); 255 } 256 257 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2); 258 if (ret < 0) { 259 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret); 260 panic(); 261 } 262 263 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2); 264 if (ret < 0) { 265 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret); 266 panic(); 267 } 268 269 return fcnlnode; 270 } 271 272 static void bl2_create_fcnl_reserved_memory(void) 273 { 274 int fcnlnode; 275 276 NOTICE("BL2: Lossy Decomp areas\n"); 277 278 fcnlnode = bl2_create_reserved_memory(); 279 280 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 281 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 282 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 283 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 284 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 285 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 286 } 287 #else 288 static void bl2_create_fcnl_reserved_memory(void) {} 289 #endif 290 291 void bl2_plat_flush_bl31_params(void) 292 { 293 uint32_t product_cut, product, cut; 294 uint32_t boot_dev, boot_cpu; 295 uint32_t lcs, reg, val; 296 297 reg = mmio_read_32(RCAR_MODEMR); 298 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 299 300 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 301 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 302 emmc_terminate(); 303 304 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 305 bl2_secure_setting(); 306 307 reg = mmio_read_32(RCAR_PRR); 308 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 309 product = reg & PRR_PRODUCT_MASK; 310 cut = reg & PRR_CUT_MASK; 311 312 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 313 goto tlb; 314 315 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 316 goto tlb; 317 318 /* Disable MFIS write protection */ 319 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 320 321 tlb: 322 reg = mmio_read_32(RCAR_MODEMR); 323 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 324 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 325 boot_cpu != MODEMR_BOOT_CPU_CA53) 326 goto mmu; 327 328 if (product_cut == PRR_PRODUCT_H3_CUT20) { 329 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 330 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 331 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 332 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 333 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 334 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 335 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 336 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 337 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 338 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 339 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 340 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 341 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 342 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 343 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 344 } 345 346 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 347 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 348 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 349 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 350 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 351 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 352 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 353 354 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 355 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 356 } 357 358 mmu: 359 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 360 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 361 362 val = rcar_rom_get_lcs(&lcs); 363 if (val) { 364 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 365 panic(); 366 } 367 368 if (lcs == LCS_SE) 369 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 370 371 rcar_swdt_release(); 372 bl2_system_cpg_init(); 373 374 #if RCAR_BL2_DCACHE == 1 375 /* Disable data cache (clean and invalidate) */ 376 disable_mmu_el3(); 377 #endif 378 } 379 380 static uint32_t is_ddr_backup_mode(void) 381 { 382 #if RCAR_SYSTEM_SUSPEND 383 static uint32_t reason = RCAR_COLD_BOOT; 384 static uint32_t once; 385 386 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 387 uint8_t data; 388 #endif 389 if (once) 390 return reason; 391 392 once = 1; 393 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 394 return reason; 395 396 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 397 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 398 ERROR("BL2: REG Keep10 READ ERROR.\n"); 399 panic(); 400 } 401 402 if (KEEP10_MAGIC != data) 403 reason = RCAR_WARM_BOOT; 404 #else 405 reason = RCAR_WARM_BOOT; 406 #endif 407 return reason; 408 #else 409 return RCAR_COLD_BOOT; 410 #endif 411 } 412 413 #if RCAR_GEN3_BL33_GZIP == 1 414 void bl2_plat_preload_setup(void) 415 { 416 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); 417 } 418 #endif 419 420 static uint64_t check_secure_load_area(uintptr_t base, uint32_t size, 421 uintptr_t dest, uint32_t len) 422 { 423 uintptr_t free_end, requested_end; 424 425 /* 426 * Handle corner cases first. 427 * 428 * The order of the 2 tests is important, because if there's no space 429 * left (i.e. free_size == 0) but we don't ask for any memory 430 * (i.e. size == 0) then we should report that the memory is free. 431 */ 432 if (len == 0U) { 433 WARN("BL2: load data size is zero\n"); 434 return 0; /* A zero-byte region is always free */ 435 } 436 if (size == 0U) { 437 goto err; 438 } 439 440 /* 441 * Check that the end addresses don't overflow. 442 * If they do, consider that this memory region is not free, as this 443 * is an invalid scenario. 444 */ 445 if (check_uptr_overflow(base, size - 1U)) { 446 goto err; 447 } 448 free_end = base + (size - 1U); 449 450 if (check_uptr_overflow(dest, len - 1U)) { 451 goto err; 452 } 453 requested_end = dest + (len - 1U); 454 455 /* 456 * Finally, check that the requested memory region lies within the free 457 * region. 458 */ 459 if ((dest < base) || (requested_end > free_end)) { 460 goto err; 461 } 462 463 return 0; 464 465 err: 466 ERROR("BL2: load data is outside the loadable area.\n"); 467 ERROR("BL2: dst=0x%lx, len=%d(0x%x)\n", dest, len, len); 468 return 1; 469 } 470 471 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest, 472 uint32_t *len) 473 { 474 uint32_t cert; 475 int ret; 476 477 ret = rcar_get_certificate(certid, &cert); 478 if (ret) { 479 ERROR("%s : cert file load error", __func__); 480 return 1; 481 } 482 483 rcar_read_certificate((uint64_t) cert, len, dest); 484 485 return 0; 486 } 487 488 int bl2_plat_handle_pre_image_load(unsigned int image_id) 489 { 490 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 491 bl_mem_params_node_t *bl_mem_params; 492 uintptr_t dev_handle; 493 uintptr_t image_spec; 494 uintptr_t dest; 495 uint32_t len; 496 uint64_t ui64_ret; 497 int iret; 498 499 bl_mem_params = get_bl_mem_params_node(image_id); 500 if (bl_mem_params == NULL) { 501 ERROR("BL2: Failed to get loading parameter.\n"); 502 return 1; 503 } 504 505 switch (image_id) { 506 case BL31_IMAGE_ID: 507 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) { 508 iret = plat_get_image_source(image_id, &dev_handle, 509 &image_spec); 510 if (iret != 0) { 511 return 1; 512 } 513 514 ui64_ret = rcar_get_dest_addr_from_cert( 515 SOC_FW_CONTENT_CERT_ID, &dest, &len); 516 if (ui64_ret != 0U) { 517 return 1; 518 } 519 520 ui64_ret = check_secure_load_area( 521 BL31_BASE, BL31_LIMIT - BL31_BASE, 522 dest, len); 523 if (ui64_ret != 0U) { 524 return 1; 525 } 526 527 *boot_kind = RCAR_COLD_BOOT; 528 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 529 530 bl_mem_params->image_info.image_base = dest; 531 bl_mem_params->image_info.image_size = len; 532 } else { 533 *boot_kind = RCAR_WARM_BOOT; 534 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 535 536 console_flush(); 537 bl2_plat_flush_bl31_params(); 538 539 /* will not return */ 540 bl2_enter_bl31(&bl_mem_params->ep_info); 541 } 542 543 return 0; 544 #ifndef SPD_NONE 545 case BL32_IMAGE_ID: 546 ui64_ret = rcar_get_dest_addr_from_cert( 547 TRUSTED_OS_FW_CONTENT_CERT_ID, &dest, &len); 548 if (ui64_ret != 0U) { 549 return 1; 550 } 551 552 ui64_ret = check_secure_load_area( 553 BL32_BASE, BL32_LIMIT - BL32_BASE, dest, len); 554 if (ui64_ret != 0U) { 555 return 1; 556 } 557 558 bl_mem_params->image_info.image_base = dest; 559 bl_mem_params->image_info.image_size = len; 560 561 return 0; 562 #endif 563 case BL33_IMAGE_ID: 564 /* case of image_id == BL33_IMAGE_ID */ 565 ui64_ret = rcar_get_dest_addr_from_cert( 566 NON_TRUSTED_FW_CONTENT_CERT_ID, 567 &dest, &len); 568 569 if (ui64_ret != 0U) { 570 return 1; 571 } 572 573 #if RCAR_GEN3_BL33_GZIP == 1 574 image_decompress_prepare(&bl_mem_params->image_info); 575 #endif 576 577 return 0; 578 default: 579 return 1; 580 } 581 582 return 0; 583 } 584 585 int bl2_plat_handle_post_image_load(unsigned int image_id) 586 { 587 static bl2_to_bl31_params_mem_t *params; 588 bl_mem_params_node_t *bl_mem_params; 589 590 if (!params) { 591 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 592 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 593 } 594 595 bl_mem_params = get_bl_mem_params_node(image_id); 596 if (!bl_mem_params) { 597 ERROR("BL2: Failed to get loading parameter.\n"); 598 return 1; 599 } 600 601 switch (image_id) { 602 case BL31_IMAGE_ID: 603 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 604 return 0; 605 case BL32_IMAGE_ID: 606 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 607 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 608 sizeof(entry_point_info_t)); 609 return 0; 610 case BL33_IMAGE_ID: 611 #if RCAR_GEN3_BL33_GZIP == 1 612 int ret; 613 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { 614 /* decompress gzip-compressed image */ 615 ret = image_decompress(&bl_mem_params->image_info); 616 if (ret != 0) { 617 return ret; 618 } 619 } else { 620 /* plain image, copy it in place */ 621 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, 622 bl_mem_params->image_info.image_size); 623 } 624 #endif 625 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 626 sizeof(entry_point_info_t)); 627 return 0; 628 default: 629 return 1; 630 } 631 632 return 0; 633 } 634 635 struct meminfo *bl2_plat_sec_mem_layout(void) 636 { 637 return &bl2_tzram_layout; 638 } 639 640 static void bl2_populate_compatible_string(void *dt) 641 { 642 uint32_t board_type; 643 uint32_t board_rev; 644 uint32_t reg; 645 int ret; 646 647 fdt_setprop_u32(dt, 0, "#address-cells", 2); 648 fdt_setprop_u32(dt, 0, "#size-cells", 2); 649 650 /* Populate compatible string */ 651 rcar_get_board_type(&board_type, &board_rev); 652 switch (board_type) { 653 case BOARD_SALVATOR_X: 654 ret = fdt_setprop_string(dt, 0, "compatible", 655 "renesas,salvator-x"); 656 break; 657 case BOARD_SALVATOR_XS: 658 ret = fdt_setprop_string(dt, 0, "compatible", 659 "renesas,salvator-xs"); 660 break; 661 case BOARD_STARTER_KIT: 662 ret = fdt_setprop_string(dt, 0, "compatible", 663 "renesas,m3ulcb"); 664 break; 665 case BOARD_STARTER_KIT_PRE: 666 ret = fdt_setprop_string(dt, 0, "compatible", 667 "renesas,h3ulcb"); 668 break; 669 case BOARD_EAGLE: 670 ret = fdt_setprop_string(dt, 0, "compatible", 671 "renesas,eagle"); 672 break; 673 case BOARD_EBISU: 674 case BOARD_EBISU_4D: 675 ret = fdt_setprop_string(dt, 0, "compatible", 676 "renesas,ebisu"); 677 break; 678 case BOARD_DRAAK: 679 ret = fdt_setprop_string(dt, 0, "compatible", 680 "renesas,draak"); 681 break; 682 default: 683 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 684 panic(); 685 } 686 687 if (ret < 0) { 688 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 689 panic(); 690 } 691 692 reg = mmio_read_32(RCAR_PRR); 693 switch (reg & PRR_PRODUCT_MASK) { 694 case PRR_PRODUCT_H3: 695 ret = fdt_appendprop_string(dt, 0, "compatible", 696 "renesas,r8a7795"); 697 break; 698 case PRR_PRODUCT_M3: 699 ret = fdt_appendprop_string(dt, 0, "compatible", 700 "renesas,r8a7796"); 701 break; 702 case PRR_PRODUCT_M3N: 703 ret = fdt_appendprop_string(dt, 0, "compatible", 704 "renesas,r8a77965"); 705 break; 706 case PRR_PRODUCT_V3M: 707 ret = fdt_appendprop_string(dt, 0, "compatible", 708 "renesas,r8a77970"); 709 break; 710 case PRR_PRODUCT_E3: 711 ret = fdt_appendprop_string(dt, 0, "compatible", 712 "renesas,r8a77990"); 713 break; 714 case PRR_PRODUCT_D3: 715 ret = fdt_appendprop_string(dt, 0, "compatible", 716 "renesas,r8a77995"); 717 break; 718 default: 719 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 720 panic(); 721 } 722 723 if (ret < 0) { 724 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 725 panic(); 726 } 727 } 728 729 static void bl2_add_rpc_node(void) 730 { 731 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0) 732 int ret, node; 733 734 node = ret = fdt_add_subnode(fdt, 0, "soc"); 735 if (ret < 0) { 736 goto err; 737 } 738 739 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000"); 740 if (ret < 0) { 741 goto err; 742 } 743 744 ret = fdt_setprop_string(fdt, node, "status", "okay"); 745 if (ret < 0) { 746 goto err; 747 } 748 749 return; 750 err: 751 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret); 752 panic(); 753 #endif 754 } 755 756 static void bl2_add_dram_entry(uint64_t start, uint64_t size) 757 { 758 char nodename[32] = { 0 }; 759 uint64_t fdtsize; 760 int ret, node; 761 762 fdtsize = cpu_to_fdt64(size); 763 764 snprintf(nodename, sizeof(nodename), "memory@"); 765 unsigned_num_print(start, 16, nodename + strlen(nodename)); 766 node = ret = fdt_add_subnode(fdt, 0, nodename); 767 if (ret < 0) { 768 goto err; 769 } 770 771 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 772 if (ret < 0) { 773 goto err; 774 } 775 776 ret = fdt_setprop_u64(fdt, node, "reg", start); 777 if (ret < 0) { 778 goto err; 779 } 780 781 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 782 sizeof(fdtsize)); 783 if (ret < 0) { 784 goto err; 785 } 786 787 return; 788 err: 789 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n", 790 start, start + size - 1, ret); 791 panic(); 792 } 793 794 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 795 { 796 uint64_t start, size, size32; 797 int chan; 798 799 for (chan = 0; chan < 4; chan++) { 800 start = dram_config[2 * chan]; 801 size = dram_config[2 * chan + 1]; 802 if (!size) 803 continue; 804 805 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n", 806 chan, start, start + size - 1, 807 (size >> 30) ? : size >> 20, 808 (size >> 30) ? "G" : "M"); 809 } 810 811 /* 812 * We add the DT nodes in reverse order here. The fdt_add_subnode() 813 * adds the DT node before the first existing DT node, so we have 814 * to add them in reverse order to get nodes sorted by address in 815 * the resulting DT. 816 */ 817 for (chan = 3; chan >= 0; chan--) { 818 start = dram_config[2 * chan]; 819 size = dram_config[2 * chan + 1]; 820 if (!size) 821 continue; 822 823 /* 824 * Channel 0 is mapped in 32bit space and the first 825 * 128 MiB are reserved and the maximum size is 2GiB. 826 */ 827 if (chan == 0) { 828 /* Limit the 32bit entry to 2 GiB - 128 MiB */ 829 size32 = size - 0x8000000U; 830 if (size32 >= 0x78000000U) { 831 size32 = 0x78000000U; 832 } 833 834 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */ 835 bl2_add_dram_entry(0x48000000, size32); 836 837 /* 838 * If channel 0 is less than 2 GiB long, the 839 * entire memory fits into the 32bit space entry, 840 * so move on to the next channel. 841 */ 842 if (size <= 0x80000000U) { 843 continue; 844 } 845 846 /* 847 * If channel 0 is more than 2 GiB long, emit 848 * another entry which covers the rest of the 849 * memory in channel 0, in the 64bit space. 850 * 851 * Start of this new entry is at 2 GiB offset 852 * from the beginning of the 64bit channel 0 853 * address, size is 2 GiB shorter than total 854 * size of the channel. 855 */ 856 start += 0x80000000U; 857 size -= 0x80000000U; 858 } 859 860 bl2_add_dram_entry(start, size); 861 } 862 } 863 864 static void bl2_advertise_dram_size(uint32_t product) 865 { 866 uint64_t dram_config[8] = { 867 [0] = 0x400000000ULL, 868 [2] = 0x500000000ULL, 869 [4] = 0x600000000ULL, 870 [6] = 0x700000000ULL, 871 }; 872 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 873 874 switch (product) { 875 case PRR_PRODUCT_H3: 876 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 877 /* 4GB(1GBx4) */ 878 dram_config[1] = 0x40000000ULL; 879 dram_config[3] = 0x40000000ULL; 880 dram_config[5] = 0x40000000ULL; 881 dram_config[7] = 0x40000000ULL; 882 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 883 (RCAR_DRAM_CHANNEL == 5) && \ 884 (RCAR_DRAM_SPLIT == 2) 885 /* 4GB(2GBx2 2ch split) */ 886 dram_config[1] = 0x80000000ULL; 887 dram_config[3] = 0x80000000ULL; 888 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 889 /* 8GB(2GBx4: default) */ 890 dram_config[1] = 0x80000000ULL; 891 dram_config[3] = 0x80000000ULL; 892 dram_config[5] = 0x80000000ULL; 893 dram_config[7] = 0x80000000ULL; 894 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 895 break; 896 897 case PRR_PRODUCT_M3: 898 if (cut < PRR_PRODUCT_30) { 899 #if (RCAR_GEN3_ULCB == 1) 900 /* 2GB(1GBx2 2ch split) */ 901 dram_config[1] = 0x40000000ULL; 902 dram_config[5] = 0x40000000ULL; 903 #else 904 /* 4GB(2GBx2 2ch split) */ 905 dram_config[1] = 0x80000000ULL; 906 dram_config[5] = 0x80000000ULL; 907 #endif 908 } else { 909 /* 8GB(2GBx4 2ch split) */ 910 dram_config[1] = 0x100000000ULL; 911 dram_config[5] = 0x100000000ULL; 912 } 913 break; 914 915 case PRR_PRODUCT_M3N: 916 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) 917 /* 4GB(4GBx1) */ 918 dram_config[1] = 0x100000000ULL; 919 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) 920 /* 2GB(1GBx2) */ 921 dram_config[1] = 0x80000000ULL; 922 #endif 923 break; 924 925 case PRR_PRODUCT_V3M: 926 /* 1GB(512MBx2) */ 927 dram_config[1] = 0x40000000ULL; 928 break; 929 930 case PRR_PRODUCT_E3: 931 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 932 /* 1GB(512MBx2) */ 933 dram_config[1] = 0x40000000ULL; 934 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 935 /* 2GB(512MBx4) */ 936 dram_config[1] = 0x80000000ULL; 937 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 938 /* 4GB(1GBx4) */ 939 dram_config[1] = 0x100000000ULL; 940 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 941 break; 942 943 case PRR_PRODUCT_D3: 944 /* 512MB */ 945 dram_config[1] = 0x20000000ULL; 946 break; 947 } 948 949 bl2_advertise_dram_entries(dram_config); 950 } 951 952 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 953 u_register_t arg3, u_register_t arg4) 954 { 955 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 956 uint32_t product, product_cut, major, minor; 957 int32_t ret; 958 const char *str; 959 const char *unknown = "unknown"; 960 const char *cpu_ca57 = "CA57"; 961 const char *cpu_ca53 = "CA53"; 962 const char *product_m3n = "M3N"; 963 const char *product_h3 = "H3"; 964 const char *product_m3 = "M3"; 965 const char *product_e3 = "E3"; 966 const char *product_d3 = "D3"; 967 const char *product_v3m = "V3M"; 968 const char *lcs_secure = "SE"; 969 const char *lcs_cm = "CM"; 970 const char *lcs_dm = "DM"; 971 const char *lcs_sd = "SD"; 972 const char *lcs_fa = "FA"; 973 const char *sscg_off = "PLL1 nonSSCG Clock select"; 974 const char *sscg_on = "PLL1 SSCG Clock select"; 975 const char *boot_hyper80 = "HyperFlash(80MHz)"; 976 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 977 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 978 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 979 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 980 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 981 const char *boot_hyper160 = "HyperFlash(150MHz)"; 982 #else 983 const char *boot_hyper160 = "HyperFlash(160MHz)"; 984 #endif 985 986 bl2_init_generic_timer(); 987 988 reg = mmio_read_32(RCAR_MODEMR); 989 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 990 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 991 992 bl2_cpg_init(); 993 994 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 995 boot_cpu == MODEMR_BOOT_CPU_CA53) { 996 rcar_pfc_init(); 997 rcar_console_boot_init(); 998 } 999 1000 plat_rcar_gic_driver_init(); 1001 plat_rcar_gic_init(); 1002 rcar_swdt_init(); 1003 1004 /* FIQ interrupts are taken to EL3 */ 1005 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 1006 1007 write_daifclr(DAIF_FIQ_BIT); 1008 1009 reg = read_midr(); 1010 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 1011 switch (midr) { 1012 case MIDR_CA57: 1013 str = cpu_ca57; 1014 break; 1015 case MIDR_CA53: 1016 str = cpu_ca53; 1017 break; 1018 default: 1019 str = unknown; 1020 break; 1021 } 1022 1023 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 1024 version_of_renesas); 1025 1026 reg = mmio_read_32(RCAR_PRR); 1027 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1028 product = reg & PRR_PRODUCT_MASK; 1029 1030 switch (product) { 1031 case PRR_PRODUCT_H3: 1032 str = product_h3; 1033 break; 1034 case PRR_PRODUCT_M3: 1035 str = product_m3; 1036 break; 1037 case PRR_PRODUCT_M3N: 1038 str = product_m3n; 1039 break; 1040 case PRR_PRODUCT_V3M: 1041 str = product_v3m; 1042 break; 1043 case PRR_PRODUCT_E3: 1044 str = product_e3; 1045 break; 1046 case PRR_PRODUCT_D3: 1047 str = product_d3; 1048 break; 1049 default: 1050 str = unknown; 1051 break; 1052 } 1053 1054 if ((PRR_PRODUCT_M3 == product) && 1055 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 1056 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 1057 /* M3 Ver.1.1 or Ver.1.2 */ 1058 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 1059 str); 1060 } else { 1061 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 1062 str, 1063 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 1064 } 1065 } else if (product == PRR_PRODUCT_D3) { 1066 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) { 1067 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str); 1068 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 1069 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str); 1070 } else { 1071 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str); 1072 } 1073 } else { 1074 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 1075 major = major + RCAR_MAJOR_OFFSET; 1076 minor = reg & RCAR_MINOR_MASK; 1077 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 1078 } 1079 1080 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) { 1081 reg = mmio_read_32(RCAR_MODEMR); 1082 sscg = reg & RCAR_SSCG_MASK; 1083 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 1084 NOTICE("BL2: %s\n", str); 1085 } 1086 1087 rcar_get_board_type(&type, &rev); 1088 1089 switch (type) { 1090 case BOARD_SALVATOR_X: 1091 case BOARD_KRIEK: 1092 case BOARD_STARTER_KIT: 1093 case BOARD_SALVATOR_XS: 1094 case BOARD_EBISU: 1095 case BOARD_STARTER_KIT_PRE: 1096 case BOARD_EBISU_4D: 1097 case BOARD_DRAAK: 1098 case BOARD_EAGLE: 1099 break; 1100 default: 1101 type = BOARD_UNKNOWN; 1102 break; 1103 } 1104 1105 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 1106 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 1107 else { 1108 NOTICE("BL2: Board is %s Rev.%d.%d\n", 1109 GET_BOARD_NAME(type), 1110 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 1111 } 1112 1113 #if RCAR_LSI != RCAR_AUTO 1114 if (product != TARGET_PRODUCT) { 1115 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 1116 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 1117 panic(); 1118 } 1119 #endif 1120 rcar_avs_init(); 1121 rcar_avs_setting(); 1122 1123 switch (boot_dev) { 1124 case MODEMR_BOOT_DEV_HYPERFLASH160: 1125 str = boot_hyper160; 1126 break; 1127 case MODEMR_BOOT_DEV_HYPERFLASH80: 1128 str = boot_hyper80; 1129 break; 1130 case MODEMR_BOOT_DEV_QSPI_FLASH40: 1131 str = boot_qspi40; 1132 break; 1133 case MODEMR_BOOT_DEV_QSPI_FLASH80: 1134 str = boot_qspi80; 1135 break; 1136 case MODEMR_BOOT_DEV_EMMC_25X1: 1137 #if RCAR_LSI == RCAR_D3 1138 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 1139 panic(); 1140 #endif 1141 str = boot_emmc25x1; 1142 break; 1143 case MODEMR_BOOT_DEV_EMMC_50X8: 1144 str = boot_emmc50x8; 1145 break; 1146 default: 1147 str = unknown; 1148 break; 1149 } 1150 NOTICE("BL2: Boot device is %s\n", str); 1151 1152 rcar_avs_setting(); 1153 reg = rcar_rom_get_lcs(&lcs); 1154 if (reg) { 1155 str = unknown; 1156 goto lcm_state; 1157 } 1158 1159 switch (lcs) { 1160 case LCS_CM: 1161 str = lcs_cm; 1162 break; 1163 case LCS_DM: 1164 str = lcs_dm; 1165 break; 1166 case LCS_SD: 1167 str = lcs_sd; 1168 break; 1169 case LCS_SE: 1170 str = lcs_secure; 1171 break; 1172 case LCS_FA: 1173 str = lcs_fa; 1174 break; 1175 default: 1176 str = unknown; 1177 break; 1178 } 1179 1180 lcm_state: 1181 NOTICE("BL2: LCM state is %s\n", str); 1182 1183 rcar_avs_end(); 1184 is_ddr_backup_mode(); 1185 1186 bl2_tzram_layout.total_base = BL31_BASE; 1187 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 1188 1189 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 1190 boot_cpu == MODEMR_BOOT_CPU_CA53) { 1191 ret = rcar_dram_init(); 1192 if (ret) { 1193 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 1194 panic(); 1195 } 1196 rcar_qos_init(); 1197 } 1198 1199 /* Set up FDT */ 1200 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 1201 if (ret) { 1202 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 1203 panic(); 1204 } 1205 1206 /* Add platform compatible string */ 1207 bl2_populate_compatible_string(fdt); 1208 1209 /* Enable RPC if unlocked */ 1210 bl2_add_rpc_node(); 1211 1212 /* Print DRAM layout */ 1213 bl2_advertise_dram_size(product); 1214 1215 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1216 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 1217 if (rcar_emmc_init() != EMMC_SUCCESS) { 1218 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 1219 panic(); 1220 } 1221 rcar_emmc_memcard_power(EMMC_POWER_ON); 1222 if (rcar_emmc_mount() != EMMC_SUCCESS) { 1223 NOTICE("BL2: Failed to eMMC mount operation.\n"); 1224 panic(); 1225 } 1226 } else { 1227 rcar_rpc_init(); 1228 rcar_dma_init(); 1229 } 1230 1231 reg = mmio_read_32(RST_WDTRSTCR); 1232 reg &= ~WDTRSTCR_RWDT_RSTMSK; 1233 reg |= WDTRSTCR_PASSWORD; 1234 mmio_write_32(RST_WDTRSTCR, reg); 1235 1236 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 1237 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 1238 1239 reg = mmio_read_32(RCAR_PRR); 1240 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 1241 mmio_write_32(CPG_CA57DBGRCR, 1242 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 1243 1244 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 1245 mmio_write_32(CPG_CA53DBGRCR, 1246 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 1247 1248 if (product_cut == PRR_PRODUCT_H3_CUT10) { 1249 reg = mmio_read_32(CPG_PLL2CR); 1250 reg &= ~((uint32_t) 1 << 5); 1251 mmio_write_32(CPG_PLL2CR, reg); 1252 1253 reg = mmio_read_32(CPG_PLL4CR); 1254 reg &= ~((uint32_t) 1 << 5); 1255 mmio_write_32(CPG_PLL4CR, reg); 1256 1257 reg = mmio_read_32(CPG_PLL0CR); 1258 reg &= ~((uint32_t) 1 << 12); 1259 mmio_write_32(CPG_PLL0CR, reg); 1260 } 1261 1262 bl2_create_fcnl_reserved_memory(); 1263 1264 fdt_pack(fdt); 1265 NOTICE("BL2: FDT at %p\n", fdt); 1266 1267 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1268 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1269 rcar_io_emmc_setup(); 1270 else 1271 rcar_io_setup(); 1272 } 1273 1274 void bl2_el3_plat_arch_setup(void) 1275 { 1276 #if RCAR_BL2_DCACHE == 1 1277 NOTICE("BL2: D-Cache enable\n"); 1278 rcar_configure_mmu_el3(BL2_BASE, 1279 BL2_END - BL2_BASE, 1280 BL2_RO_BASE, BL2_RO_LIMIT 1281 #if USE_COHERENT_MEM 1282 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1283 #endif 1284 ); 1285 #endif 1286 } 1287 1288 void bl2_platform_setup(void) 1289 { 1290 1291 } 1292 1293 static void bl2_init_generic_timer(void) 1294 { 1295 /* FIXME: V3M 16.666 MHz ? */ 1296 #if RCAR_LSI == RCAR_D3 1297 uint32_t reg_cntfid = EXTAL_DRAAK; 1298 #elif RCAR_LSI == RCAR_E3 1299 uint32_t reg_cntfid = EXTAL_EBISU; 1300 #else /* RCAR_LSI == RCAR_E3 */ 1301 uint32_t reg; 1302 uint32_t reg_cntfid; 1303 uint32_t modemr; 1304 uint32_t modemr_pll; 1305 uint32_t board_type; 1306 uint32_t board_rev; 1307 uint32_t pll_table[] = { 1308 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1309 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1310 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1311 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1312 }; 1313 1314 modemr = mmio_read_32(RCAR_MODEMR); 1315 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1316 1317 /* Set frequency data in CNTFID0 */ 1318 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1319 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1320 switch (modemr_pll) { 1321 case MD14_MD13_TYPE_0: 1322 rcar_get_board_type(&board_type, &board_rev); 1323 if (BOARD_SALVATOR_XS == board_type) { 1324 reg_cntfid = EXTAL_SALVATOR_XS; 1325 } 1326 break; 1327 case MD14_MD13_TYPE_3: 1328 if (PRR_PRODUCT_H3_CUT10 == reg) { 1329 reg_cntfid = reg_cntfid >> 1U; 1330 } 1331 break; 1332 default: 1333 /* none */ 1334 break; 1335 } 1336 #endif /* RCAR_LSI == RCAR_E3 */ 1337 /* Update memory mapped and register based frequency */ 1338 write_cntfrq_el0((u_register_t )reg_cntfid); 1339 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1340 /* Enable counter */ 1341 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1342 (uint32_t)CNTCR_EN); 1343 } 1344