1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 30 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 31 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 32workaround_reset_end cortex_x3, ERRATUM(2070301) 33 34check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 35 36workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 37 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 38workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 39 40check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 41 42workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 43 /* Disable retention control for WFI and WFE. */ 44 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 45 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 46 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 47 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 48workaround_reset_end cortex_x3, ERRATUM(2615812) 49 50check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 51 52workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 53 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 54 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 55 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 56workaround_reset_end cortex_x3, ERRATUM(2742421) 57 58check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 59 60workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 61#if IMAGE_BL31 62 override_vector_table wa_cve_vbar_cortex_x3 63#endif /* IMAGE_BL31 */ 64workaround_reset_end cortex_x3, CVE(2022, 23960) 65 66check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 67 68cpu_reset_func_start cortex_x3 69 /* Disable speculative loads */ 70 msr SSBS, xzr 71cpu_reset_func_end cortex_x3 72 73 /* ---------------------------------------------------- 74 * HW will do the cache maintenance while powering down 75 * ---------------------------------------------------- 76 */ 77func cortex_x3_core_pwr_dwn 78apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 79 /* --------------------------------------------------- 80 * Enable CPU power down bit in power control register 81 * --------------------------------------------------- 82 */ 83 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 84 isb 85 ret 86endfunc cortex_x3_core_pwr_dwn 87 88errata_report_shim cortex_x3 89 90 /* --------------------------------------------- 91 * This function provides Cortex-X3- 92 * specific register information for crash 93 * reporting. It needs to return with x6 94 * pointing to a list of register names in ascii 95 * and x8 - x15 having values of registers to be 96 * reported. 97 * --------------------------------------------- 98 */ 99.section .rodata.cortex_x3_regs, "aS" 100cortex_x3_regs: /* The ascii list of register names to be reported */ 101 .asciz "cpuectlr_el1", "" 102 103func cortex_x3_cpu_reg_dump 104 adr x6, cortex_x3_regs 105 mrs x8, CORTEX_X3_CPUECTLR_EL1 106 ret 107endfunc cortex_x3_cpu_reg_dump 108 109declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 110 cortex_x3_reset_func, \ 111 cortex_x3_core_pwr_dwn 112