1 /* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 #include <lib/cpus/errata.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 18 #if ENABLE_RME 19 #define FEAT_ENABLE_ALL_WORLDS \ 20 ((1u << CPU_CONTEXT_SECURE) | \ 21 (1u << CPU_CONTEXT_NS) | \ 22 (1u << CPU_CONTEXT_REALM)) 23 #define FEAT_ENABLE_REALM (1 << CPU_CONTEXT_REALM) 24 #else 25 #define FEAT_ENABLE_ALL_WORLDS \ 26 ((1u << CPU_CONTEXT_SECURE) | \ 27 (1u << CPU_CONTEXT_NS)) 28 #define FEAT_ENABLE_REALM U(0) 29 #endif 30 31 #define FEAT_ENABLE_SECURE (1 << CPU_CONTEXT_SECURE) 32 #define FEAT_ENABLE_NS (1 << CPU_CONTEXT_NS) 33 34 #define ISOLATE_FIELD(reg, feat, mask) \ 35 ((unsigned int)(((reg) >> (feat)) & mask)) 36 37 #define SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, world) \ 38 (((guard) == 0U) || ((((enabled_worlds) >> (world)) & 1U) == 0U)) 39 40 41 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 42 __attribute__((always_inline)) \ 43 static inline bool is_ ## name ## _supported(void) \ 44 { \ 45 if ((guard) == FEAT_STATE_DISABLED) { \ 46 return false; \ 47 } \ 48 if ((guard) == FEAT_STATE_ALWAYS) { \ 49 return true; \ 50 } \ 51 return read_func(); \ 52 } 53 54 /* 55 * CREATE_IDREG_UPDATE and CREATE_PERCPU_IDREG_UPDATE are two macros that 56 * generate the update_feat_abc_idreg_field() function based on how its 57 * corresponding ID register is cached. 58 * The function disables ID register fields related to a feature if the build 59 * flag for that feature is 0 or if the feature should be disabled for that 60 * world. If the particular field has to be disabled, its field in the cached 61 * ID register is set to 0. 62 * 63 * Note: For most ID register fields, a value of 0 represents 64 * the Unimplemented state, and hence we use this macro to show features 65 * disabled in EL3 as unimplemented to lower ELs. However, certain feature's 66 * ID Register fields (like ID_AA64MMFR4_EL1.E2H0) deviate from this convention, 67 * where 0 does not represent Unimplemented. 68 * For those features, a custom update_feat_abc_idreg_field() 69 * needs to be created. This custom function should set the field to the 70 * feature's unimplemented state value if the feature is disabled in EL3. 71 * 72 * For example: 73 * 74 * __attribute__((always_inline)) 75 * static inline void update_feat_abc_idreg_field(size_t security_state) 76 * { 77 * if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { 78 * per_world_context_t *per_world_ctx = 79 * &per_world_context[security_state]; 80 * perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs); 81 * 82 * perworld_idregs->idreg &= 83 * ~((u_register_t)mask << idfield); 84 * perworld_idregs->idreg |= 85 * (((u_register_t)<unimplemented state value> & mask) << idfield); 86 * } 87 * } 88 */ 89 90 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 91 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) \ 92 __attribute__((always_inline)) \ 93 static inline void update_ ## name ## _idreg_field(size_t security_state) \ 94 { \ 95 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \ 96 per_world_context_t *per_world_ctx = \ 97 &per_world_context[security_state]; \ 98 perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs); \ 99 perworld_idregs->idreg &= ~((u_register_t)mask << idfield); \ 100 } \ 101 } 102 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ 103 enabled_worlds) \ 104 __attribute__((always_inline)) \ 105 static inline void update_ ## name ## _idreg_field(size_t security_state) \ 106 { \ 107 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \ 108 percpu_idregs_t *percpu_idregs = \ 109 &(get_cpu_data(idregs[security_state]));\ 110 percpu_idregs->idreg &= ~((u_register_t)mask << idfield); \ 111 } \ 112 } 113 #else 114 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) 115 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ 116 enabled_worlds) 117 #endif 118 119 #define _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 120 __attribute__((always_inline)) \ 121 static inline bool is_ ## name ## _present(void) \ 122 { \ 123 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 124 ? true : false; \ 125 } 126 127 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 128 enabled_worlds) \ 129 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 130 CREATE_IDREG_UPDATE(name, idreg, idfield, mask, 1U, enabled_worlds) 131 132 #define CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 133 enabled_worlds) \ 134 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 135 CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, 1U, \ 136 enabled_worlds) 137 138 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \ 139 enabled_worlds) \ 140 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 141 enabled_worlds) \ 142 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 143 144 #define CREATE_PERCPU_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \ 145 enabled_worlds) \ 146 CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 147 enabled_worlds) \ 148 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 149 150 /* +----------------------------+ 151 * | Features supported | 152 * +----------------------------+ 153 * | GENTIMER | 154 * +----------------------------+ 155 * | FEAT_PAN | 156 * +----------------------------+ 157 * | FEAT_VHE | 158 * +----------------------------+ 159 * | FEAT_TTCNP | 160 * +----------------------------+ 161 * | FEAT_UAO | 162 * +----------------------------+ 163 * | FEAT_PACQARMA3 | 164 * +----------------------------+ 165 * | FEAT_PAUTH | 166 * +----------------------------+ 167 * | FEAT_TTST | 168 * +----------------------------+ 169 * | FEAT_BTI | 170 * +----------------------------+ 171 * | FEAT_MTE2 | 172 * +----------------------------+ 173 * | FEAT_SSBS | 174 * +----------------------------+ 175 * | FEAT_NMI | 176 * +----------------------------+ 177 * | FEAT_GCS | 178 * +----------------------------+ 179 * | FEAT_EBEP | 180 * +----------------------------+ 181 * | FEAT_SEBEP | 182 * +----------------------------+ 183 * | FEAT_SEL2 | 184 * +----------------------------+ 185 * | FEAT_TWED | 186 * +----------------------------+ 187 * | FEAT_FGT | 188 * +----------------------------+ 189 * | FEAT_EC/ECV2 | 190 * +----------------------------+ 191 * | FEAT_RNG | 192 * +----------------------------+ 193 * | FEAT_TCR2 | 194 * +----------------------------+ 195 * | FEAT_S2POE | 196 * +----------------------------+ 197 * | FEAT_S1POE | 198 * +----------------------------+ 199 * | FEAT_S2PIE | 200 * +----------------------------+ 201 * | FEAT_S1PIE | 202 * +----------------------------+ 203 * | FEAT_AMU/AMUV1P1 | 204 * +----------------------------+ 205 * | FEAT_MPAM | 206 * +----------------------------+ 207 * | FEAT_HCX | 208 * +----------------------------+ 209 * | FEAT_RNG_TRAP | 210 * +----------------------------+ 211 * | FEAT_RME | 212 * +----------------------------+ 213 * | FEAT_SB | 214 * +----------------------------+ 215 * | FEAT_CSV2_2/CSV2_3 | 216 * +----------------------------+ 217 * | FEAT_SPE | 218 * +----------------------------+ 219 * | FEAT_SVE | 220 * +----------------------------+ 221 * | FEAT_RAS | 222 * +----------------------------+ 223 * | FEAT_DIT | 224 * +----------------------------+ 225 * | FEAT_SYS_REG_TRACE | 226 * +----------------------------+ 227 * | FEAT_TRF | 228 * +----------------------------+ 229 * | FEAT_NV2 | 230 * +----------------------------+ 231 * | FEAT_BRBE | 232 * +----------------------------+ 233 * | FEAT_TRBE | 234 * +----------------------------+ 235 * | FEAT_SME/SME2 | 236 * +----------------------------+ 237 * | FEAT_PMUV3 | 238 * +----------------------------+ 239 * | FEAT_MTPMU | 240 * +----------------------------+ 241 * | FEAT_FGT2 | 242 * +----------------------------+ 243 * | FEAT_THE | 244 * +----------------------------+ 245 * | FEAT_SCTLR2 | 246 * +----------------------------+ 247 * | FEAT_D128 | 248 * +----------------------------+ 249 * | FEAT_LS64_ACCDATA | 250 * +----------------------------+ 251 * | FEAT_FPMR | 252 * +----------------------------+ 253 * | FEAT_MOPS | 254 * +----------------------------+ 255 * | FEAT_PAUTH_LR | 256 * +----------------------------+ 257 * | FEAT_FGWTE3 | 258 * +----------------------------+ 259 * | FEAT_MPAM_PE_BW_CTRL | 260 * +----------------------------+ 261 * | FEAT_CPA2 | 262 * +----------------------------+ 263 * | FEAT_AIE | 264 * +----------------------------+ 265 * | FEAT_PFAR | 266 * +----------------------------+ 267 * | FEAT_RME_GPC2 | 268 * +----------------------------+ 269 * | FEAT_RME_GDI | 270 * +----------------------------+ 271 * | FEAT_IDTE3 | 272 * +----------------------------+ 273 * | FEAT_UINJ | 274 * +----------------------------+ 275 * | FEAT_LSE | 276 * +----------------------------+ 277 * | FEAT_MORELLO | 278 * +----------------------------+ 279 */ 280 281 __attribute__((always_inline)) 282 static inline bool is_armv7_gentimer_present(void) 283 { 284 /* The Generic Timer is always present in an ARMv8-A implementation */ 285 return true; 286 } 287 288 /* FEAT_PAN: Privileged access never */ 289 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 290 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN, 291 FEAT_ENABLE_ALL_WORLDS) 292 293 /* FEAT_VHE: Virtualization Host Extensions */ 294 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 295 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE, 296 FEAT_ENABLE_ALL_WORLDS) 297 298 /* FEAT_TTCNP: Translation table common not private */ 299 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 300 ID_AA64MMFR2_EL1_CNP_MASK, 1U, 301 FEAT_ENABLE_ALL_WORLDS) 302 303 /* FEAT_UAO: User access override */ 304 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 305 ID_AA64MMFR2_EL1_UAO_MASK, 1U, 306 FEAT_ENABLE_ALL_WORLDS) 307 308 /* If any of the fields is not zero, QARMA3 algorithm is present */ 309 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 310 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 311 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U, 312 FEAT_ENABLE_ALL_WORLDS) 313 314 /* FEAT_PAUTH: Pointer Authentication */ 315 __attribute__((always_inline)) 316 static inline bool is_feat_pauth_present(void) 317 { 318 uint64_t mask_id_aa64isar1 = 319 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 320 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 321 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 322 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 323 324 /* 325 * If any of the fields is not zero or QARMA3 is present, 326 * PAuth is present 327 */ 328 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 329 is_feat_pacqarma3_present()); 330 } 331 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH) 332 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS) 333 334 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 335 __attribute__((always_inline)) 336 static inline void update_feat_pauth_idreg_field(size_t security_state) 337 { 338 uint64_t mask_id_aa64isar1 = 339 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 340 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 341 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 342 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 343 344 uint64_t mask_id_aa64isar2 = 345 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_MASK) | 346 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_MASK); 347 348 per_world_context_t *per_world_ctx = &per_world_context[security_state]; 349 perworld_idregs_t *perworld_idregs = 350 &(per_world_ctx->idregs); 351 352 if ((SHOULD_ID_FIELD_DISABLE(ENABLE_PAUTH, FEAT_ENABLE_NS, 353 security_state)) && 354 (SHOULD_ID_FIELD_DISABLE(CTX_INCLUDE_PAUTH_REGS, 355 FEAT_ENABLE_ALL_WORLDS, 356 security_state))) { 357 perworld_idregs->id_aa64isar1_el1 &= ~(mask_id_aa64isar1); 358 perworld_idregs->id_aa64isar2_el1 &= ~(mask_id_aa64isar2); 359 } 360 } 361 #endif 362 363 /* 364 * FEAT_PAUTH_LR 365 * This feature has a non-standard discovery method so define this function 366 * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This 367 * feature is enabled with ENABLE_PAUTH when present. 368 */ 369 __attribute__((always_inline)) 370 static inline bool is_feat_pauth_lr_present(void) 371 { 372 /* 373 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more 374 * of these is 0b0110 then the feature is present. 375 * 1) id_aa64isr1_el1.api 376 * 2) id_aa64isr1_el1.apa 377 * 3) id_aa64isr2_el1.apa3 378 */ 379 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) { 380 return true; 381 } 382 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) { 383 return true; 384 } 385 if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) { 386 return true; 387 } 388 return false; 389 } 390 CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR) 391 392 /* FEAT_TTST: Small translation tables */ 393 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 394 ID_AA64MMFR2_EL1_ST_MASK, 1U, 395 FEAT_ENABLE_ALL_WORLDS) 396 397 /* FEAT_BTI: Branch target identification */ 398 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 399 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI, 400 FEAT_ENABLE_ALL_WORLDS) 401 402 /* FEAT_MTE2: Memory tagging extension */ 403 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 404 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2, 405 FEAT_ENABLE_SECURE | FEAT_ENABLE_NS) 406 407 /* FEAT_SSBS: Speculative store bypass safe */ 408 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 409 ID_AA64PFR1_EL1_SSBS_MASK, 1U, 410 FEAT_ENABLE_ALL_WORLDS) 411 412 /* FEAT_NMI: Non-maskable interrupts */ 413 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 414 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED, 415 FEAT_ENABLE_ALL_WORLDS) 416 417 /* FEAT_EBEP */ 418 CREATE_PERCPU_FEATURE_FUNCS(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 419 ID_AA64DFR1_EBEP_MASK, 1U, ENABLE_FEAT_EBEP, 420 FEAT_ENABLE_ALL_WORLDS) 421 422 /* FEAT_SEBEP */ 423 CREATE_PERCPU_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 424 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED, 425 FEAT_ENABLE_ALL_WORLDS) 426 427 /* FEAT_SEL2: Secure EL2 */ 428 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 429 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2, 430 FEAT_ENABLE_ALL_WORLDS) 431 432 /* FEAT_TWED: Delayed trapping of WFE */ 433 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 434 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED, 435 FEAT_ENABLE_ALL_WORLDS) 436 437 /* FEAT_FGT: Fine-grained traps */ 438 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 439 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT, 440 FEAT_ENABLE_ALL_WORLDS) 441 442 /* FEAT_FGT2: Fine-grained traps extended */ 443 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 444 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2, 445 FEAT_ENABLE_ALL_WORLDS) 446 447 /* FEAT_FGWTE3: Fine-grained write traps EL3 */ 448 CREATE_FEATURE_FUNCS(feat_fgwte3, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 449 ID_AA64MMFR4_EL1_FGWTE3_MASK, FGWTE3_IMPLEMENTED, 450 ENABLE_FEAT_FGWTE3, FEAT_ENABLE_ALL_WORLDS) 451 452 /* FEAT_ECV: Enhanced Counter Virtualization */ 453 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 454 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV, 455 FEAT_ENABLE_ALL_WORLDS) 456 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 457 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, 458 ENABLE_FEAT_ECV, FEAT_ENABLE_ALL_WORLDS) 459 460 /* FEAT_RNG: Random number generator */ 461 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 462 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG, 463 FEAT_ENABLE_ALL_WORLDS) 464 465 /* FEAT_TCR2: Support TCR2_ELx regs */ 466 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 467 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2, 468 FEAT_ENABLE_ALL_WORLDS) 469 470 /* FEAT_S2POE */ 471 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 472 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE, 473 FEAT_ENABLE_ALL_WORLDS) 474 475 /* FEAT_S1POE */ 476 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 477 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE, 478 FEAT_ENABLE_ALL_WORLDS) 479 480 __attribute__((always_inline)) 481 static inline bool is_feat_sxpoe_supported(void) 482 { 483 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 484 } 485 486 /* FEAT_S2PIE */ 487 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 488 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE, 489 FEAT_ENABLE_ALL_WORLDS) 490 491 /* FEAT_S1PIE */ 492 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 493 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE, 494 FEAT_ENABLE_ALL_WORLDS) 495 496 /* FEAT_THE: Translation Hardening Extension */ 497 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 498 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE, 499 FEAT_ENABLE_NS) 500 501 /* FEAT_SCTLR2 */ 502 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 503 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 504 ENABLE_FEAT_SCTLR2, 505 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 506 507 /* FEAT_D128 */ 508 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT, 509 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED, 510 ENABLE_FEAT_D128, FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 511 512 /* FEAT_RME_GPC2 */ 513 _CREATE_FEATURE_PRESENT(feat_rme_gpc2, id_aa64pfr0_el1, 514 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 515 RME_GPC2_IMPLEMENTED) 516 517 /* FEAT_RME_GDI */ 518 CREATE_FEATURE_FUNCS(feat_rme_gdi, id_aa64mmfr4_el1, 519 ID_AA64MMFR4_EL1_RME_GDI_SHIFT, 520 ID_AA64MMFR4_EL1_RME_GDI_MASK, RME_GDI_IMPLEMENTED, 521 ENABLE_FEAT_RME_GDI, FEAT_ENABLE_ALL_WORLDS) 522 523 /* FEAT_FPMR */ 524 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT, 525 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED, 526 ENABLE_FEAT_FPMR, FEAT_ENABLE_NS) 527 /* FEAT_MOPS */ 528 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT, 529 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED, 530 ENABLE_FEAT_MOPS, FEAT_ENABLE_ALL_WORLDS) 531 532 __attribute__((always_inline)) 533 static inline bool is_feat_sxpie_supported(void) 534 { 535 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 536 } 537 538 /* FEAT_GCS: Guarded Control Stack */ 539 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 540 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS, 541 FEAT_ENABLE_ALL_WORLDS) 542 543 /* FEAT_AMU: Activity Monitors Extension */ 544 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 545 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU, 546 FEAT_ENABLE_NS) 547 548 /* Auxiliary counters for FEAT_AMU */ 549 _CREATE_FEATURE_PRESENT(feat_amu_aux, amcfgr_el0, 550 AMCFGR_EL0_NCG_SHIFT, AMCFGR_EL0_NCG_MASK, 1U) 551 552 CREATE_FEATURE_SUPPORTED(feat_amu_aux, is_feat_amu_aux_present, 553 ENABLE_AMU_AUXILIARY_COUNTERS) 554 555 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 556 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 557 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1, 558 FEAT_ENABLE_NS) 559 560 /* 561 * Return MPAM version: 562 * 563 * 0x00: None Armv8.0 or later 564 * 0x01: v0.1 Armv8.4 or later 565 * 0x10: v1.0 Armv8.2 or later 566 * 0x11: v1.1 Armv8.4 or later 567 * 568 */ 569 __attribute__((always_inline)) 570 static inline bool is_feat_mpam_present(void) 571 { 572 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 573 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 574 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 575 & ID_AA64PFR1_MPAM_FRAC_MASK)); 576 return ret; 577 } 578 579 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 580 581 582 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 583 __attribute__((always_inline)) 584 static inline void update_feat_mpam_idreg_field(size_t security_state) 585 { 586 if (SHOULD_ID_FIELD_DISABLE(ENABLE_FEAT_MPAM, 587 FEAT_ENABLE_NS | FEAT_ENABLE_REALM, security_state)) { 588 per_world_context_t *per_world_ctx = 589 &per_world_context[security_state]; 590 perworld_idregs_t *perworld_idregs = 591 &(per_world_ctx->idregs); 592 593 perworld_idregs->id_aa64pfr0_el1 &= 594 ~((u_register_t)ID_AA64PFR0_MPAM_MASK 595 << ID_AA64PFR0_MPAM_SHIFT); 596 597 perworld_idregs->id_aa64pfr1_el1 &= 598 ~((u_register_t)ID_AA64PFR1_MPAM_FRAC_MASK 599 << ID_AA64PFR1_MPAM_FRAC_SHIFT); 600 } 601 } 602 #endif 603 604 /* FEAT_MPAM_PE_BW_CTRL: MPAM PE-side bandwidth controls */ 605 __attribute__((always_inline)) 606 static inline bool is_feat_mpam_pe_bw_ctrl_present(void) 607 { 608 if (is_feat_mpam_present()) { 609 return ((unsigned long long)(read_mpamidr_el1() & 610 MPAMIDR_HAS_BW_CTRL_BIT) != 0U); 611 } 612 return false; 613 } 614 615 CREATE_FEATURE_SUPPORTED(feat_mpam_pe_bw_ctrl, is_feat_mpam_pe_bw_ctrl_present, 616 ENABLE_FEAT_MPAM_PE_BW_CTRL) 617 618 /* 619 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 620 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 621 * Feat_Debug supported. The value of the field determines feature presence 622 * 623 * 0b0110 - Arm v8.0 debug 624 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 625 * 0x1000 - FEAT_Debugv8p2 is supported 626 * 0x1001 - FEAT_Debugv8p4 is supported 627 * 0x1010 - FEAT_Debugv8p8 is supported 628 * 0x1011 - FEAT_Debugv8p9 is supported 629 * 630 */ 631 CREATE_PERCPU_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, 632 ID_AA64DFR0_DEBUGVER_SHIFT, ID_AA64DFR0_DEBUGVER_MASK, 633 DEBUGVER_V8P9_IMPLEMENTED, ENABLE_FEAT_DEBUGV8P9, 634 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 635 636 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 637 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 638 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX, 639 FEAT_ENABLE_ALL_WORLDS) 640 641 /* FEAT_RNG_TRAP: Trapping support */ 642 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 643 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP, 644 FEAT_ENABLE_ALL_WORLDS) 645 646 /* Return the RME version, zero if not supported. */ 647 _CREATE_FEATURE_PRESENT(feat_rme, id_aa64pfr0_el1, 648 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 1U) 649 650 CREATE_FEATURE_SUPPORTED(feat_rme, is_feat_rme_present, ENABLE_RME) 651 652 /* FEAT_SB: Speculation barrier instruction */ 653 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 654 ID_AA64ISAR1_SB_MASK, 1U, 655 FEAT_ENABLE_ALL_WORLDS) 656 657 /* FEAT_MEC: Memory Encryption Contexts */ 658 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT, 659 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC, 660 FEAT_ENABLE_ALL_WORLDS) 661 662 /* 663 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 664 * of id_aa64pfr0_el1 register and can be used to check for below features: 665 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 666 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 667 * 0b0000 - Feature FEAT_CSV2 is not implemented. 668 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 669 * are not implemented. 670 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 671 * implemented. 672 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 673 */ 674 675 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 676 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2, 677 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 678 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 679 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3, 680 FEAT_ENABLE_ALL_WORLDS) 681 682 /* FEAT_SPE: Statistical Profiling Extension */ 683 CREATE_PERCPU_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 684 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS, 685 FEAT_ENABLE_ALL_WORLDS) 686 687 /* FEAT_SVE: Scalable Vector Extension */ 688 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 689 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS, 690 FEAT_ENABLE_ALL_WORLDS) 691 692 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 693 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 694 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS, 695 FEAT_ENABLE_ALL_WORLDS) 696 697 /* FEAT_DIT: Data Independent Timing instructions */ 698 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 699 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT, 700 FEAT_ENABLE_ALL_WORLDS) 701 702 /* FEAT_SYS_REG_TRACE */ 703 CREATE_PERCPU_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, 704 ID_AA64DFR0_TRACEVER_SHIFT, ID_AA64DFR0_TRACEVER_MASK, 705 1U, ENABLE_SYS_REG_TRACE_FOR_NS, 706 FEAT_ENABLE_ALL_WORLDS) 707 708 /* FEAT_TRF: TraceFilter */ 709 CREATE_PERCPU_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 710 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS, 711 FEAT_ENABLE_ALL_WORLDS) 712 713 /* FEAT_NV2: Enhanced Nested Virtualization */ 714 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 715 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS, 716 FEAT_ENABLE_ALL_WORLDS) 717 718 /* FEAT_BRBE: Branch Record Buffer Extension */ 719 CREATE_PERCPU_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 720 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS, 721 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 722 723 /* FEAT_TRBE: Trace Buffer Extension */ 724 _CREATE_FEATURE_PRESENT(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 725 ID_AA64DFR0_TRACEBUFFER_MASK, 1U) 726 727 CREATE_FEATURE_SUPPORTED(feat_trbe, is_feat_trbe_present, ENABLE_TRBE_FOR_NS) 728 729 CREATE_PERCPU_IDREG_UPDATE(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 730 ID_AA64DFR0_TRACEBUFFER_MASK, 731 ENABLE_TRBE_FOR_NS && !check_if_trbe_disable_affected_core(), 732 FEAT_ENABLE_NS) 733 734 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 735 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 736 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U, 737 FEAT_ENABLE_ALL_WORLDS) 738 739 /* FEAT_SMEx: Scalar Matrix Extension */ 740 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 741 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS, 742 FEAT_ENABLE_ALL_WORLDS) 743 744 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 745 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS, 746 FEAT_ENABLE_ALL_WORLDS) 747 748 /* FEAT_LS64_ACCDATA: Support for 64-byte EL0 stores with status */ 749 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT, 750 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED, 751 ENABLE_FEAT_LS64_ACCDATA, FEAT_ENABLE_ALL_WORLDS) 752 753 /* FEAT_AIE: Memory Attribute Index Enhancement */ 754 CREATE_FEATURE_FUNCS(feat_aie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_AIE_SHIFT, 755 ID_AA64MMFR3_EL1_AIE_MASK, 1U, ENABLE_FEAT_AIE, 756 FEAT_ENABLE_NS) 757 758 /* FEAT_PFAR: Physical Fault Address Register Extension */ 759 CREATE_FEATURE_FUNCS(feat_pfar, id_aa64pfr1_el1, ID_AA64PFR1_EL1_PFAR_SHIFT, 760 ID_AA64PFR1_EL1_PFAR_MASK, 1U, ENABLE_FEAT_PFAR, 761 FEAT_ENABLE_NS) 762 763 /* FEAT_IDTE3: Trapping lower EL ID Register access to EL3 */ 764 CREATE_FEATURE_FUNCS(feat_idte3, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_IDS_SHIFT, 765 ID_AA64MMFR2_EL1_IDS_MASK, 2U, ENABLE_FEAT_IDTE3, 766 FEAT_ENABLE_ALL_WORLDS) 767 768 /* FEAT_LSE: Atomic instructions */ 769 CREATE_FEATURE_FUNCS(feat_lse, id_aa64isar0_el1, ID_AA64ISAR0_ATOMIC_SHIFT, 770 ID_AA64ISAR0_ATOMIC_MASK, 1U, USE_SPINLOCK_CAS, 771 FEAT_ENABLE_ALL_WORLDS) 772 773 774 /******************************************************************************* 775 * Function to get hardware granularity support 776 ******************************************************************************/ 777 778 __attribute__((always_inline)) 779 static inline bool is_feat_tgran4K_present(void) 780 { 781 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 782 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 783 return (tgranx < 8U); 784 } 785 786 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 787 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED, 788 FEAT_ENABLE_ALL_WORLDS) 789 790 __attribute__((always_inline)) 791 static inline bool is_feat_tgran64K_present(void) 792 { 793 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 794 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 795 return (tgranx < 8U); 796 } 797 798 /* FEAT_PMUV3 */ 799 _CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 800 ID_AA64DFR0_PMUVER_MASK, 1U) 801 802 /* FEAT_MTPMU */ 803 __attribute__((always_inline)) 804 static inline bool is_feat_mtpmu_present(void) 805 { 806 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 807 ID_AA64DFR0_MTPMU_MASK); 808 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 809 } 810 811 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 812 813 CREATE_PERCPU_IDREG_UPDATE(feat_mtpmu, id_aa64dfr0_el1, ID_AA64DFR0_MTPMU_SHIFT, 814 ID_AA64DFR0_MTPMU_MASK, DISABLE_MTPMU, 815 FEAT_ENABLE_ALL_WORLDS) 816 817 /************************************************************************* 818 * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface 819 * extension). 820 ************************************************************************/ 821 CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT, 822 ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE, 823 FEAT_ENABLE_ALL_WORLDS) 824 825 CREATE_FEATURE_FUNCS(feat_cpa2, id_aa64isar3_el1, ID_AA64ISAR3_EL1_CPA_SHIFT, 826 ID_AA64ISAR3_EL1_CPA_MASK, CPA2_IMPLEMENTED, 827 ENABLE_FEAT_CPA2, FEAT_ENABLE_ALL_WORLDS) 828 829 /* FEAT_UINJ: Injection of Undefined Instruction exceptions */ 830 CREATE_FEATURE_FUNCS(feat_uinj, id_aa64pfr2_el1, ID_AA64PFR2_EL1_UINJ_SHIFT, 831 ID_AA64PFR2_EL1_UINJ_MASK, UINJ_IMPLEMENTED, 832 ENABLE_FEAT_UINJ, FEAT_ENABLE_ALL_WORLDS) 833 834 /* FEAT_MORELLO_PRESENT */ 835 CREATE_FEATURE_FUNCS(feat_morello, id_aa64pfr1_el1, ID_AA64PFR1_EL1_CE_SHIFT, 836 ID_AA64PFR1_EL1_CE_MASK, MORELLO_EXTENSION_IMPLEMENTED, 837 ENABLE_FEAT_MORELLO, FEAT_ENABLE_ALL_WORLDS) 838 #endif /* ARCH_FEATURES_H */ 839