1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef RDASPEN_DEFS_DTSI 8#define RDASPEN_DEFS_DTSI 9 10#include <platform_def.h> 11 12#define CPU(cluster_num, cluster_core_num, cpu_num, mpid) \ 13 CPU##cpu_num:cpu@mpid## { \ 14 device_type = "cpu"; \ 15 compatible = "arm,cortex-a720ae"; \ 16 reg = <0x0 0x##mpid>; \ 17 enable-method = "psci"; \ 18 i-cache-size = <0x10000>; \ 19 i-cache-line-size = <0x40>; \ 20 i-cache-sets = <0x100>; \ 21 d-cache-size = <0x10000>; \ 22 d-cache-line-size = <0x40>; \ 23 d-cache-sets = <0x100>; \ 24 next-level-cache = <&CL##cluster_num##_L2_##cluster_core_num>; \ 25 CL##cluster_num##_L2_##cluster_core_num: l2-cache { \ 26 compatible = "cache"; \ 27 cache-unified; \ 28 cache-level = <0x02>; \ 29 /* 512KB */ \ 30 cache-size = <0x80000>; \ 31 /* 64B */ \ 32 cache-line-size = <0x40>; \ 33 /* 8-way set */ \ 34 cache-sets = <0x400>; \ 35 next-level-cache = <&CL##cluster_num##_L3>; \ 36 }; \ 37 }; 38 39#define CORE(cluster_core_num, cpu_num) \ 40 core##cluster_core_num { \ 41 cpu = <&CPU##cpu_num>; \ 42 }; 43 44#define CLUSTER_L3_CACHE(cluster_num) \ 45 CL##cluster_num##_L3: l3-cache##cluster_num## { \ 46 compatible = "cache"; \ 47 cache-unified; \ 48 cache-level = <0x03>; \ 49 /* 4MB */ \ 50 cache-size = <0x400000>; \ 51 /* 64B */ \ 52 cache-line-size = <0x40>; \ 53 /* 16-way set */ \ 54 cache-sets = <0x1000>; \ 55 }; 56 57#define CLUSTER_DSU_PMU(cluster_num, cpu_list, interrupt_map) \ 58 dsu-pmu-##cluster_num { \ 59 compatible = "arm,dsu-pmu"; \ 60 cpus = ##cpu_list; \ 61 interrupts = ##interrupt_map; \ 62 }; 63 64#define CLUSTER_0_DSU_PMU_INTERRUPT_MAP <GIC_SPI 216 IRQ_TYPE_EDGE_RISING> 65#define CLUSTER_1_DSU_PMU_INTERRUPT_MAP <GIC_SPI 217 IRQ_TYPE_EDGE_RISING> 66#define CLUSTER_2_DSU_PMU_INTERRUPT_MAP <GIC_SPI 218 IRQ_TYPE_EDGE_RISING> 67#define CLUSTER_3_DSU_PMU_INTERRUPT_MAP <GIC_SPI 219 IRQ_TYPE_EDGE_RISING> 68 69#if (PLATFORM_CLUSTER_0_CORE_COUNT == 1) 70#define CLUSTER_0_CPU_LIST \ 71 CORE(0, 0) 72#define CLUSTER_0_CPUS \ 73 CPU(0, 0, 0, 0) 74#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0> 75#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 2) 76#define CLUSTER_0_CPU_LIST \ 77 CORE(0, 0) \ 78 CORE(1, 1) 79#define CLUSTER_0_CPUS \ 80 CPU(0, 0, 0, 0) \ 81 CPU(0, 1, 1, 100) 82#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1> 83#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 3) 84#define CLUSTER_0_CPU_LIST \ 85 CORE(0, 0) \ 86 CORE(1, 1) \ 87 CORE(2, 2) 88#define CLUSTER_0_CPUS \ 89 CPU(0, 0, 0, 0) \ 90 CPU(0, 1, 1, 100) \ 91 CPU(0, 2, 2, 200) 92#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2> 93#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 4) 94#define CLUSTER_0_CPU_LIST \ 95 CORE(0, 0) \ 96 CORE(1, 1) \ 97 CORE(2, 2) \ 98 CORE(3, 3) 99#define CLUSTER_0_CPUS \ 100 CPU(0, 0, 0, 0) \ 101 CPU(0, 1, 1, 100) \ 102 CPU(0, 2, 2, 200) \ 103 CPU(0, 3, 3, 300) 104#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3> 105#endif 106 107#if (PLATFORM_CLUSTER_1_CORE_COUNT == 1) 108#define CLUSTER_1_CPU_LIST \ 109 CORE(0, 4) 110#define CLUSTER_1_CPUS \ 111 CPU(1, 0, 4, 10000) 112#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4> 113#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 2) 114#define CLUSTER_1_CPU_LIST \ 115 CORE(0, 4) \ 116 CORE(1, 5) 117#define CLUSTER_1_CPUS \ 118 CPU(1, 0, 4, 10000) \ 119 CPU(1, 1, 5, 10100) 120#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5> 121#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 3) 122#define CLUSTER_1_CPU_LIST \ 123 CORE(0, 4) \ 124 CORE(1, 5) \ 125 CORE(2, 6) 126#define CLUSTER_1_CPUS \ 127 CPU(1, 0, 4, 10000) \ 128 CPU(1, 1, 5, 10100) \ 129 CPU(1, 2, 6, 10200) 130#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6> 131#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 4) 132#define CLUSTER_1_CPU_LIST \ 133 CORE(0, 4) \ 134 CORE(1, 5) \ 135 CORE(2, 6) \ 136 CORE(3, 7) 137#define CLUSTER_1_CPUS \ 138 CPU(1, 0, 4, 10000) \ 139 CPU(1, 1, 5, 10100) \ 140 CPU(1, 2, 6, 10200) \ 141 CPU(1, 3, 7, 10300) 142#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> 143#endif 144 145#if (PLATFORM_CLUSTER_2_CORE_COUNT == 1) 146#define CLUSTER_2_CPU_LIST \ 147 CORE(0, 8) 148#define CLUSTER_2_CPUS \ 149 CPU(2, 0, 8, 20000) 150#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8> 151#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 2) 152#define CLUSTER_2_CPU_LIST \ 153 CORE(0, 8) \ 154 CORE(1, 9) 155#define CLUSTER_2_CPUS \ 156 CPU(2, 0, 8, 20000) \ 157 CPU(2, 1, 9, 20100) 158#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9> 159#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 3) 160#define CLUSTER_2_CPU_LIST \ 161 CORE(0, 8) \ 162 CORE(1, 9) \ 163 CORE(2, 10) 164#define CLUSTER_2_CPUS \ 165 CPU(2, 0, 8, 20000) \ 166 CPU(2, 1, 9, 20100) \ 167 CPU(2, 2, 10, 20200) 168#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10> 169#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 4) 170#define CLUSTER_2_CPU_LIST \ 171 CORE(0, 8) \ 172 CORE(1, 9) \ 173 CORE(2, 10) \ 174 CORE(3, 11) 175#define CLUSTER_2_CPUS \ 176 CPU(2, 0, 8, 20000) \ 177 CPU(2, 1, 9, 20100) \ 178 CPU(2, 2, 10, 20200) \ 179 CPU(2, 3, 11, 20300) 180#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11> 181#endif 182 183#if (PLATFORM_CLUSTER_3_CORE_COUNT == 1) 184#define CLUSTER_3_CPU_LIST \ 185 CORE(0, 12) 186#define CLUSTER_3_CPUS \ 187 CPU(3, 0, 12, 30000) 188#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12> 189#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 2) 190#define CLUSTER_3_CPU_LIST \ 191 CORE(0, 12) \ 192 CORE(1, 13) 193#define CLUSTER_3_CPUS \ 194 CPU(3, 0, 12, 30000) \ 195 CPU(3, 1, 13, 30100) 196#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13> 197#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 3) 198#define CLUSTER_3_CPU_LIST \ 199 CORE(0, 12) \ 200 CORE(1, 13) \ 201 CORE(2, 14) 202#define CLUSTER_3_CPUS \ 203 CPU(3, 0, 12, 30000) \ 204 CPU(3, 1, 13, 30100) \ 205 CPU(3, 2, 14, 30200) 206#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14> 207#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 4) 208#define CLUSTER_3_CPU_LIST \ 209 CORE(0, 12) \ 210 CORE(1, 13) \ 211 CORE(2, 14) \ 212 CORE(3, 15) 213#define CLUSTER_3_CPUS \ 214 CPU(3, 0, 12, 30000) \ 215 CPU(3, 1, 13, 30100) \ 216 CPU(3, 2, 14, 30200) \ 217 CPU(3, 3, 15, 30300) 218#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14>, <&CPU15> 219#endif 220 221#define CLUSTER_0_CPU_MAP \ 222 cluster0 { \ 223 CLUSTER_0_CPU_LIST \ 224 }; 225 226#define CLUSTER_0_DSU_PMU \ 227 CLUSTER_DSU_PMU(0, \ 228 CLUSTER_0_DSU_PMU_CPU_LIST, \ 229 CLUSTER_0_DSU_PMU_INTERRUPT_MAP) 230 231#if (PLATFORM_CLUSTER_1_CORE_COUNT >= 1) 232#define CLUSTER_1_CPU_MAP \ 233 cluster1 { \ 234 CLUSTER_1_CPU_LIST \ 235 }; 236 237#define CLUSTER_1_DSU_PMU \ 238 CLUSTER_DSU_PMU(1, \ 239 CLUSTER_1_DSU_PMU_CPU_LIST, \ 240 CLUSTER_1_DSU_PMU_INTERRUPT_MAP) 241#endif 242 243#if (PLATFORM_CLUSTER_2_CORE_COUNT >= 1) 244#define CLUSTER_2_CPU_MAP \ 245 cluster2 { \ 246 CLUSTER_2_CPU_LIST \ 247 }; 248 249#define CLUSTER_2_DSU_PMU \ 250 CLUSTER_DSU_PMU(2, \ 251 CLUSTER_2_DSU_PMU_CPU_LIST, \ 252 CLUSTER_2_DSU_PMU_INTERRUPT_MAP) 253#endif 254 255#if (PLATFORM_CLUSTER_3_CORE_COUNT >= 1) 256#define CLUSTER_3_CPU_MAP \ 257 cluster3 { \ 258 CLUSTER_3_CPU_LIST \ 259 }; 260 261#define CLUSTER_3_DSU_PMU \ 262 CLUSTER_DSU_PMU(3, \ 263 CLUSTER_3_DSU_PMU_CPU_LIST, \ 264 CLUSTER_3_DSU_PMU_INTERRUPT_MAP) 265#endif 266 267/* Max 4 clusters */ 268#if (PLAT_ARM_CLUSTER_COUNT == 1) 269#define CPU_MAP \ 270 cpu-map { \ 271 CLUSTER_0_CPU_MAP \ 272 }; 273 274#define CPUS \ 275 CLUSTER_0_CPUS 276 277#define DSU_PMU \ 278 CLUSTER_0_DSU_PMU 279 280#define L3_CACHE \ 281 CLUSTER_L3_CACHE(0) 282 283#elif (PLAT_ARM_CLUSTER_COUNT == 2) 284#define CPU_MAP \ 285 cpu-map { \ 286 CLUSTER_0_CPU_MAP \ 287 CLUSTER_1_CPU_MAP \ 288 }; 289 290#define CPUS \ 291 CLUSTER_0_CPUS \ 292 CLUSTER_1_CPUS 293 294#define DSU_PMU \ 295 CLUSTER_0_DSU_PMU \ 296 CLUSTER_1_DSU_PMU 297 298#define L3_CACHE \ 299 CLUSTER_L3_CACHE(0) \ 300 CLUSTER_L3_CACHE(1) 301 302#elif (PLAT_ARM_CLUSTER_COUNT == 3) 303#define CPU_MAP \ 304 cpu-map { \ 305 CLUSTER_0_CPU_MAP \ 306 CLUSTER_1_CPU_MAP \ 307 CLUSTER_2_CPU_MAP \ 308 }; 309 310#define CPUS \ 311 CLUSTER_0_CPUS \ 312 CLUSTER_1_CPUS \ 313 CLUSTER_2_CPUS 314 315#define DSU_PMU \ 316 CLUSTER_0_DSU_PMU \ 317 CLUSTER_1_DSU_PMU \ 318 CLUSTER_2_DSU_PMU 319 320#define L3_CACHE \ 321 CLUSTER_L3_CACHE(0) \ 322 CLUSTER_L3_CACHE(1) \ 323 CLUSTER_L3_CACHE(2) 324 325#elif (PLAT_ARM_CLUSTER_COUNT == 4) 326#define CPU_MAP \ 327 cpu-map { \ 328 CLUSTER_0_CPU_MAP \ 329 CLUSTER_1_CPU_MAP \ 330 CLUSTER_2_CPU_MAP \ 331 CLUSTER_3_CPU_MAP \ 332 }; 333 334#define CPUS \ 335 CLUSTER_0_CPUS \ 336 CLUSTER_1_CPUS \ 337 CLUSTER_2_CPUS \ 338 CLUSTER_3_CPUS 339 340#define DSU_PMU \ 341 CLUSTER_0_DSU_PMU \ 342 CLUSTER_1_DSU_PMU \ 343 CLUSTER_2_DSU_PMU \ 344 CLUSTER_3_DSU_PMU 345 346#define L3_CACHE \ 347 CLUSTER_L3_CACHE(0) \ 348 CLUSTER_L3_CACHE(1) \ 349 CLUSTER_L3_CACHE(2) \ 350 CLUSTER_L3_CACHE(3) 351 352#endif /* PLAT_ARM_CLUSTER_COUNT */ 353 354#endif /* RDASPEN_DEFS_DTSI */ 355