1 /* 2 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/el3_runtime/context_mgmt.h> 14 #include <lib/extensions/sme.h> 15 #include <lib/extensions/sve.h> 16 17 void sme_enable(cpu_context_t *context) 18 { 19 u_register_t reg; 20 el3_state_t *state; 21 22 /* Get the context state. */ 23 state = get_el3state_ctx(context); 24 25 /* Enable SME in CPTR_EL3. */ 26 reg = read_ctx_reg(state, CTX_CPTR_EL3); 27 reg |= ESM_BIT; 28 write_ctx_reg(state, CTX_CPTR_EL3, reg); 29 30 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 31 reg = read_ctx_reg(state, CTX_SCR_EL3); 32 reg |= SCR_ENTP2_BIT; 33 write_ctx_reg(state, CTX_SCR_EL3, reg); 34 } 35 36 void sme_init_el3(void) 37 { 38 u_register_t cptr_el3 = read_cptr_el3(); 39 u_register_t smcr_el3; 40 41 /* Set CPTR_EL3.ESM bit so we can access SMCR_EL3 without trapping. */ 42 write_cptr_el3(cptr_el3 | ESM_BIT); 43 isb(); 44 45 /* 46 * Set the max LEN value and FA64 bit. This register is set up globally 47 * to be the least restrictive, then lower ELs can restrict as needed 48 * using SMCR_EL2 and SMCR_EL1. 49 */ 50 smcr_el3 = SMCR_ELX_LEN_MAX; 51 if (read_feat_sme_fa64_id_field() != 0U) { 52 VERBOSE("[SME] FA64 enabled\n"); 53 smcr_el3 |= SMCR_ELX_FA64_BIT; 54 } 55 56 /* 57 * Enable access to ZT0 register. 58 * Make sure FEAT_SME2 is supported by the hardware before continuing. 59 * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to 60 * access ZT0 register without trapping. 61 */ 62 if (is_feat_sme2_supported()) { 63 VERBOSE("SME2 enabled\n"); 64 smcr_el3 |= SMCR_ELX_EZT0_BIT; 65 } 66 write_smcr_el3(smcr_el3); 67 68 /* Reset CPTR_EL3 value. */ 69 write_cptr_el3(cptr_el3); 70 isb(); 71 } 72 73 void sme_init_el2_unused(void) 74 { 75 /* 76 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 accesses to the 77 * CPACR_EL1 or CPACR from both Execution states do not trap to EL2. 78 */ 79 write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TCPAC_BIT); 80 } 81 82 void sme_disable(cpu_context_t *context) 83 { 84 u_register_t reg; 85 el3_state_t *state; 86 87 /* Get the context state. */ 88 state = get_el3state_ctx(context); 89 90 /* Disable SME, SVE, and FPU since they all share registers. */ 91 reg = read_ctx_reg(state, CTX_CPTR_EL3); 92 reg &= ~ESM_BIT; /* Trap SME */ 93 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 94 reg |= TFP_BIT; /* Trap FPU/SIMD */ 95 write_ctx_reg(state, CTX_CPTR_EL3, reg); 96 97 /* Disable access to TPIDR2_EL0. */ 98 reg = read_ctx_reg(state, CTX_SCR_EL3); 99 reg &= ~SCR_ENTP2_BIT; 100 write_ctx_reg(state, CTX_SCR_EL3, reg); 101 } 102