1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 184 registers in cpu context. This must be enabled, if the platform wants to use 185 this feature in the Secure world and MTE is enabled at ELX. This flag can 186 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 187 Default value is 0. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``FEATURE_DETECTION`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 218 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 219 mechanism. Default is ``0``. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 235 the normal boot flow. It must specify the entry point address of the EL3 236 payload. Please refer to the "Booting an EL3 payload" section for more 237 details. 238 239- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 240 (also known as group 1 counters). These are implementation-defined counters, 241 and as such require additional platform configuration. Default is 0. 242 243- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 244 allows platforms with auxiliary counters to describe them via the 245 ``HW_CONFIG`` device tree blob. Default is 0. 246 247- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 248 are compiled out. For debug builds, this option defaults to 1, and calls to 249 ``assert()`` are left in place. For release builds, this option defaults to 0 250 and calls to ``assert()`` function are compiled out. This option can be set 251 independently of ``DEBUG``. It can also be used to hide any auxiliary code 252 that is only required for the assertion and does not fit in the assertion 253 itself. 254 255- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 256 dumps or not. It is supported in both AArch64 and AArch32. However, in 257 AArch32 the format of the frame records are not defined in the AAPCS and they 258 are defined by the implementation. This implementation of backtrace only 259 supports the format used by GCC when T32 interworking is disabled. For this 260 reason enabling this option in AArch32 will force the compiler to only 261 generate A32 code. This option is enabled by default only in AArch64 debug 262 builds, but this behaviour can be overridden in each platform's Makefile or 263 in the build command line. 264 265- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 266 extensions. This flag can take the values 0 to 2, to align with the 267 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 268 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 269 and this option can be used to enable this feature on those systems as well. 270 This flag can take the values 0 to 2, the default is 0. 271 272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 274 onwards. This flag can take the values 0 to 2, to align with the 275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 276 277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 280 optional feature available on Arm v8.0 onwards. This flag can take values 281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 282 Default value is ``0``. 283 284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 287 and upwards. This flag can take the values 0 to 2, to align with the 288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 289 290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 292 Physical Offset register) during EL2 to EL3 context save/restore operations. 293 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 295 mechanism. Default value is ``0``. 296 297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 299 Read Trap Register) during EL2 to EL3 context save/restore operations. 300 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 302 mechanism. Default value is ``0``. 303 304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 307 mandatory architectural feature and is enabled from v8.7 and upwards. This 308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 309 mechanism. Default value is ``0``. 310 311- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 312 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 313 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 314 feature available from v8.9 and upwards. This flag can take the values 0 to 315 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is 316 ``0``. 317 318- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 319 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 320 permission fault for any privileged data access from EL1/EL2 to virtual 321 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 322 mandatory architectural feature and is enabled from v8.1 and upwards. This 323 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 324 mechanism. Default value is ``0``. 325 326- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 327 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 328 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 329 mechanism. Default value is ``0``. 330 331- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 332 extension. This feature is only supported in AArch64 state. This flag can 333 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 334 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 335 Armv8.5 onwards. 336 337- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 338 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 339 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 340 later CPUs. It is enabled from v8.5 and upwards and if needed can be 341 overidden from platforms explicitly. 342 343- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 344 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 345 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 346 mechanism. Default is ``0``. 347 348- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 349 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 350 available on Arm v8.6. This flag can take values 0 to 2, to align with the 351 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 352 353 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 354 delayed by the amount of value in ``TWED_DELAY``. 355 356- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 357 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 358 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 359 architectural feature and is enabled from v8.1 and upwards. It can take 360 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 361 Default value is ``0``. 362 363- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 364 allow access to TCR2_EL2 (extended translation control) from EL2 as 365 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 366 mandatory architectural feature and is enabled from v8.9 and upwards. This 367 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 368 mechanism. Default value is ``0``. 369 370- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 371 at EL2 and below, and context switch relevant registers. This flag 372 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 373 mechanism. Default value is ``0``. 374 375- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 376 at EL2 and below, and context switch relevant registers. This flag 377 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 378 mechanism. Default value is ``0``. 379 380- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 381 at EL2 and below, and context switch relevant registers. This flag 382 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 386 at EL2 and below, and context switch relevant registers. This flag 387 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 391 allow use of Guarded Control Stack from EL2 as well as adding the GCS 392 registers to the EL2 context save/restore operations. This flag can take 393 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 394 Default value is ``0``. 395 396- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 397 support in GCC for TF-A. This option is currently only supported for 398 AArch64. Default is 0. 399 400- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 401 feature. MPAM is an optional Armv8.4 extension that enables various memory 402 system components and resources to define partitions; software running at 403 various ELs can assign themselves to desired partition to control their 404 performance aspects. 405 406 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 407 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 408 access their own MPAM registers without trapping into EL3. This option 409 doesn't make use of partitioning in EL3, however. Platform initialisation 410 code should configure and use partitions in EL3 as required. This option 411 defaults to ``0``. 412 413- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 414 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 415 firmware to detect and limit high activity events to assist in SoC processor 416 power domain dynamic power budgeting and limit the triggering of whole-rail 417 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 418 419- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 420 allows platforms with cores supporting MPMM to describe them via the 421 ``HW_CONFIG`` device tree blob. Default is 0. 422 423- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 424 support within generic code in TF-A. This option is currently only supported 425 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 426 in BL32 (SP_min) for AARCH32. Default is 0. 427 428- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 429 Measurement Framework(PMF). Default is 0. 430 431- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 432 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 433 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 434 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 435 software. 436 437- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 438 Management Extension. This flag can take the values 0 to 2, to align with 439 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 440 an experimental feature. 441 442- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 443 instrumentation which injects timestamp collection points into TF-A to 444 allow runtime performance to be measured. Currently, only PSCI is 445 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 446 as well. Default is 0. 447 448- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 449 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 450 registers so are enabled together. Using this option without 451 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 452 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 453 superset of SVE. SME is an optional architectural feature for AArch64 454 and TF-A support is experimental. At this time, this build option cannot be 455 used on systems that have SPD=spmd/SPM_MM and atempting to build with this 456 option will fail. This flag can take the values 0 to 2, to align with the 457 ``FEATURE_DETECTION`` mechanism. Default is 0. 458 459- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 460 version 2 (SME2) for the non-secure world only. SME2 is an optional 461 architectural feature for AArch64 and TF-A support is experimental. 462 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 463 accesses will still be trapped. This flag can take the values 0 to 2, to 464 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 465 466- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 467 Extension for secure world. Used along with SVE and FPU/SIMD. 468 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 469 This is experimental. Default is 0. 470 471- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 472 extensions. This is an optional architectural feature for AArch64. 473 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 474 mechanism. The default is 2 but is automatically disabled when the target 475 architecture is AArch32. 476 477- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 478 (SVE) for the Non-secure world only. SVE is an optional architectural feature 479 for AArch64. Note that when SVE is enabled for the Non-secure world, access 480 to SIMD and floating-point functionality from the Secure world is disabled by 481 default and controlled with ENABLE_SVE_FOR_SWD. 482 This is to avoid corruption of the Non-secure world data in the Z-registers 483 which are aliased by the SIMD and FP registers. The build option is not 484 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 485 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 486 enabled. This flag can take the values 0 to 2, to align with the 487 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 488 used on systems that have SPM_MM enabled. The default is 1. 489 490- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 491 SVE is an optional architectural feature for AArch64. Note that this option 492 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 493 automatically disabled when the target architecture is AArch32. 494 495- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 496 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 497 default value is set to "none". "strong" is the recommended stack protection 498 level if this feature is desired. "none" disables the stack protection. For 499 all values other than "none", the ``plat_get_stack_protector_canary()`` 500 platform hook needs to be implemented. The value is passed as the last 501 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 502 503- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 504 flag depends on ``DECRYPTION_SUPPORT`` build flag. 505 506- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 507 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 508 509- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 510 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 511 on ``DECRYPTION_SUPPORT`` build flag. 512 513- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 514 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 515 build flag. 516 517- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 518 deprecated platform APIs, helper functions or drivers within Trusted 519 Firmware as error. It can take the value 1 (flag the use of deprecated 520 APIs as error) or 0. The default is 0. 521 522- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 523 configure an Arm® Ethos™-N NPU. To use this service the target platform's 524 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 525 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 526 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 527 528- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 529 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 530 ``TRUSTED_BOARD_BOOT`` to be enabled. 531 532- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 533 (```ethosn.bin```). This firmware image will be included in the FIP and 534 loaded at runtime. 535 536- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 537 targeted at EL3. When set ``0`` (default), no exceptions are expected or 538 handled at EL3, and a panic will result. The exception to this rule is when 539 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 540 occuring during normal world execution, are trapped to EL3. Any exception 541 trapped during secure world execution are trapped to the SPMC. This is 542 supported only for AArch64 builds. 543 544- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 545 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 546 Default value is 40 (LOG_LEVEL_INFO). 547 548- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 549 injection from lower ELs, and this build option enables lower ELs to use 550 Error Records accessed via System Registers to inject faults. This is 551 applicable only to AArch64 builds. 552 553 This feature is intended for testing purposes only, and is advisable to keep 554 disabled for production images. 555 556- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 557 detection mechanism. It detects whether the Architectural features enabled 558 through feature specific build flags are supported by the PE or not by 559 validating them either at boot phase or at runtime based on the value 560 possessed by the feature flag (0 to 2) and report error messages at an early 561 stage. This flag will also enable errata ordering checking for ``DEBUG`` 562 builds. 563 564 This prevents and benefits us from EL3 runtime exceptions during context save 565 and restore routines guarded by these build flags. Henceforth validating them 566 before their usage provides more control on the actions taken under them. 567 568 The mechanism permits the build flags to take values 0, 1 or 2 and 569 evaluates them accordingly. 570 571 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 572 573 :: 574 575 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 576 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 577 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 578 579 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 580 0, feature is disabled statically during compilation. If it is defined as 1, 581 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 582 implemented by the PE, a hard panic is generated. Finally, if the flag is set 583 to 2, feature is validated at runtime. 584 585 Note that the entire implementation is divided into two phases, wherein as 586 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 587 supported and is planned to be handled explicilty in phase-2 implementation. 588 589 FEATURE_DETECTION macro is disabled by default, and is currently an 590 experimental procedure. Platforms can explicitly make use of this by 591 mechanism, by enabling it to validate whether they have set their build flags 592 properly at an early phase. 593 594- ``FIP_NAME``: This is an optional build option which specifies the FIP 595 filename for the ``fip`` target. Default is ``fip.bin``. 596 597- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 598 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 599 600- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 601 602 :: 603 604 0: Encryption is done with Secret Symmetric Key (SSK) which is common 605 for a class of devices. 606 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 607 unique per device. 608 609 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 610 611- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 612 tool to create certificates as per the Chain of Trust described in 613 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 614 include the certificates in the FIP and FWU_FIP. Default value is '0'. 615 616 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 617 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 618 the corresponding certificates, and to include those certificates in the 619 FIP and FWU_FIP. 620 621 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 622 images will not include support for Trusted Board Boot. The FIP will still 623 include the corresponding certificates. This FIP can be used to verify the 624 Chain of Trust on the host machine through other mechanisms. 625 626 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 627 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 628 will not include the corresponding certificates, causing a boot failure. 629 630- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 631 inherent support for specific EL3 type interrupts. Setting this build option 632 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 633 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 634 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 635 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 636 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 637 the Secure Payload interrupts needs to be synchronously handed over to Secure 638 EL1 for handling. The default value of this option is ``0``, which means the 639 Group 0 interrupts are assumed to be handled by Secure EL1. 640 641- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 642 Interrupts, resulting from errors in NS world, will be always trapped in 643 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 644 will be trapped in the current exception level (or in EL1 if the current 645 exception level is EL0). 646 647- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 648 software operations are required for CPUs to enter and exit coherency. 649 However, newer systems exist where CPUs' entry to and exit from coherency 650 is managed in hardware. Such systems require software to only initiate these 651 operations, and the rest is managed in hardware, minimizing active software 652 management. In such systems, this boolean option enables TF-A to carry out 653 build and run-time optimizations during boot and power management operations. 654 This option defaults to 0 and if it is enabled, then it implies 655 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 656 657 If this flag is disabled while the platform which TF-A is compiled for 658 includes cores that manage coherency in hardware, then a compilation error is 659 generated. This is based on the fact that a system cannot have, at the same 660 time, cores that manage coherency in hardware and cores that don't. In other 661 words, a platform cannot have, at the same time, cores that require 662 ``HW_ASSISTED_COHERENCY=1`` and cores that require 663 ``HW_ASSISTED_COHERENCY=0``. 664 665 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 666 translation library (xlat tables v2) must be used; version 1 of translation 667 library is not supported. 668 669- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 670 implementation defined system register accesses from lower ELs. Default 671 value is ``0``. 672 673- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 674 bottom, higher addresses at the top. This build flag can be set to '1' to 675 invert this behavior. Lower addresses will be printed at the top and higher 676 addresses at the bottom. 677 678- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 679 used for generating the PKCS keys and subsequent signing of the certificate. 680 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 681 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 682 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 683 compatibility. The default value of this flag is ``rsa`` which is the TBBR 684 compliant PKCS#1 RSA 2.1 scheme. 685 686- ``KEY_SIZE``: This build flag enables the user to select the key size for 687 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 688 depend on the chosen algorithm and the cryptographic module. 689 690 +---------------------------+------------------------------------+ 691 | KEY_ALG | Possible key sizes | 692 +===========================+====================================+ 693 | rsa | 1024 , 2048 (default), 3072, 4096* | 694 +---------------------------+------------------------------------+ 695 | ecdsa | unavailable | 696 +---------------------------+------------------------------------+ 697 | ecdsa-brainpool-regular | unavailable | 698 +---------------------------+------------------------------------+ 699 | ecdsa-brainpool-twisted | unavailable | 700 +---------------------------+------------------------------------+ 701 702 703 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 704 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 705 706- ``HASH_ALG``: This build flag enables the user to select the secure hash 707 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 708 The default value of this flag is ``sha256``. 709 710- ``LDFLAGS``: Extra user options appended to the linkers' command line in 711 addition to the one set by the build system. 712 713- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 714 output compiled into the build. This should be one of the following: 715 716 :: 717 718 0 (LOG_LEVEL_NONE) 719 10 (LOG_LEVEL_ERROR) 720 20 (LOG_LEVEL_NOTICE) 721 30 (LOG_LEVEL_WARNING) 722 40 (LOG_LEVEL_INFO) 723 50 (LOG_LEVEL_VERBOSE) 724 725 All log output up to and including the selected log level is compiled into 726 the build. The default value is 40 in debug builds and 20 in release builds. 727 728- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 729 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 730 provide trust that the code taking the measurements and recording them has 731 not been tampered with. 732 733 This option defaults to 0. 734 735- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 736 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 737 the measurements and recording them as per `PSA DRTM specification`_. For 738 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 739 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 740 should have mechanism to authenticate BL31. This is an experimental feature. 741 742 This option defaults to 0. 743 744- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 745 options to the compiler. An example usage: 746 747 .. code:: make 748 749 MARCH_DIRECTIVE := -march=armv8.5-a 750 751- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 752 specifies a file that contains the Non-Trusted World private key in PEM 753 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 754 will be used to save the key. 755 756- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 757 optional. It is only needed if the platform makefile specifies that it 758 is required in order to build the ``fwu_fip`` target. 759 760- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 761 contents upon world switch. It can take either 0 (don't save and restore) or 762 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 763 wants the timer registers to be saved and restored. 764 765- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 766 tb_fw_config device tree. This flag is defined only when 767 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 768 769- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 770 for the BL image. It can be either 0 (include) or 1 (remove). The default 771 value is 0. 772 773- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 774 the underlying hardware is not a full PL011 UART but a minimally compliant 775 generic UART, which is a subset of the PL011. The driver will not access 776 any register that is not part of the SBSA generic UART specification. 777 Default value is 0 (a full PL011 compliant UART is present). 778 779- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 780 must be subdirectory of any depth under ``plat/``, and must contain a 781 platform makefile named ``platform.mk``. For example, to build TF-A for the 782 Arm Juno board, select PLAT=juno. 783 784- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 785 instead of the normal boot flow. When defined, it must specify the entry 786 point address for the preloaded BL33 image. This option is incompatible with 787 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 788 over ``PRELOADED_BL33_BASE``. 789 790- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 791 vector address can be programmed or is fixed on the platform. It can take 792 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 793 programmable reset address, it is expected that a CPU will start executing 794 code directly at the right address, both on a cold and warm reset. In this 795 case, there is no need to identify the entrypoint on boot and the boot path 796 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 797 does not need to be implemented in this case. 798 799- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 800 possible for the PSCI power-state parameter: original and extended State-ID 801 formats. This flag if set to 1, configures the generic PSCI layer to use the 802 extended format. The default value of this flag is 0, which means by default 803 the original power-state format is used by the PSCI implementation. This flag 804 should be specified by the platform makefile and it governs the return value 805 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 806 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 807 set to 1 as well. 808 809- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 810 OS-initiated mode. This option defaults to 0. 811 812- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features 813 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 814 or later CPUs. This flag can take the values 0 to 2, to align with the 815 ``FEATURE_DETECTION`` mechanism. 816 817- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors 818 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, 819 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. 820 821- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 822 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 823 entrypoint) or 1 (CPU reset to BL31 entrypoint). 824 The default value is 0. 825 826- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 827 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 828 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 829 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 830 831- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 832 file that contains the ROT private key in PEM format or a PKCS11 URI and 833 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 834 accepted and it will be used to save the key. 835 836- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 837 certificate generation tool to save the keys used to establish the Chain of 838 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 839 840- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 841 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 842 target. 843 844- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 845 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 846 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 847 848- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 849 optional. It is only needed if the platform makefile specifies that it 850 is required in order to build the ``fwu_fip`` target. 851 852- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 853 Delegated Exception Interface to BL31 image. This defaults to ``0``. 854 855 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 856 set to ``1``. 857 858- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 859 isolated on separate memory pages. This is a trade-off between security and 860 memory usage. See "Isolating code and read-only data on separate memory 861 pages" section in :ref:`Firmware Design`. This flag is disabled by default 862 and affects all BL images. 863 864- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 865 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 866 allocated in RAM discontiguous from the loaded firmware image. When set, the 867 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 868 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 869 sections are placed in RAM immediately following the loaded firmware image. 870 871- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 872 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 873 discontiguous from loaded firmware images. When set, the platform need to 874 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 875 flag is disabled by default and NOLOAD sections are placed in RAM immediately 876 following the loaded firmware image. 877 878- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 879 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 880 UEFI+ACPI this can provide a certain amount of OS forward compatibility 881 with newer platforms that aren't ECAM compliant. 882 883- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 884 This build option is only valid if ``ARCH=aarch64``. The value should be 885 the path to the directory containing the SPD source, relative to 886 ``services/spd/``; the directory is expected to contain a makefile called 887 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 888 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 889 cannot be enabled when the ``SPM_MM`` option is enabled. 890 891- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 892 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 893 execution in BL1 just before handing over to BL31. At this point, all 894 firmware images have been loaded in memory, and the MMU and caches are 895 turned off. Refer to the "Debugging options" section for more details. 896 897- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 898 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 899 component runs at the EL3 exception level. The default value is ``0`` ( 900 disabled). This configuration supports pre-Armv8.4 platforms (aka not 901 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 902 903- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 904 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 905 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 906 907- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 908 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 909 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 910 mechanism should be used. 911 912- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 913 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 914 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 915 extension. This is the default when enabling the SPM Dispatcher. When 916 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 917 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 918 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 919 extension). 920 921- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 922 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 923 for logical partitions in EL3, managed by the SPMD as defined in the FF-A 924 1.2 specification. This flag is disabled by default. This flag must not be 925 used if ``SPMC_AT_EL3`` is enabled. This is an experimental feature. 926 927- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 928 Partition Manager (SPM) implementation. The default value is ``0`` 929 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 930 enabled (``SPD=spmd``). 931 932- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 933 description of secure partitions. The build system will parse this file and 934 package all secure partition blobs into the FIP. This file is not 935 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 936 937- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 938 secure interrupts (caught through the FIQ line). Platforms can enable 939 this directive if they need to handle such interruption. When enabled, 940 the FIQ are handled in monitor mode and non secure world is not allowed 941 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 942 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 943 944- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 945 Platforms can configure this if they need to lower the hardware 946 limit, for example due to asymmetric configuration or limitations of 947 software run at lower ELs. The default is the architectural maximum 948 of 2048 which should be suitable for most configurations, the 949 hardware will limit the effective VL to the maximum physically supported 950 VL. 951 952- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 953 Handoff using Transfer List defined in `Firmware Handoff specification`_. 954 This defaults to ``0``. Please note that this is an experimental feature 955 based on Firmware Handoff specification v0.9. 956 957- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 958 Random Number Generator Interface to BL31 image. This defaults to ``0``. 959 960- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 961 Boot feature. When set to '1', BL1 and BL2 images include support to load 962 and verify the certificates and images in a FIP, and BL1 includes support 963 for the Firmware Update. The default value is '0'. Generation and inclusion 964 of certificates in the FIP and FWU_FIP depends upon the value of the 965 ``GENERATE_COT`` option. 966 967 .. warning:: 968 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 969 already exist in disk, they will be overwritten without further notice. 970 971- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 972 specifies a file that contains the Trusted World private key in PEM 973 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 974 it will be used to save the key. 975 976- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 977 synchronous, (see "Initializing a BL32 Image" section in 978 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 979 synchronous method) or 1 (BL32 is initialized using asynchronous method). 980 Default is 0. 981 982- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 983 routing model which routes non-secure interrupts asynchronously from TSP 984 to EL3 causing immediate preemption of TSP. The EL3 is responsible 985 for saving and restoring the TSP context in this routing model. The 986 default routing model (when the value is 0) is to route non-secure 987 interrupts to TSP allowing it to save its context and hand over 988 synchronously to EL3 via an SMC. 989 990 .. note:: 991 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 992 must also be set to ``1``. 993 994- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 995 internal-trusted-storage) as SP in tb_fw_config device tree. 996 997- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 998 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 999 this delay. It can take values in the range (0-15). Default value is ``0`` 1000 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1001 Platforms need to explicitly update this value based on their requirements. 1002 1003- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1004 linker. When the ``LINKER`` build variable points to the armlink linker, 1005 this flag is enabled automatically. To enable support for armlink, platforms 1006 will have to provide a scatter file for the BL image. Currently, Tegra 1007 platforms use the armlink support to compile BL3-1 images. 1008 1009- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1010 memory region in the BL memory map or not (see "Use of Coherent memory in 1011 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1012 (Coherent memory region is included) or 0 (Coherent memory region is 1013 excluded). Default is 1. 1014 1015- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 1016 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 1017 Default is 0. 1018 1019- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1020 firmware configuration framework. This will move the io_policies into a 1021 configuration device tree, instead of static structure in the code base. 1022 1023- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1024 at runtime using fconf. If this flag is enabled, COT descriptors are 1025 statically captured in tb_fw_config file in the form of device tree nodes 1026 and properties. Currently, COT descriptors used by BL2 are moved to the 1027 device tree and COT descriptors used by BL1 are retained in the code 1028 base statically. 1029 1030- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1031 runtime using firmware configuration framework. The platform specific SDEI 1032 shared and private events configuration is retrieved from device tree rather 1033 than static C structures at compile time. This is only supported if 1034 SDEI_SUPPORT build flag is enabled. 1035 1036- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1037 and Group1 secure interrupts using the firmware configuration framework. The 1038 platform specific secure interrupt property descriptor is retrieved from 1039 device tree in runtime rather than depending on static C structure at compile 1040 time. 1041 1042- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1043 This feature creates a library of functions to be placed in ROM and thus 1044 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1045 is 0. 1046 1047- ``V``: Verbose build. If assigned anything other than 0, the build commands 1048 are printed. Default is 0. 1049 1050- ``VERSION_STRING``: String used in the log output for each TF-A image. 1051 Defaults to a string formed by concatenating the version number, build type 1052 and build string. 1053 1054- ``W``: Warning level. Some compiler warning options of interest have been 1055 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1056 each level enabling more warning options. Default is 0. 1057 1058 This option is closely related to the ``E`` option, which enables 1059 ``-Werror``. 1060 1061 - ``W=0`` (default) 1062 1063 Enables a wide assortment of warnings, most notably ``-Wall`` and 1064 ``-Wextra``, as well as various bad practices and things that are likely to 1065 result in errors. Includes some compiler specific flags. No warnings are 1066 expected at this level for any build. 1067 1068 - ``W=1`` 1069 1070 Enables warnings we want the generic build to include but are too time 1071 consuming to fix at the moment. It re-enables warnings taken out for 1072 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1073 to eventually be merged into ``W=0``. Some warnings are expected on some 1074 builds, but new contributions should not introduce new ones. 1075 1076 - ``W=2`` (recommended) 1077 1078 Enables warnings we want the generic build to include but cannot be enabled 1079 due to external libraries. This level is expected to eventually be merged 1080 into ``W=0``. Lots of warnings are expected, primarily from external 1081 libraries like zlib and compiler-rt, but new controbutions should not 1082 introduce new ones. 1083 1084 - ``W=3`` 1085 1086 Enables warnings that are informative but not necessary and generally too 1087 verbose and frequently ignored. A very large number of warnings are 1088 expected. 1089 1090 The exact set of warning flags depends on the compiler and TF-A warning 1091 level, however they are all succinctly set in the top-level Makefile. Please 1092 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1093 individual flags. 1094 1095- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1096 the CPU after warm boot. This is applicable for platforms which do not 1097 require interconnect programming to enable cache coherency (eg: single 1098 cluster platforms). If this option is enabled, then warm boot path 1099 enables D-caches immediately after enabling MMU. This option defaults to 0. 1100 1101- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1102 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1103 default value of this flag is ``no``. Note this option must be enabled only 1104 for ARM architecture greater than Armv8.5-A. 1105 1106- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1107 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1108 The default value of this flag is ``0``. 1109 1110 ``AT`` speculative errata workaround disables stage1 page table walk for 1111 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1112 produces either the correct result or failure without TLB allocation. 1113 1114 This boolean option enables errata for all below CPUs. 1115 1116 +---------+--------------+-------------------------+ 1117 | Errata | CPU | Workaround Define | 1118 +=========+==============+=========================+ 1119 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1120 +---------+--------------+-------------------------+ 1121 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1122 +---------+--------------+-------------------------+ 1123 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1124 +---------+--------------+-------------------------+ 1125 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1126 +---------+--------------+-------------------------+ 1127 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1128 +---------+--------------+-------------------------+ 1129 1130 .. note:: 1131 This option is enabled by build only if platform sets any of above defines 1132 mentioned in ’Workaround Define' column in the table. 1133 If this option is enabled for the EL3 software then EL2 software also must 1134 implement this workaround due to the behaviour of the errata mentioned 1135 in new SDEN document which will get published soon. 1136 1137- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1138 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1139 This flag is disabled by default. 1140 1141- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1142 host machine where a custom installation of OpenSSL is located, which is used 1143 to build the certificate generation, firmware encryption and FIP tools. If 1144 this option is not set, the default OS installation will be used. 1145 1146- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1147 functions that wait for an arbitrary time length (udelay and mdelay). The 1148 default value is 0. 1149 1150- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1151 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1152 optional architectural feature for AArch64. This flag can take the values 1153 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1154 and it is automatically disabled when the target architecture is AArch32. 1155 1156- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1157 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1158 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1159 feature for AArch64. This flag can take the values 0 to 2, to align with the 1160 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1161 disabled when the target architecture is AArch32. 1162 1163- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1164 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1165 but unused). This feature is available if trace unit such as ETMv4.x, and 1166 ETE(extending ETM feature) is implemented. This flag can take the values 1167 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1168 1169- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1170 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1171 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1172 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1173 1174- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1175 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1176 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1177 The default value is 0. 1178 1179- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1180 ``plat_can_cmo`` which will return zero if cache management operations should 1181 be skipped and non-zero otherwise. By default, this option is disabled which 1182 means platform hook won't be checked and CMOs will always be performed when 1183 related functions are called. 1184 1185- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1186 firmware interface for the BL31 image. By default its disabled (``0``). 1187 1188- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1189 errata mitigation for platforms with a non-arm interconnect using the errata 1190 ABI. By default its disabled (``0``). 1191 1192- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1193 The platform will use PSA compliant Crypto APIs during authentication and 1194 image measurement process by enabling this option. It uses APIs defined as 1195 per the `PSA Crypto API specification`_. This feature is only supported if 1196 using MbedTLS 3.x version. By default it is disabled (``0``). 1197 1198- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1199 driver(s). By default it is disabled (``0``) because it constitutes an attack 1200 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1201 This option should only be enabled on a need basis if there is a use case for 1202 reading characters from the console. 1203 1204GICv3 driver options 1205-------------------- 1206 1207GICv3 driver files are included using directive: 1208 1209``include drivers/arm/gic/v3/gicv3.mk`` 1210 1211The driver can be configured with the following options set in the platform 1212makefile: 1213 1214- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1215 Enabling this option will add runtime detection support for the 1216 GIC-600, so is safe to select even for a GIC500 implementation. 1217 This option defaults to 0. 1218 1219- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1220 for GIC-600 AE. Enabling this option will introduce support to initialize 1221 the FMU. Platforms should call the init function during boot to enable the 1222 FMU and its safety mechanisms. This option defaults to 0. 1223 1224- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1225 functionality. This option defaults to 0 1226 1227- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1228 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1229 functions. This is required for FVP platform which need to simulate GIC save 1230 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1231 1232- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1233 This option defaults to 0. 1234 1235- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1236 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1237 1238Debugging options 1239----------------- 1240 1241To compile a debug version and make the build more verbose use 1242 1243.. code:: shell 1244 1245 make PLAT=<platform> DEBUG=1 V=1 all 1246 1247AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1248(for example Arm-DS) might not support this and may need an older version of 1249DWARF symbols to be emitted by GCC. This can be achieved by using the 1250``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1251the version to 4 is recommended for Arm-DS. 1252 1253When debugging logic problems it might also be useful to disable all compiler 1254optimizations by using ``-O0``. 1255 1256.. warning:: 1257 Using ``-O0`` could cause output images to be larger and base addresses 1258 might need to be recalculated (see the **Memory layout on Arm development 1259 platforms** section in the :ref:`Firmware Design`). 1260 1261Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1262``LDFLAGS``: 1263 1264.. code:: shell 1265 1266 CFLAGS='-O0 -gdwarf-2' \ 1267 make PLAT=<platform> DEBUG=1 V=1 all 1268 1269Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1270ignored as the linker is called directly. 1271 1272It is also possible to introduce an infinite loop to help in debugging the 1273post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1274``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1275section. In this case, the developer may take control of the target using a 1276debugger when indicated by the console output. When using Arm-DS, the following 1277commands can be used: 1278 1279:: 1280 1281 # Stop target execution 1282 interrupt 1283 1284 # 1285 # Prepare your debugging environment, e.g. set breakpoints 1286 # 1287 1288 # Jump over the debug loop 1289 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1290 1291 # Resume execution 1292 continue 1293 1294Firmware update options 1295----------------------- 1296 1297- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1298 in defining the firmware update metadata structure. This flag is by default 1299 set to '2'. 1300 1301- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1302 firmware bank. Each firmware bank must have the same number of images as per 1303 the `PSA FW update specification`_. 1304 This flag is used in defining the firmware update metadata structure. This 1305 flag is by default set to '1'. 1306 1307- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1308 `PSA FW update specification`_. The default value is 0, and this is an 1309 experimental feature. 1310 PSA firmware update implementation has some limitations, such as BL2 is 1311 not part of the protocol-updatable images, if BL2 needs to be updated, then 1312 it should be done through another platform-defined mechanism, and it assumes 1313 that the platform's hardware supports CRC32 instructions. 1314 1315-------------- 1316 1317*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1318 1319.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1320.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1321.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1322.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1323.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1324.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1325.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1326