1 /* 2 * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CPG_REGISTERS_H 8 #define CPG_REGISTERS_H 9 10 /* CPG base address */ 11 #define CPG_BASE (0xE6150000U) 12 13 /* CPG system module stop control 2 */ 14 #define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) 15 /* CPG software reset 2 */ 16 #define CPG_SRCR2 (CPG_BASE + 0x00B0U) 17 /* CPG module stop status 2 */ 18 #define CPG_MSTPSR2 (CPG_BASE + 0x0040U) 19 /* CPG system module stop control 3 */ 20 #define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) 21 /* CPG module stop status 3 */ 22 #define CPG_MSTPSR3 (CPG_BASE + 0x0048U) 23 /* CPG write protect */ 24 #define CPG_CPGWPR (CPG_BASE + 0x0900U) 25 /* CPG write protect control */ 26 #define CPG_CPGWPCR (CPG_BASE + 0x0904U) 27 /* CPG system module stop control 9 */ 28 #define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) 29 /* CPG module stop status 9 */ 30 #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) 31 /* SDHI2 clock frequency control register */ 32 #define CPG_SD2CKCR (CPG_BASE + 0x0268U) 33 /* SDHI3 clock frequency control register */ 34 #define CPG_SD3CKCR (CPG_BASE + 0x026CU) 35 36 /* CPG (SECURITY) registers */ 37 38 /* Secure Module Stop Control Register 0 */ 39 #define SCMSTPCR0 (CPG_BASE + 0x0B20U) 40 /* Secure Module Stop Control Register 1 */ 41 #define SCMSTPCR1 (CPG_BASE + 0x0B24U) 42 /* Secure Module Stop Control Register 2 */ 43 #define SCMSTPCR2 (CPG_BASE + 0x0B28U) 44 /* Secure Module Stop Control Register 3 */ 45 #define SCMSTPCR3 (CPG_BASE + 0x0B2CU) 46 /* Secure Module Stop Control Register 4 */ 47 #define SCMSTPCR4 (CPG_BASE + 0x0B30U) 48 /* Secure Module Stop Control Register 5 */ 49 #define SCMSTPCR5 (CPG_BASE + 0x0B34U) 50 /* Secure Module Stop Control Register 6 */ 51 #define SCMSTPCR6 (CPG_BASE + 0x0B38U) 52 /* Secure Module Stop Control Register 7 */ 53 #define SCMSTPCR7 (CPG_BASE + 0x0B3CU) 54 /* Secure Module Stop Control Register 8 */ 55 #define SCMSTPCR8 (CPG_BASE + 0x0B40U) 56 /* Secure Module Stop Control Register 9 */ 57 #define SCMSTPCR9 (CPG_BASE + 0x0B44U) 58 /* Secure Module Stop Control Register 10 */ 59 #define SCMSTPCR10 (CPG_BASE + 0x0B48U) 60 /* Secure Module Stop Control Register 11 */ 61 #define SCMSTPCR11 (CPG_BASE + 0x0B4CU) 62 63 /* CPG (SECURITY) registers */ 64 65 /* Secure Software Reset Access Enable Control Register 0 */ 66 #define SCSRSTECR0 (CPG_BASE + 0x0B80U) 67 /* Secure Software Reset Access Enable Control Register 1 */ 68 #define SCSRSTECR1 (CPG_BASE + 0x0B84U) 69 /* Secure Software Reset Access Enable Control Register 2 */ 70 #define SCSRSTECR2 (CPG_BASE + 0x0B88U) 71 /* Secure Software Reset Access Enable Control Register 3 */ 72 #define SCSRSTECR3 (CPG_BASE + 0x0B8CU) 73 /* Secure Software Reset Access Enable Control Register 4 */ 74 #define SCSRSTECR4 (CPG_BASE + 0x0B90U) 75 /* Secure Software Reset Access Enable Control Register 5 */ 76 #define SCSRSTECR5 (CPG_BASE + 0x0B94U) 77 /* Secure Software Reset Access Enable Control Register 6 */ 78 #define SCSRSTECR6 (CPG_BASE + 0x0B98U) 79 /* Secure Software Reset Access Enable Control Register 7 */ 80 #define SCSRSTECR7 (CPG_BASE + 0x0B9CU) 81 /* Secure Software Reset Access Enable Control Register 8 */ 82 #define SCSRSTECR8 (CPG_BASE + 0x0BA0U) 83 /* Secure Software Reset Access Enable Control Register 9 */ 84 #define SCSRSTECR9 (CPG_BASE + 0x0BA4U) 85 /* Secure Software Reset Access Enable Control Register 10 */ 86 #define SCSRSTECR10 (CPG_BASE + 0x0BA8U) 87 /* Secure Software Reset Access Enable Control Register 11 */ 88 #define SCSRSTECR11 (CPG_BASE + 0x0BACU) 89 90 /* CPG (REALTIME) registers */ 91 92 /* Realtime Module Stop Control Register 0 */ 93 #define RMSTPCR0 (CPG_BASE + 0x0110U) 94 /* Realtime Module Stop Control Register 1 */ 95 #define RMSTPCR1 (CPG_BASE + 0x0114U) 96 /* Realtime Module Stop Control Register 2 */ 97 #define RMSTPCR2 (CPG_BASE + 0x0118U) 98 /* Realtime Module Stop Control Register 3 */ 99 #define RMSTPCR3 (CPG_BASE + 0x011CU) 100 /* Realtime Module Stop Control Register 4 */ 101 #define RMSTPCR4 (CPG_BASE + 0x0120U) 102 /* Realtime Module Stop Control Register 5 */ 103 #define RMSTPCR5 (CPG_BASE + 0x0124U) 104 /* Realtime Module Stop Control Register 6 */ 105 #define RMSTPCR6 (CPG_BASE + 0x0128U) 106 /* Realtime Module Stop Control Register 7 */ 107 #define RMSTPCR7 (CPG_BASE + 0x012CU) 108 /* Realtime Module Stop Control Register 8 */ 109 #define RMSTPCR8 (CPG_BASE + 0x0980U) 110 /* Realtime Module Stop Control Register 9 */ 111 #define RMSTPCR9 (CPG_BASE + 0x0984U) 112 /* Realtime Module Stop Control Register 10 */ 113 #define RMSTPCR10 (CPG_BASE + 0x0988U) 114 /* Realtime Module Stop Control Register 11 */ 115 #define RMSTPCR11 (CPG_BASE + 0x098CU) 116 117 /* CPG (SYSTEM) registers */ 118 119 /* System Module Stop Control Register 0 */ 120 #define SMSTPCR0 (CPG_BASE + 0x0130U) 121 /* System Module Stop Control Register 1 */ 122 #define SMSTPCR1 (CPG_BASE + 0x0134U) 123 /* System Module Stop Control Register 2 */ 124 #define SMSTPCR2 (CPG_BASE + 0x0138U) 125 /* System Module Stop Control Register 3 */ 126 #define SMSTPCR3 (CPG_BASE + 0x013CU) 127 /* System Module Stop Control Register 4 */ 128 #define SMSTPCR4 (CPG_BASE + 0x0140U) 129 /* System Module Stop Control Register 5 */ 130 #define SMSTPCR5 (CPG_BASE + 0x0144U) 131 /* System Module Stop Control Register 6 */ 132 #define SMSTPCR6 (CPG_BASE + 0x0148U) 133 /* System Module Stop Control Register 7 */ 134 #define SMSTPCR7 (CPG_BASE + 0x014CU) 135 /* System Module Stop Control Register 8 */ 136 #define SMSTPCR8 (CPG_BASE + 0x0990U) 137 /* System Module Stop Control Register 9 */ 138 #define SMSTPCR9 (CPG_BASE + 0x0994U) 139 /* System Module Stop Control Register 10 */ 140 #define SMSTPCR10 (CPG_BASE + 0x0998U) 141 /* System Module Stop Control Register 11 */ 142 #define SMSTPCR11 (CPG_BASE + 0x099CU) 143 144 #endif /* CPG_REGISTERS_H */ 145