1 /* 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/arm/dcc.h> 17 #include <drivers/console.h> 18 #include <lib/mmio.h> 19 #include <libfdt.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #include <custom_svc.h> 24 #include <plat_fdt.h> 25 #include <plat_private.h> 26 #include <plat_startup.h> 27 #include <zynqmp_def.h> 28 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 entry_point_info_t *next_image_info; 42 43 assert(sec_state_is_valid(type)); 44 if (type == NON_SECURE) { 45 next_image_info = &bl33_image_ep_info; 46 } else { 47 next_image_info = &bl32_image_ep_info; 48 } 49 50 return next_image_info; 51 } 52 53 /* 54 * Set the build time defaults. We want to do this when doing a JTAG boot 55 * or if we can't find any other config data. 56 */ 57 static inline void bl31_set_default_config(void) 58 { 59 bl32_image_ep_info.pc = BL32_BASE; 60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 61 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 62 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 63 DISABLE_ALL_EXCEPTIONS); 64 } 65 66 /* 67 * Perform any BL31 specific platform actions. Here is an opportunity to copy 68 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 69 * are lost (potentially). This needs to be done before the MMU is initialized 70 * so that the memory layout can be used while creating page tables. 71 */ 72 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 73 u_register_t arg2, u_register_t arg3) 74 { 75 uint64_t tfa_handoff_addr; 76 77 if (CONSOLE_IS(cadence) || (CONSOLE_IS(cadence1))) { 78 /* Register the console to provide early debug support */ 79 static console_t bl31_boot_console; 80 (void)console_cdns_register(UART_BASE, 81 get_uart_clk(), 82 UART_BAUDRATE, 83 &bl31_boot_console); 84 console_set_scope(&bl31_boot_console, 85 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT | 86 CONSOLE_FLAG_CRASH); 87 } else if (CONSOLE_IS(dcc)) { 88 /* Initialize the dcc console for debug */ 89 int32_t rc = console_dcc_register(); 90 if (rc == 0) { 91 panic(); 92 } 93 } else { 94 /* No console device found. */ 95 } 96 /* Initialize the platform config for future decision making */ 97 zynqmp_config_setup(); 98 99 /* 100 * Do initial security configuration to allow DRAM/device access. On 101 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 102 * other platforms might have more programmable security devices 103 * present. 104 */ 105 106 /* Populate common information for BL32 and BL33 */ 107 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 108 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 109 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 110 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 111 112 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 113 114 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 115 bl31_set_default_config(); 116 } else { 117 /* use parameters from XBL */ 118 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 119 &bl33_image_ep_info, 120 tfa_handoff_addr); 121 if (ret != XBL_HANDOFF_SUCCESS) { 122 panic(); 123 } 124 } 125 if (bl32_image_ep_info.pc != 0) { 126 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 127 } 128 if (bl33_image_ep_info.pc != 0) { 129 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 130 } 131 132 custom_early_setup(); 133 134 } 135 136 #if ZYNQMP_WDT_RESTART 137 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 138 139 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 140 { 141 static uint32_t index; 142 uint32_t i; 143 144 /* Validate 'handler' and 'id' parameters */ 145 if (!handler || index >= MAX_INTR_EL3) { 146 return -EINVAL; 147 } 148 149 /* Check if a handler has already been registered */ 150 for (i = 0; i < index; i++) { 151 if (id == type_el3_interrupt_table[i].id) { 152 return -EALREADY; 153 } 154 } 155 156 type_el3_interrupt_table[index].id = id; 157 type_el3_interrupt_table[index].handler = handler; 158 159 index++; 160 161 return 0; 162 } 163 164 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 165 void *handle, void *cookie) 166 { 167 uint32_t intr_id; 168 uint32_t i; 169 interrupt_type_handler_t handler = NULL; 170 171 intr_id = plat_ic_get_pending_interrupt_id(); 172 173 for (i = 0; i < MAX_INTR_EL3; i++) { 174 if (intr_id == type_el3_interrupt_table[i].id) { 175 handler = type_el3_interrupt_table[i].handler; 176 } 177 } 178 179 if (handler != NULL) { 180 return handler(intr_id, flags, handle, cookie); 181 } 182 183 return 0; 184 } 185 #endif 186 187 void bl31_platform_setup(void) 188 { 189 prepare_dtb(); 190 191 /* Initialize the gic cpu and distributor interfaces */ 192 plat_arm_gic_driver_init(); 193 plat_arm_gic_init(); 194 } 195 196 void bl31_plat_runtime_setup(void) 197 { 198 #if ZYNQMP_WDT_RESTART 199 uint64_t flags = 0; 200 uint64_t rc; 201 202 set_interrupt_rm_flag(flags, NON_SECURE); 203 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 204 rdo_el3_interrupt_handler, flags); 205 if (rc) { 206 panic(); 207 } 208 #endif 209 210 custom_runtime_setup(); 211 } 212 213 /* 214 * Perform the very early platform specific architectural setup here. 215 */ 216 void bl31_plat_arch_setup(void) 217 { 218 plat_arm_interconnect_init(); 219 plat_arm_interconnect_enter_coherency(); 220 221 const mmap_region_t bl_regions[] = { 222 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 223 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 224 MT_MEMORY | MT_RW | MT_NS), 225 #endif 226 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 227 MT_MEMORY | MT_RW | MT_SECURE), 228 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 229 MT_CODE | MT_SECURE), 230 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 231 MT_RO_DATA | MT_SECURE), 232 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 233 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 234 MT_DEVICE | MT_RW | MT_SECURE), 235 {0} 236 }; 237 238 custom_mmap_add(); 239 240 setup_page_tables(bl_regions, plat_arm_get_mmap()); 241 enable_mmu_el3(0); 242 } 243